Abstract: A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.

Abstract: A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; depositing a second conformal layer on the first conformal layer; removing a portion of the second conformal layer to expose a portion of the first conformal layer; and thinning the first conformal layer and the second conformal layer alternatively to form a second pattern. A semiconductor self-aligned structure is also provided.

Abstract: A common mode filter monolithically integrated with a protection device. In accordance with an embodiment a semiconductor material having a resistivity of at least 5 Ohm-centimeters is provided. A protection device is formed from a portion of the semiconductor material and a dielectric material is formed over the semiconductor material. A coil is formed over the dielectric material.

Abstract: In one embodiment, a device includes a first conductive pad disposed over a substrate, and a etch stop layer disposed over a top surface of the first conductive pad. The device further includes a solder barrier disposed over the etch stop layer.

Abstract: A semiconductor module includes: a metal block; an insulation layer for heat radiation formed by directly depositing a ceramic material on at least a first surface of the metal block; an insulation layer for a relay electrode formed by directly depositing a ceramic material on a part of a second surface 1b of the metal block; a relay electrode formed by depositing a metal material on the upper surface of the insulation layer for the relay electrode; a circuit element bonded with the second surface of the metal block by solder; and an external lead terminal, wherein a bonding wire or a lead frame from the circuit element is bonded with the relay electrode, and the relay electrode and the external lead terminal are connected.

Abstract: An integrated passives package includes an encapsulation compound and a plurality of electrically conductive pads embedded in the encapsulation compound. Each of the pads has opposing first and second sides. The first side of the pads is uncovered by the encapsulation compound and forms array of external electrical connections at a first side of the package. The integrated passives package further includes a plurality of passive components embedded in the encapsulation compound. Each of the passive components has a first terminal attached to one of the pads and a second terminal attached to a different one the pads at the second side of the pads. Corresponding semiconductor modules and methods of manufacturing are also provided.

Abstract: According to the disclosure, a lead frame is provided, which includes: a first island and a second island that are arranged side by side; an outer peripheral frame; first leads that extend in a second direction perpendicular to the first direction; second leads that extend in the second direction; a first coupling portion that couples the first leads to the frame; a second coupling portion that couples the second leads to the frame; an intermediate portion formed between the first and second coupling portions in the first direction such that it extends in the second direction to terminate before the space between the first and second islands; and a deformation restraining portion formed or provided in at least one of the first leads, the second leads, the first and the second coupling portions and configured to restrain deformations of the first and second leads during a molding process.

Abstract: A semiconductor device includes a semiconductor element that is mounted on a substrate, an electrode pad that contains aluminum as a main component and is provided in the semiconductor element, a copper wire that contains copper as a main component and connects a connection terminal provided on the substrate and the electrode pad, and an encapsulant resin that encapsulates the semiconductor element and the copper wire. When the semiconductor device is heated at 200° C. for 16 hours in the atmosphere, a barrier layer containing any metal selected from palladium and platinum is farmed at a junction between the copper wire and the electrode pad.

Abstract: The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device has a plurality of power units placed in parallel in a predetermined direction, wherein each of the power units includes a plurality of semiconductor elements placed on a metal plate having predetermined gaps with each other. The semiconductor elements of each of the two power units include a near-sided semiconductor element that is closer to an inlet of the resin among the two semiconductor elements having the predetermined gap therebetween. A structure is positioned on a passage and downstream in a resin flow direction relative to a predetermined position that corresponds to end parts of the near-sided semiconductor elements. The structure is a joint to connect the two power units placed adjacent to each other in the predetermined direction, and to be integrally sealed with the resin, along with the power unit.

Abstract: A semiconductor device can reduce the number of bonding wires. The semiconductor device includes two or more semiconductor elements each of which has electrodes on a first main surface and a second main surface, an electrode plate that has one surface which is bonded to electrodes on the first main surfaces of the semiconductor elements, with a first bonding material layer interposed therebetween, and extends over the electrodes on the first main surfaces of the two or more semiconductor elements, and a conductive plate that includes a first lead terminal and a semiconductor element bonding portion which is bonded to electrodes on the second main surfaces of the semiconductor elements. A second bonding material layer is interposed therebetween, and is connected to the electrodes on the second main surfaces of the two or more semiconductor elements.

Abstract: A no-lead type semiconductor package has a mold cap that forms a mold body. The corners of the mold body are reinforced with mold columns such that the corners have rounded protrusions and do not form 90° angles. The mold columns prevent the corner pads from peeling.

Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Abstract: A silicon interconnect structure includes a peripheral outer via in a silicon substrate, a solid core inner via in the silicon substrate, the solid core inner via coaxial with the peripheral outer via to form a coaxial via structure, a metal interconnect stack formed over a first surface of the peripheral outer via and the solid core inner via, at least portions of the metal interconnect stack forming an electrical connection with the peripheral outer via and the solid core inner via, first contact pads on a surface of the metal interconnect stack, and second contact pads on an exposed surface of the peripheral outer via and the solid core inner via.

Abstract: A semiconductor device includes a semiconductor die and an encapsulant formed over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A plurality of conductive vias is formed through the first insulating layer. A conductive pad is formed over the encapsulant. An interconnect structure is formed over the semiconductor die and encapsulant. A first opening is formed in the encapsulant to expose the conductive vias. The conductive vias form a conductive via array. The conductive via array is inspected through the first opening to measure a dimension of the first opening and determine a position of the first opening. The semiconductor device is adjusted based on a position of the conductive via array. A conductive material is formed in the first opening over the conductive via array.

Abstract: The stacked package includes: a substrate having an upper surface formed with connection pads, a lower surface, and four side surfaces; a first semiconductor chip mounted over the upper surface of the substrate; a first adhesive member that covers a portion of the substrate including the first semiconductor chip; and a second semiconductor chip formed with bumps on edges of a first surface and mounted over the substrate with interposition of the first semiconductor chip and the first adhesive member such that a center of the first surface is attached over the first adhesive member and the bumps are bonded onto the connection pads, with a second surface opposing to the first surface being polished evenly.

Abstract: Stack packages are provided. The stack package includes a first chip and a second chip. The first chip includes a first chip body, first through electrodes penetrating the first chip body, and an insulation layer disposed on a bottom surface of the first chip body. The second chip includes a second chip body and bumps disposed on a top surface of the second chip body. The first and second chips are vertically stacked such that the bumps penetrate the insulation layer to pierce the first through electrodes and the top surface of the second chip body directly contacts the insulation layer. Related fabrication methods, electronic systems and memory cards are also provided.

Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.

Abstract: Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming one or more openings in a front side of the semiconductor device and forming sacrificial plugs in the openings that partially fill the openings. The method further includes further filling the partially filled openings with a conductive material, where individual sacrificial plugs are generally between the conductive material and a substrate of the semiconductor device. The sacrificial plugs are exposed at a backside of the semiconductor device. Contact regions can be formed at the backside by removing the sacrificial plugs.

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

Abstract: A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion.

Abstract: The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.

Abstract: An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.

Abstract: A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern.

Abstract: Approaches for reducing through-silicon via (TSV) stress are provided. Specifically, provided is a device comprising a substrate and a TSV formed in the substrate, the TSV having an element patterned therein. The TSV further comprises a set of openings adjacent the element that are subsequently filled with a TSV fill material. The element may be patterned according to any number of shapes (e.g., circle, oval, rectangle, etc.) to optimize the stress distribution for the TSV. The element is patterned and provided within the TSV in order to reduce or compensate for stress forces caused by a change in volume of the conductive fill materials of the openings of the TSV. These approaches apply to both single TSVs and a plurality of TSVs (e.g., arranged as a matrix).

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate, sequentially forming an etch stop layer and an interlayer dielectric layer on the semiconductor substrate, forming a copper metal interconnect structure in the interlayer dielectric layer, forming a copper layer in the copper metal interconnect structure, forming a cobalt layer on the copper layer, and forming an aluminum nitride layer on the cobalt layer. The stack of cobalt layer and copper layer effectively suppresses electromigration caused by diffusion of the copper layer into the interlayer dielectric layer, improves the adhesion between the copper layer and the etch stop layer, and prevents delamination.

Abstract: A method and structure for preventing integrated circuit failure due to electromigration and time dependent dielectric breakdown is disclosed. A randomly patterned metal cap layer is selectively formed on the metal interconnect lines (typically copper (Cu)) with an interspace distance between metal cap segments that is less than the critical length (for short-length effects). Since the diffusivity is lower for the Cu/metal cap interface than for the Cu/dielectric cap interface, the region with a metal cap serves as a diffusion barrier.

Abstract: A substrate structure is provided. The substrate structure includes a substrate body; a metal layer formed on a surface of the substrate body; an insulating layer formed on the surface of the substrate body and having at least an opening for exposing the metal layer; and at least a die attach area defined on the surface of the substrate body corresponding in position to the opening for a semiconductor chip to be disposed thereon. The die attach area covers the entire opening or the metal layer is formed within the die attach area, thereby effectively preventing package delamination and improving the product yield.

Abstract: Embodiments of the present disclosure are directed towards interconnect structures for embedded bridge in integrated circuit (IC) package assemblies. In one embodiment, a method includes depositing an electrically insulative layer on a bridge interconnect structure, the bridge interconnect structure including a die contact that is configured to route electrical signals between a first die and a second die, depositing a sacrificial layer on the electrically insulative layer, forming an opening through the sacrificial layer and the electrically insulative layer to expose the die contact and forming a die interconnect of the first die or the second die by depositing an electrically conductive material into the opening. Other embodiments may be described and/or claimed.

Abstract: A chip package device includes an electrically conducting chip carrier, at least one semiconductor chip attached to the electrically conducting chip carrier, and an insulating laminate structure embedding the chip carrier, the at least one semiconductor chip and a passive electronic device. The passive electronic device includes a first structured electrically conducting layer, the first structured electrically conducting layer extending over a surface of the laminate structure.

Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.

Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a conductive plug that at least partially fills a contact seam void. The contact seam void is formed in a contact that extends through an ILD layer of dielectric material overlying a device region. A metallization layer is deposited overlying the contact.

Abstract: A structure and method for fabricating an improved SiCOH hardmask with graded transition layers having an improved profile for forming sub-20 nm back end of the line (BEOL) metallized interconnects are provided. In one embodiment, the improved hardmask may be comprised of five layers: an oxide adhesion layer, a graded transition layer, a dielectric layer, an inverse graded transition layer, and an oxide layer. In another embodiment, the improved hardmask may be comprised of four layers; an oxide adhesion layer, a graded transition layer, a dielectric layer, and an oxide layer. In another embodiment, a method of forming an improved hardmask may comprise a continuous five step plasma enhanced chemical vapor deposition (PECVD) process utilizing a silicon precursor, a porogen, and oxygen. In yet another embodiment, a method of forming an improved hardmask may comprise a continuous four step PECVD process utilizing a silicon precursor, a porogen, and oxygen.

Abstract: Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. A bit line structure is disposed on the bit line contact plug to extend in a first direction. The bit line structure is disposed in a trench pattern that intrudes into a side of the storage node contact plug. Related methods and systems are also provided.

Abstract: A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal. The chemical mechanical polishing thereby causes the first connection electrode to protrude from the surface of the first substrate. The first substrate is stacked with a second substrate having a second connection electrode. The first and second connection electrodes are bonded by applying pressure and heating to a temperature that is below the melting point of the metal of the first connection electrode.

Abstract: Provided is an integrated circuit device including a through-silicon-via (TSV) structure and a method of manufacturing the integrated circuit device. The integrated circuit device includes a semiconductor structure including a substrate and an interlayer insulating film, a TSV structure passing through the substrate and the interlayer insulating film, a via insulating film substantially surrounding the TSV structure, and an insulating spacer disposed between the interlayer insulating film and the via insulating film.

Abstract: An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g2+m2?V2 and an LCM of g and m is less than 20 g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2>m and the LCM of g, m, and m2 is less than 20 g.

Abstract: A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.

Abstract: The present invention provides an encapsulant with a base for use in semiconductor encapsulation, for collectively encapsulating a device mounting surface of a substrate on which semiconductor devices are mounted, or a device forming surface of a wafer on which semiconductor devices are formed, the encapsulant comprising the base, an encapsulating resin layer composed of an uncured or semi-cured thermosetting resin formed on one surface of the base, and a surface resin layer formed on the other surface of the base. The encapsulant enables a semiconductor apparatus having a good appearance and laser marking property to be manufactured.

Abstract: Disclosed herein are a molding composition for a semiconductor package including a liquid crystal thermosetting polymer resin and graphene oxide to thereby effectively decrease coefficient of thermal expansion (CTE) and warpage and maximize an effect of thermal conductivity, and a semiconductor package using the same.

Abstract: A method for forming an alignment feature for back side wafer processing in a wafer fabrication process involves forming a trench into but not entirely through a wafer from a top side of the wafer; forming a contrasting material on surfaces of the trench; and grinding a bottom side of the wafer to expose the trench using the handling wafer to handle the wafer during such grinding, wherein the contrasting material lining the exposed trench provides an alignment reference for precise alignment of the wafer for back side processing the wafer.

Abstract: Methods for forming an alignment mark and the resulting mark are disclosed. Embodiments may include forming a first shape having rotational symmetry; forming a second shape; and forming an alignment mark by combining the first shape and one or more of the second shape, wherein the alignment mark has rotational symmetry.

Abstract: A carburetor having an inlet opening that includes a pair of concavities operative to direct air toward the metering rod of the carburetor. A carburetor having an inlet opening that includes an arcuate manifold adjacent to the inlet opening and in fluid communication with a fuel reservoir. A carburetor having a slide assembly that includes a positioning mechanism operative to adjust the position of the metering rod relative to the throttle slide. A throttle slide that includes a flow guide that bisects an arcuate relief on an underside thereof. A method for configuring the throat of a carburetor that includes an upper portion of a first diameter and a lower portion of a second diameter that is offset from the first diameter. The method comprises deriving an optimum size for the first and second diameters and the offset based on the pumping efficiency and operating parameters of the engine.

Abstract: A potable water dispenser comprising a supporting structure for means of producing carbonated water. The means of producing carbonated water comprise at least one dispensing assembly that can be connected hermetically to the mouth of a container and is provided with a water dispensing port that is controlled by a first valve and is adapted to pour into the container a measured quantity of water, and a port for injecting pressurized gas into the container, which can be activated to carbonate the water poured into the container from the dispensing port. In the dispensing assembly there is, moreover, a venting port, which is controlled by a second valve, so as to allow the outflow of air from the container when water is poured into the container by the dispensing port.

Abstract: Conventional spray-drying methods are improved by incorporation of a pressure nozzle and a diffuser plate to improve the flow of drying gas and a drying chamber extension to increase drying time, such improvements leading to the formation of homogeneous solid dispersions of drugs in concentration-enhancing polymers.

Abstract: The system (10) includes a mold (12) with lock pins (18) extending from the mold (12). Each lock pin (18) defines a reduced-diameter lock valley (22) and a wider lock head (24), and is configured to pass through a throughbore (36A, 36b) of a coupling plate (28) of a mold machine (30) and into and through a wide-opening portion (44) of a “butternut-squash” shaped key-slot (42D) defined within a bar (40) of a clamping mechanism (38) adjacent the coupling plate (28). The bar (40) of the clamping mechanism (38) may be selectively moved between a receiving position and a locking position thereby moving the key slot (42D) defined within the bar (40) to engage and release the lock valley (22) to secure and release the lock pin (18) to efficiently secure the mold (12) within, and permit removal of the mold (12) from, a mold machine (30).

Abstract: A mold releasability evaluating apparatus includes a forming die that includes a bottom portion having a main surface, and a wall surface portion that is connected to the main surface of the bottom portion and has a wall surface in which an angle formed with the main surface of the bottom portion is an obtuse angle; an extrusion pin capable of protruding out from the main surface of the bottom portion in a direction that separates a compact from the main surface of the bottom; and a measuring device configured to measure a load applied to the extrusion pin when the extrusion pin pushes the compact away from the main surface of the bottom portion, after one surface of the compact is formed by the main surface of the bottom portion.

Abstract: Arrangement information regarding shot areas is obtained in an imprinting method. When a pattern is sequentially formed in the shot areas, the attraction force of a first attraction area is reduced to less than that of the second attraction area. After the pattern is formed in the shot area corresponding to the first attraction area, the attraction forces of the first and second attraction areas are changed. The position information regarding the shot area corresponding to the second attraction area is obtained, which is compared with the position information regarding the shot area corresponding to the second attraction area based on the arrangement information. If the difference between the compared position information is a threshold value or less, positioning of a substrate and a mold is achieved using the arrangement information. If the difference is greater than the threshold value, the arrangement information regarding the shot areas is obtained again.

Abstract: A tool (100) for manufacturing a component part from a flowable base material, wherein the tool (100) comprises a processing chamber (102) into which the flowable base material is introducible for manufacturing the component part, an acoustic sensor (104) configured for sensing an acoustic signal originating from the tool (100), particularly from the processing chamber (102), and being indicative of an interaction between the flowable base material and the tool (100), particularly the processing chamber (102), during the manufacturing, wherein the acoustic sensor (104) comprises a movable actuator (110), and a control unit (200) configured for controlling and/or documenting the manufacturing in the processing chamber (102) based on the sensed acoustic signal.