Abstract: A conductive structure includes a wafer having a scribe line defined thereon, at least a first wiring layer formed in the scribe line, and at least a via layer disposed in the scribe line and under the wiring layer. The first wiring layer includes a main pattern and the via layer includes a closed frame pattern corresponding to the main pattern of the first wiring layer.

Abstract: A semiconductor having through-silicon via includes a substrate, an outer dielectric liner, an inner dielectric liner and a conductive contacting layer. The substrate has a top surface and a bottom surface and defining at least one through-silicon via going through the top surface toward the bottom surface. The outer dielectric liner covers the top surface of the substrate. The inner dielectric liner covers a wall of the through-silicon via. The thickness of the inner dielectric liner reduces from the top surface toward the bottom surface. The conductive contacting liner over fills the through-silicon via and is exposed on the top surface.

Abstract: A semiconductor substrate for use in an integrated circuit, the semiconductor substrate including a channel defined on a surface of the substrate. The channel includes a first wall, a second wall, and a third wall. The first wall is recessed from the surface. The second wall extends from the surface to the first wall. The third wall extends from the surface to the first wall and faces the second wall across the channel. At least one of the second wall and the third wall includes a plurality of structures projecting into the channel from the second wall or the third wall.

Abstract: Conductors in a 3D circuit that include horizontal lines with a plurality of vertical extensions in high aspect ratio trenches can be formed using a two-step etching procedure. The procedure can comprise providing a substrate having a plurality of spaced-apart stacks; forming a pattern of vertical pillars in a body of conductor material between stacks; and forming a pattern of horizontal lines in the body of conductor material over stacks, the horizontal lines connecting vertical pillars in the pattern of vertical pillars. The body of conductor material can be deposited over the plurality of spaced-apart stacks. A first etch process can be used to form the pattern of vertical pillars. A second etch process can be used to form the pattern of horizontal lines. The conductors can be used as word lines or as bit lines in 3D memory.

Abstract: Semiconductor devices and methods for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region. A contact dielectric layer is formed on the substrate, covering the substrate and device component. The contact dielectric layer includes a lower contact dielectric layer, an intermediate contact dielectric etch stop layer formed on the lower contact dielectric layer, and an upper contact dielectric layer formed on the intermediate contact dielectric etch stop layer. A contact opening is formed through the contact dielectric layer. The contact opening has an upper contact sidewall profile in the upper contact dielectric layer and a lower tapered contact sidewall profile in the lower contact dielectric layer. The tapered sidewall profile prevents shorting with the device component.

Abstract: A chip package structure and a manufacturing method thereof are provided. The chip package structure includes a substrate, a chip, a plurality of wires, a film layer, a carrier, and an encapsulant. The substrate has an upper surface and a lower surface. The chip is mounted on the upper surface of the substrate. The wires are electrically connected to the chip and the substrate respectively. The film layer is attached to the substrate and entirely encapsulates the chip and the wires. The carrier is adhered on the film layer. The encapsulant is disposed on the upper surface of the substrate, wherein the encapsulant has an electro-magnetic shielding filler. The encapsulant at least partially encapsulates the carrier and the film layer, and the encapsulant covers the chip and the wires.

Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.

Abstract: A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Abstract: A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction: a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor chip; a resin which covers the semiconductor chip, and includes first and second surfaces opposite to each other, first and second side surfaces opposite to each other, and third and fourth side surfaces opposite to each other; a first conductive member which is formed on the semiconductor chip on a first surface side, and includes an end portion projecting from the first or second side surface; a second conductive member including an end portion projecting from the first or second side surface; and a metal which is formed on a second surface side of the semiconductor chip, is exposed from the resin body on the second surface side, and includes an end portion thereof exposed from the third and fourth side surfaces on the same plane as the third and fourth side surfaces.

Abstract: Embodiments of the present disclosure are directed to leadframe packages with wettable sides and methods of manufacturing same. In one embodiment, the leads of the leadframe packages have recesses with a curved profile formed therein. The recesses are plated with a solder wettable layer of conductive material that enables solder to flow along the surface during surface mounting of the package to a board, such as a PCB.

Abstract: A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto.

Abstract: The present interposer makes it possible to tailor the coefficient of thermal expansion of the interposer to match components to be attached thereto within very wide ranges. The semiconductor interposer, includes a substrate of a semiconductor material having a first side and an opposite second side. There is at least one conductive wafer-through via including metal. At least one recess is provided in the first side of the substrate and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure. The exposed surfaces of the metal-filled via and metal-filled recess are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via includes a narrow part and a wider part, and contact elements are provided on the routing structure having an aspect ratio, height:diameter, <1:1, preferably 1:1 to 2:1.

Abstract: A partition in lattice form forms a plurality of housing sections. A plurality of circuit blocks including a semiconductor block and a terminal base block are electrically connected one to another in a state of being housed in the housing sections to form a power semiconductor circuit. The semiconductor block is formed by covering an IGBT with an insulating material. A collector of the IGBT is connected to an electrode through a metal plate. The electrode is led out from an inner portion of the insulating material to a side surface of the insulating material. A terminal base block includes a power terminal to which an external power wiring for supplying electric power to the IGBT is electrically connected, and a screw hole into which a screw for fixing the power wiring is inserted.

Abstract: Methods of manufacturing semiconductor device assemblies include attaching a back side of a first semiconductor die to a substrate and structurally and electrically coupling a first end of laterally extending conductive elements to conductive terminals on or in a surface of the substrate. Second ends of the laterally extending conductive elements are structurally and electrically coupled to bond pads on or in an active surface of the first semiconductor die. Conductive structures are structurally and electrically coupled to bond pads of a second semiconductor die. At least some of the conductive structures are aligned with at least some of the bond pads of the first semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. At least some of the conductive structures are structurally and electrically coupled to at least some of the bond pads of the first semiconductor die.

Abstract: A BGA type packaged integrated circuit (IC) die has an exposed coronal heat spreader. The die, which is attached to a substrate, is encapsulated in a central segment of molding compound. The central segment is laterally surrounded by, and separated by a moat from a ring segment of molding compound, to a form a slot. The coronal heat spreader is inserted into the slot to cap the central segment. The coronal heat spreader is attached to the substrate and to the central segment with thermal glue. In operation, at least some of the heat generated by the die is dissipated through the coronal heat spreader.

Abstract: Certain embodiments provide a semiconductor package including a base metal portion, a frame body, a plurality of wires, and a lid body. The base metal portion includes multiple grooves on a back surface, and can mount a semiconductor chip on a front surface. The frame body is arranged on the front surface of the base metal portion. The plurality of wires are arranged to penetrate through a side surface of the frame body. The lid body is arranged on the frame body.

Abstract: A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.

Abstract: An integrated circuit device package may include a flexible substrate having a first wiring, an integrated circuit device having a second wiring, a flexible insulation structure having a first opening and a second opening exposing the first wiring and the second wiring, respectively, a third wiring electrically connecting the first wiring to the second wiring, and a flexible protection member covering the third wiring. A stacked flexible integrated circuit device package may include a flexible substrate, a first flexible integrated circuit device including a first connection pad, a second flexible integrated circuit device including a second connection pad, a connection wiring electrically connecting the first and the second connection pads to an external device, and a flexible protection member disposed on the second flexible integrated circuit device.

Abstract: A semiconductor device includes a main surface, a back surface opposite to the main surface, a first side on the main surface, a second side opposite to the first side, a third side between the first side and the second side, a fourth side opposite to the third side, a first point on a periphery of the main surface between the first side and the third side, a second point on the periphery of the main surface between the second side and the fourth side, a third point on the periphery of the main surface between the first side and the fourth side, and a fourth point on the periphery of the main surface between the third side and the second side, a first semiconductor chip disposed over the main surface of the substrate, and a second semiconductor chip disposed over the main surface of the substrate.

Abstract: Provided are a flow path member that suppresses flow path breakage, a heat exchanger and a semiconductor device using the same. This flow path member has a flow path in which a fluid flows and which is constituted by a lid portion, a partition wall portion, a side wall portion and a bottom plate portion. At least one of the partition wall portion and the sidewall portion is partly embedded in at least one of the lid portion and the bottom plate portion for direct connection.

Abstract: A chip stacking packaging structure is provided for achieving high-density stacking and improving a heat dissipation efficiency of the chip stacking packaging structure. The chip stacking packaging structure includes a main substrate and at least one stacking substrate in which a main chip is disposed in the main substrate, at least one stacking chip is disposed on the stacking substrate, and a side edge of the stacking substrate is disposed on the main substrate, so that the stacking chip is connected to the main chip.

Abstract: An integrated circuit package including a first substrate, a first die, a second die, a second substrate, and a system on chip. The first substrate includes a first portion including first connections, a second portion including no connections, a third portion including second connections, a first opening between the first portion and the second portion, and a second opening between the second portion and the third portion. The first die is arranged on the first substrate. The first die includes third connections to connect to the first connections via the first opening. The second die is arranged adjacent to the first die on the first substrate. The second die includes fourth connections to connect to the second connections via the second opening. The second substrate is connected to the first substrate. The system on chip is arranged on the second substrate between the first substrate and the second substrate.

Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line.

Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.

Abstract: Provided is a semiconductor flat package with improved mountability. In a semiconductor device, an end surface of a lead, which is exposed from an encapsulation resin, is covered with a plated layer, and a side end surface of the plated layer and a side end surface of the encapsulation resin are flush with each other. A material with good solder wettability is formed at a lead cut portion of the semiconductor flat package, to thereby improve solder connection strength with a circuit board. A solder fillet is formed from the lead cut portion of the semiconductor package, to thereby enable adaptation of solder automatic visual inspection after mounting.

Abstract: Provided is a semiconductor package, including: a lower package to which elements are mounted; a metal post connected to the lower package and including at least one metal material portion; and an upper package to which elements is mounted, and which is connected to the metal post via a solder ball.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Abstract: A semiconductor device includes a substrate having a plurality of contact surfaces, an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact surfaces and a second open portion which exposes the other contact surfaces, a storage node contact (SNC) plug filling the first open portion, and a damascene structure filing the second open portion and including a bit line, a spacer formed on both sidewalls of the bit line, a capping layer formed over the bit line and the spacer, and an air gap formed between the bit line and the spacer. The bit line includes a conductive material of which the volume is contracted by a heat treatment to form the air gap.

Abstract: An interposer structure including a semiconductor substrate, a plurality of shallow trenches, a plurality of deep trenches and a plurality of metal damascene structures is provided. The semiconductor substrate has a first surface and a second surface opposite to each other. The shallow trenches are formed on the first surface in both of a first area and a second area of the semiconductor substrate and correspondingly a plurality of respective openings are formed on the first surface. The deep trenches extend from at least one of the shallow trenches toward the second surface in the second area and correspondingly a plurality of respective openings are formed on the second surface. The metal damascene structures are filled in both of the shallow trenches and the deep trenches. A manufacturing method for the aforementioned interposer structure is also provided.

Abstract: A method of forming an integrated circuit structure includes forming a cap layer above a first ILD layer of a first metal level, the first ILD layer includes a recess filled with a first conductive material to form a first interconnect structure. Next, a second ILD layer is formed above the cap layer and a via is formed within the second ILD layer as a second interconnect structure of a second metal level. The via is aligned with the first interconnect structure. Subsequently, a portion of the cap layer is removed to extend the via to expose a top portion of the first conductive material then a passivation cap is selectively formed at a bottom portion of the via in the second ILD layer and the passivation cap contacting the top portion of the first conductive material. The passivation cap includes a metal alloy to form an interface between the bottom portion of the via and the first conductive material.

Abstract: A memory device comprises a substrate, a plurality of buried word lines, a plurality of digital contacts, a patterned insulating layer, a liner layer, a plurality of buried bit lines, and a cap layer. The buried word lines are arranged in the substrate in parallel along a first direction. Each of the digital contacts is arranged between one pair of the neighboring buried word lines. The patterned insulating layer is arranged on the buried word lines, having a plurality of contact holes opposite to the digital contacts. The liner layer is arranged on the substrate, and abuts the patterned insulating layer. The buried bit lines are arranged in parallel along a second direction different from the first direction. The cap layer arranged to cover the buried bit lines.

Abstract: A semiconductor device comprises a plurality of device features formed on a substrate and a plurality of dummy features formed on the substrate and across an open region between the device features. Adjacent device features are spaced apart by a distance of 100 microns or more. Each device feature includes a barrier island and a metal layer on top of the barrier island. Each dummy feature has a structure that corresponds to the structure of the barrier island. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor element, an interconnection layer, and a bonding layer. The interconnection layer includes Cu. The bonding layer includes a first alloy that is an alloy of Cu and a first metal other than Cu between the semiconductor element and the interconnection layer. A melting point of the first alloy is higher than a melting point of the first metal.

Abstract: Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing one or more frontside redistribution layers over a molded panel having a backside and an opposing frontside through which a semiconductor die and a first Surface Mount Device (SMD) are exposed. Material is removed from the backside of the molded panel to expose the first SMD therethrough. A contact array is formed over the frontside of the molded panel and electrically coupled to the semiconductor die and to the first SMD through the frontside redistribution layers. The molded panel is singulated to produce a SiP having a molded body in which the semiconductor die and the first SMD are embedded and through which the first SMD extends.

Abstract: Certain embodiments provide a semiconductor device including a semiconductor substrate, a side wall portion, a cap substrate, a plurality of external connection terminals, and a ground conductor. The semiconductor substrate includes a semiconductor element on its front surface. The side wall portion has conductivity and is provided on the front surface of the semiconductor substrate so as to surround the semiconductor element. The cap substrate is provided on the side wall portion so as to be electrically connected to the side wall portion. Each of the plurality of external connection terminals is provided on a back surface of the semiconductor substrate so as to be electrically connected to the semiconductor element. The ground conductor is provided to be electrically connected to the side wall portion on the entire back surface of the semiconductor substrate except an area in which the plurality of external connection terminals is provided.

Abstract: A semiconductor device including a semiconductor substrate having a hook-up region; wirings extending in a first direction above the semiconductor substrate and being aligned with a first spacing between one another, every two wirings forming pairs of wirings, each pair having a first portion being bent in a second direction different from the first direction in the hook-up region, the wirings of each pair being spaced from one another by a first spacing, the pairs being spaced from one another by a second spacing greater than the first spacing; and fringe patterns each being formed on a first side of each of the wirings of each of the pairs, the first side facing the second spacing.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.

Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.

Abstract: Exemplary embodiments of the present invention provide a V0 via unit cell with multiple keep out zones. The keep out zones are oriented concentrically and provide support for multiple sizes of through-silicon vias (TSVs). An off-center alignment between the V0 via unit cell and a probe pad is used to improve contact between the V0 vias and a probe pad. During a chip redesign, the TSV size may be changed without the need to revise the V0 mask.

Abstract: A method for creating one or more vias in an integrated circuit structure and the integrated circuit structure. The method includes depositing a coating layer over a hard mask layer on the integrated circuit structure; locating an initial via pattern layer over the coating layer; and etching the pattern of the one or more initial openings in the coating layer and through openings in the hard mask layer. The coating layer is a conformal deposition of an oxide, a boron nitride, or other nitride. The initial via pattern layer has one or more initial openings located therein.

Abstract: A semiconductor device includes a first contact plug, a diametric dimension of an upper end portion thereof greater than the lower end portion thereof; a first insulating film above a substrate and covering the first plug; a second contact plug, a diametric dimension of an upper end portion thereof less than lower end portion thereof, the lower end portion contacting the upper end portion of the first plug; a second insulating film above the first insulating film and the first plug and covering the second plug; a wiring layer including a lower end portion contacting the upper end portion of the second plug; and a third insulating film above the second insulating film and the second plug and covering the wiring layer; wherein the upper end portion of the first plug displaced from the lower end portion of the second plug has a step.

Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.

Abstract: The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.

Abstract: Vias (holes) are formed in a wafer or a dielectric layer. A low viscosity conductive ink, containing microscopic metal particles, is deposited over the top surface of the wafer to cover the vias. An external force is applied to urge the ink into the vias, including an electrical force, a magnetic force, a centrifugal force, a vacuum, or a suction force for outgas sing the air in the vias. Any remaining ink on the surface is removed by a squeegee, spinning, an air knife, or removal of an underlying photoresist layer. The ink in the vias is heated to evaporate the liquid and sinter the remaining metal particles to form a conductive path in the vias. The resulting wafer may be bonded to one or more other wafers and singulated to form a 3-D module.

Abstract: An electronic device includes a chip with an integrated electronic component and a terminal made of a first metal material. The device further includes a lead made of a second metal material different from the first metal material. A bonding wire made of a selected one of the first and second metal materials has opposite ends coupled with the terminal and the lead. An interface element having a first layer made of a selected one of the first and second metal materials and a second layer made of an unselected one of the first and second metal materials has the first layer coupled with the bonding wire and the second layer coupled with a component, wherein the component is ether the terminal or the lead.

Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

Abstract: A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.