Abstract: A semiconductor device includes a first fin rising out of a semiconductor base. It further includes a second fin rising out of the semiconductor base. The second fin is substantially parallel to the first fin that forms a span between the first fin and the second fin. A first dielectric layer is deposited on exposed surfaces of a first gate body area of the first fin, a second gate body area of the second fin, and an adjacent surface of the semiconductor base that defines the span between the first and second gate body areas. A gate electrode layer is sandwiched between the first dielectric layer and a second dielectric layer. The semiconductor device includes a third fin interdigitated between the first fin and the second fin within the span. Exposed surfaces of the gate body area of the third fin are in contact with the second dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract: Methods and apparatus are provided for an integrated circuit. The method includes forming a corrugation mask on a substrate, and forming a channel corrugation on the substrate. The corrugation mask is removed from the substrate, and a gate insulator is formed overlying the channel corrugation on the substrate. A gate is formed overlying the channel gate insulator.

Abstract: Variations in the contact area between contact plugs are suppressed to suppress fluctuations in contact resistance. In three third interlayer insulating films, a contact hole is self-alignedly formed to extend through the portions thereof interposed between two wiring portions and the portions thereof interposed between two gate wiring portions and reach a first polysilicon plug. In the contact hole, a second polysilicon plug is formed to come in contact with the first polysilicon plug.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to different types of transistors having different channel materials. In one aspect, a method of fabricating a semiconductor device includes providing a substrate comprising a silicon substrate having a main surface oriented in a {100} crystal plane and having a notch oriented in a <100> direction. The method additionally includes forming a plurality of silicon protrusions in a first predetermined region by recessing portions of the main surface surrounding the silicon protrusions. The method additionally includes forming shallow trench isolation (STI) structures adjacent to the silicon protrusions to electrically isolate the silicon protrusions, thereby defining channel areas of a transistor of a first type. The method further includes removing at least upper portions of the silicon protrusions, thereby forming trenches between neighboring STI structures and filling the trenches with a III-V material.

Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing material without using GeH4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.

Abstract: A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide layer and a top nitride layer are provided over the dummy gate structure and active region to protect the dummy gate during source and drain implantation. The active region is implanted using dopants such as, a n-type dopant or a p-type dopant to create a source region and a drain region in the active region, after which the sacrificial conformal layer is removed.

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

Abstract: Integrated circuits with smooth metal gates and methods for fabricating integrated circuits with smooth metal gates are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a partially fabricated integrated circuit including a dielectric layer formed with a trench bound by a trench surface. The method deposits metal in the trench and forms an overburden portion of metal overlying the dielectric layer. The method includes selectively etching the metal with a chemical etchant and removing the overburden portion of metal.

Abstract: A semiconductor device according to an embodiment includes a gate wire including a laminated film in which a polysilicon film, a barrier conductive film, and a metal film are laminated in this order; a first contact plug/upper layer wire arranged above the source or the drain; a second upper layer wire arranged above an element isolation region; a second contact plug arranged apart from the second upper layer wire and connecting the metal film and the polysilicon film above a channel region; and a third contact plug formed apart from the polysilicon film in the element isolation region and connecting the second upper layer wire and the metal film. The second contact plug includes a barrier metal in contact with the polysilicon film and the barrier conductive film is made of WN, TaN, or Ta and the barrier metal is made of Ti or TiN.

Abstract: According to one embodiment, an electronic device includes a substrate, a first electrode provided stationary above the substrate and used for a variable capacitor, a second electrode provided movable above or below the first electrode and used for the variable capacitor, a first protective insulation film provided on a first surface of the first electrode, the first surface facing the second electrode, and a second protective insulation film provided on a second surface of the second electrode, the second surface facing the first electrode.

Abstract: A MEMS microphone with reduced parasitic capacitance is provided. A microphone includes a protection film covering a rim-sided area of the backplate.

Abstract: An integrated device package includes a housing having a first opening and a second opening in fluid communication with an interior volume of the housing. A package substrate(s) has a first port and a second port. A first device die is mounted to the substrate(s) over the first port. A second device die is mounted to the substrate(s) over the second port. The substrate(s) is coupled to the housing to cover the first and second openings such that the first device die is disposed within the interior volume through the first opening and the second device die is disposed within the interior volume through the second opening.

Abstract: There is provided a microphone including: a thin film member including leg members extended in a direction not in parallel with a vibration direction; first supports supporting first points of the leg members, respectively; and a piezoelectric member connected to second points of the leg members and converting vibrations of the thin film member into electrical signals.

Abstract: A semiconductor sensor device has a pressure sensing die and at least one other die mounted on a substrate, and electrical interconnections that interconnect the pressure sensing die and the at least one other die. An active region of the pressure sensing die is covered with a pressure sensitive gel material, and a cap having a cavity is mounted over the pressure sensing die such that the pressure sensing die is positioned within the cavity. The cap has a side vent hole that exposes the gel covered active region of the pressure sensing die to ambient atmospheric pressure outside the sensor device. Molding compound on an upper surface of the substrate encapsulates the at least one other die and at least a portion of the cap.

Abstract: A MEMS (microelectromechanical systems) structure comprises a MEMS wafer. A MEMS wafer includes a cap with cavities bonded to a structural layer through a dielectric layer disposed between the cap and the structural layer. Unique configurations of MEMS devices and methods of providing such are set forth which provide for, in part, creating rounded, scalloped or chamfered MEMS profiles by shaping the etch mask photoresist reflow, by using a multi-step deep reactive ion etch (DRIE) with different etch characteristics, or by etching after DRIE.

Abstract: The disclosure provides methods and apparatus for release-assisted microcontact printing of MEMS. Specifically, the principles disclosed herein enable patterning diaphragms and conductive membranes on a substrate having articulations of desired shapes and sizes. Such diaphragms deflect under applied pressure or force (e.g., electrostatic, electromagnetic, acoustic, pneumatic, mechanical, etc.) generating a responsive signal. Alternatively, the diaphragm can be made to deflect in response to an external bias to measure the external bias/phenomenon. The disclosed principles enable transferring diaphragms and/or thin membranes without rupturing.

Abstract: A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher chemical affinity for a diffusible species of a magnetic material, from which the magnetic region is formed, compared to a chemical affinity between the diffusible species and at least another species of the magnetic material. Thus, the diffusible species is removed from the magnetic material to the attracter material. The removal accommodates crystallization of the depleted magnetic material. The crystallized, depleted magnetic material enables a high tunnel magneto resistance, high energy barrier, and high energy barrier ratio. The magnetic region may be formed as a continuous magnetic material, thus enabling a high exchange stiffness, and positioning the magnetic region between two magnetic anisotropy-inducing oxide regions enables a high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed.

Abstract: A magnetic device includes a substrate, a sensing block and a repair layer. The substrate has a bottom electrode, a registration layer and a barrier layer disposed on the registration layer. The sensing block is patterned to distribute on the barrier layer. The repair layer is disposed substantially on the barrier layer, wherein the barrier layer is configured to have a tunneling effect when a bias voltage exists between the sensing block and the registration layer.

Abstract: A magnetoresistive element according to an embodiment includes: a base layer; a first magnetic layer formed on the base layer, and including a first magnetic film having an axis of easy magnetization in a direction perpendicular to a film plane, the first magnetic film including MnxGa100-x (45?x<64 atomic %); a first nonmagnetic layer formed on the first magnetic layer; and a second magnetic layer formed on the first nonmagnetic layer, and including a second magnetic film having an axis of easy magnetization in a direction perpendicular to a film plane, the second magnetic film including MnyGa100-y (45?y<64 atomic %). The first and second magnetic layers include different Mn composition rates from each other, a magnetization direction of the first magnetic layer is changeable by a current flowing between the first magnetic layer and the second magnetic layer via the first nonmagnetic layer.

Abstract: A current sensor device for sensing a measuring current includes a semiconductor chip having a magnetic field sensitive element. The current sensor device further includes an encapsulant embedding the semiconductor chip. A conductor configured to carry the measuring current is electrically insulated from the magnetic field sensitive element. A redistribution structure includes a first metal layer having a first structured portion which forms part of the conductor.

Abstract: A method for forming a photo diode is provided. The method includes: forming a first bottom electrode corresponding to a first pixel and a second bottom electrode corresponding to a second pixel over a substrate; forming a dielectric layer over the substrate; patterning the dielectric layer over the substrate; forming a photo conversion layer over the substrate; and forming a top electrode over the photo conversion layer; forming a color filter layer over the top electrode, wherein at least a portion of the dielectric layer separates a first portion of the color filter layer corresponding to a first pixel from a second portion of the color filer layer corresponding to a second pixel, and a refractive index of the dielectric layer is lower than a refractive index of the color filter layer.

Abstract: Embodiments of mechanisms of a backside illuminated image sensor device structure are provided. The backside illuminated image sensor device structure includes a substrate having a frontside and a backside and a pixel array formed in the frontside of the substrate. The backside illuminated image sensor device structure further includes an antireflective layer formed over the backside of the substrate, and the antireflective layer is made of silicon carbide nitride.

Abstract: A pixel array includes a plurality of photodiodes disposed in a semiconductor layer and arranged in the pixel array. A color filter layer is disposed proximate to the semiconductor layer. Light is to be directed to at least a first one of the plurality of photodiodes through the color filter layer. An optical shield layer is disposed proximate to the color filter layer. The color filter layer is disposed between the optical shield layer and the semiconductor layer. The optical shield layer shields at least a second one of the plurality of photodiodes from the light.

Abstract: To suppress appearance of a ghost. The present optical module includes a sensor configured to pick up an image of an image pickup object, and a memory chip configured to store pixel data read out from the sensor and having the sensor joined thereto. The memory chip is connected to a substrate by a connection portion by flip-chip connection. The sensor can be connected by a wire to the memory chip, to which the sensor is joined. Further, the sensor can be joined to the memory chip in such a manner as to project toward an opening of the substrate. The present technology can be applied to a camera module.

Abstract: An avalanche photodiode with a defect-assisted silicon absorption region. An example includes a substrate; a layer of silicon on the substrate, the layer of silicon including a positively-doped region, a negatively-doped region, and an absorption region between the positively-doped and negatively-doped regions, the absorption region including defects in its crystal structure; and contacts in electrical communication with the positively-doped and negatively-doped regions to receive a bias potential.

Abstract: A photodetection device of the present invention includes a semiconductor substrate which is defined such that a first light-receiving portion and a second light-receiving portion are spaced from one another, and an optical filter which is formed on the semiconductor substrate, and includes a first filter which is disposed so as to cover the first light-receiving portion, to selectively allow an optic element in a first wavelength band to transmit through, and a second filter which is disposed so as to cover the second light-receiving portion, to selectively allow an optic element in a second wavelength band different from the first wavelength band, to transmit through, and the optical filter has a filter laminated structure which is defined such that edge portions of the first filter and the second filter overlap one another on a boundary region between the first light-receiving portion and the second light-receiving portion.

Abstract: A solid-state imaging apparatus includes a plurality of phase difference detection pixels configured adjacent to one another; and an isolation structure arranged so as to isolate light entering each of light-receiving units of the plurality of phase difference detection pixels, in which the isolation structure is formed so as to have a inclined side wall surface whose cross section is tapered.

Abstract: A method for manufacturing a solid-state image sensor, comprising preparing a substrate including a pixel region where a plurality of pixels are provided and a peripheral region, forming a structure including a wiring layer and an interlayer insulation film on the pixel region and the peripheral region, forming a first wiring pattern only on the structure located in the peripheral region, forming a protective film covering the first wiring pattern and the structure, forming a second wiring pattern on a convex portion of the protective film formed by steps between an upper surface of the first wiring pattern and the structure so that an end of the second wiring pattern is located away from the pixel region than an end of the first wiring pattern in a state that the protective film covers the first wiring pattern, and forming an optical system.

Abstract: Phosphate-based glass doped with copper ions having infrared blocking filter characteristics is formed into particles and is mixed with a transparent encapsulating resin to encapsulate a semiconductor element. The glass particles have a particle diameter four times or more as large as a wavelength of infrared radiation to be blocked. An optical semiconductor device can be obtained having a stable filter characteristics thereof even if an incident light angle changes and is resistant to moisture.

Abstract: A backside illumination semiconductor image sensing device includes a semiconductor substrate. The semiconductor substrate includes a radiation sensitive diode and a peripheral region. The peripheral region is proximal to a sidewall of the backside illumination semiconductor image sensing device. The backside illumination semiconductor image sensing device further includes a first anti reflective coating (ARC) on a backside of the semiconductor substrate and a dielectric layer on the first anti reflective coating. Additionally, a radiation shielding layer is disposed on the dielectric layer. Moreover, the backside illumination semiconductor image sensing device has a photon blocking layer on the sidewall of the of the backside illumination semiconductor image sensing device. The at least a portion of a sidewall of the radiation shielding layer is not covered by the photon blocking layer and the photon blocking layer is configured to block photons penetrating into the semiconductor substrate.

Abstract: An avalanche photodiode can include: an avalanche region having one or more layers prepared from GaAs; an N? absorption layer extending across the avalanche region; an N-type layer above at least a center portion of the N? absorption layer; and optionally a lower conductivity layer laterally from the N-type layer to a surface of the avalanche region and above a perimeter portion of the N? absorption layer, the lower conductivity layer having lower conductivity compared to the N-type layer. The avalanche photodiode can include a window layer above the N-type layer and lower conductivity layer, and an anode contact above the window layer. The avalanche photodiode can include an N+ barrier layer below the N? absorption layer, an N+ conduction layer below the N+ barrier layer, a substrate below the N+ conduction layer, and a cathode contact coupled with the N+ conduction layer.

Abstract: Systems and methods are provided for fabricating a backside illuminated image sensor including an array of pixels. An example image sensor includes a first pixel, a second pixel, and an isolation structure. The first pixel is disposed in a front side of a substrate and is configured to generate charged carriers in response to light incident upon a backside of the substrate. The second pixel is disposed in the front side of the substrate and is configured to generate charged carriers in response to light incident upon the backside of the substrate. The isolation structure is disposed to separate the second pixel from the first pixel, and extends from the backside of the substrate toward the front side of the substrate. The isolation structure includes a sidewall substantially vertically to the front side of the substrate.

Abstract: An electronic device may include a first semiconductor layer, a first electrode layer on the semiconductor layer, an adhesive insulating layer on the first electrode layer, a second electrode layer on the adhesive insulating layer, a second semiconductor layer. The first electrode layer may include a first plurality of electrodes, the first electrode layer may be between the adhesive insulating layer and the first semiconductor layer, and the adhesive insulating layer may include at least one of SiOCN, SiBN, and/or BN. The second electrode layer may include a second plurality of electrodes, the adhesive insulating layer may be between the first and second electrode layers, and the second electrode layer may be between the adhesive insulating layer and the second semiconductor layer.

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first doping region arranged at a main surface of the semiconductor substrate, an emitter layer arranged at a back side surface of the semiconductor substrate, at least one first conductivity type area separated from the first doping region by a second doping region of the semiconductor substrate and at least one temperature-stabilizing resistance area. The first doping region has a first conductivity type and the emitter layer has at least mainly a second conductivity type. The second doping region has the second conductivity type and the at least one first conductivity type area has the first conductivity type. The at least one temperature-stabilizing resistance area is located within the second doping region and adjacent to the at least one first conductivity type area.

Abstract: An infrared ray sensor includes a thermopile. The thermopile includes a first semiconductor material part and a second semiconductor material part, the first semiconductor material part and the second semiconductor material part are laminated, and a dielectric film is provided between the first semiconductor material part and the second semiconductor material part.

Abstract: There is provided a power semiconductor device, including: a first semiconductor layer of a first conductive type having a thickness of t1 so as to withstand a reverse voltage of 600V; and a second semiconductor layer of a second conductive type formed inside an upper portion of the first semiconductor layer and having a thickness of t2, wherein t1/t2 is 15 to 18.

Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

Abstract: Approaches for providing enlarged fin tips for a set of fins of a fin field effect transistor device (FinFET) are disclosed. Specifically, approaches are provided for patterning a hardmask formed over a substrate; forming a set of fin tips from the substrate using a first etch; and forming a set of fins from the substrate using a second etch, wherein each of the set of fin tips has a width greater than a most narrow section of each of the set of fins. Each of the fin tips has a tapered profile that enlarges towards a top end thereof to compensate for erosion losses during processing.

Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.

Abstract: An electronic fuse includes a body, an anode coupled to the body, and a cathode coupled to the body. Each of the anode and the cathode includes a first line contacting the body. The first line is discontinuous along its length and includes a first portion and a second portion with a space therebetween. A second line is disposed above the first line and a plurality of vias couple the first and second lines. The first portion of the first line is coupled to a first subset of the plurality of vias and the second portion of the first line is coupled to a second subset of the vias.

Abstract: A novel method for manufacturing a semiconductor device and a semiconductor device are provided. The semiconductor device includes a substrate, a trench capacitor, a contact pad, an inter-layer dielectric (ILD) layer and contact elements. The trench capacitor includes a doped region, a first dielectric layer, a bottom electrode, a second dielectric layer and a top electrode, in which the contact pad is positioned on the doped region. The ILD layer has contact windows, and the contact elements are disposed therein. Because of the presence of the contact pad positioned on the doped region, the thickness of the ILD layer over the top electrode is increased but still satisfying the requirement of the maximum depth limit to the contact windows of etching the ILD layer.

Abstract: A semiconductor device includes a lower electrode including at least one of a noble metal and a conductive noble metal oxide, a dielectric layer disposed on the lower electrode and including titanium oxide, a protection insulating layer disposed on the dielectric layer and including tantalum oxide and a barrier oxide, and an upper electrode disposed on the protection insulating layer.

Abstract: A capacitor having a configuration in which capacitors are coupled in series to each other is described. The capacitor formed on a substrate according to an exemplary embodiment of the present invention includes: a polysilicon layer doped with an impurity; a first insulation layer formed on the polysilicon layer; a first metal layer formed on the first insulation layer and including first and second areas; a second insulation layer formed on the first metal layer; and a second metal layer formed on the second insulation layer and coupled to the second area of the first metal layer. The second metal layer is overlapped with at least a part of the first area of the first metal layer.

Abstract: A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10.

Abstract: An assembly (60) includes a substrate (1) that is provided with at least one electrical contact (3a), a flexible printed circuit membrane (51) including an electrically insulating film (6) and an electrically conducting layer (7) that is at least partially covering the insulating film (6). The conducting layer (7) is at least locally accessible from outside of the membrane (51). A connection element (10) is provided for electrically connecting the at least one electrical contact (3a) and the conducting layer (7) at a position where the conducting layer (7) is accessible, to form an electrical connection between the substrate (1) and the membrane (51). A chip package (70) includes a housing (15) having at least one electrically conducting terminal, and an assembly (60) as mentioned. The flexible printed circuit membrane (51) is arranged for electrically connecting the substrate and the at least one terminal of the housing (15).

Abstract: Provided is a composite substrate manufacturing method, including at least: a first raw board deforming step of preparing a first substrate by deforming a first raw board having at least one surface as a minor surface into a state in which the minor surface warps outward; and a joining step of joining, after the first raw board deforming step, a protruding surface of the first substrate and one surface of a second substrate to each other, thereby manufacturing a composite substrate including the first substrate and the second substrate, in which the second substrate is any one substrate selected from a substrate having both surfaces as substantially flat surfaces and a substrate that warps so that a surface thereof to be joined to the first substrate warps outward. Also provided are a semiconductor element manufacturing method, a composite substrate and a semiconductor element manufactured.

Abstract: Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases.

Abstract: One embodiment describes a method of manufacturing a semiconductor device. Here, impurities are implanted into a semiconductor body via a first side of the semiconductor body. Thereafter, a drift zone layer on the first side of the semiconductor body is formed. The following is an ablation of the semiconductor body from a second side of the semiconductor body and up to pn junction defined by impurities.