Abstract: Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection.

Abstract: According to one embodiment, there is provided a semiconductor device including a first amplifier and a second amplifier. The first amplifier has an input terminal to receive a first signal and an output terminal to output a second signal. The second amplifier is configured to receive the first signal and a correction data, to generate a correction signal according to the first signal and the correction data, and to output the generated correction signal to the output terminal of the first amplifier so as to add the first signal and the generated correction signal.

Abstract: A semiconductor device outputs a signal to control a gate potential a switching device. The semiconductor device includes a first signal output terminal, and is capable of receiving or internally creating a reference signal, which varies between a first potential and a second potential. The semiconductor device can switch between first and second operations. The first operation outputs to the first signal output terminal a signal that is at a third potential when the reference signal is at the first potential, and that is at a fourth potential higher than the third potential when the reference signal is at the second potential. The second operation outputs to the first signal output terminal a signal that is at the fourth potential when the reference signal is at the first potential, and that is at the third potential when the reference signal is at the second potential.

Abstract: A control voltage is generated at a control input of a semiconductor circuit breaker by an actuation circuit at switching flanks of a switching signal, said control voltage having a profile which is flattened in relation to the profile of the switching signal. With the disclosed method, the switching losses in a semiconductor circuit breaker are reduced. By defining a value for a switching parameter of a control device of the actuation circuit, the switching behavior of the actuation circuit can be influenced by the switching parameter. A specific parameter value of the switching parameter can be varied during operation of the actuation circuit.

Abstract: A semiconductor device which has reduced power consumption and includes a selection transistor is provided. A semiconductor device in which the number of wirings and terminals for inputting a power supply potential is reduced and which operates at high speed is provided. A buffer circuit connected to a gate line connected to a gate of the selection transistor has a function of generating a potential higher than a high power supply potential by using the high power supply potential and outputs the potential depending on the selection signal. A bootstrap circuit boosts a high power supply potential that is input to an inverter that is the closest to an output side among a plurality of inverters included in a buffer circuit. Further, by providing a delay circuit in the buffer circuit, the bootstrap circuit starts to boost a potential at the timing later than the input of the selection signal.

Abstract: A voltage select circuit includes a plurality of first transfer elements configured to transfer respective operating voltages to a first output terminal, a transfer select circuit unit configured to output a first voltage necessary to transfer an operating voltage, selected from among the operating voltages, to at least one first transfer element in response to a plurality of enable signals, and a control circuit configured to boost the first voltage to a second voltage in response to the plurality of enable signals.

Abstract: New designs of high power switching circuits and controller circuits are provided. Principal silicon bipolar switch is connected in parallel to snubber switch that is formed of a wide bandgap material. The snubber switch is activated during at least one of turn-on and turn-off of the principal silicon switch so as to minimize (or reduce) the switching loss and to bypass safe operation area limitations.

Abstract: In a bidirectional switch using a metal-oxide-semiconductor field-effect transistor (MOSFET), the source terminal and the backgate terminal of the MOSFET are connected to each other via a transfer gate. A switch may be used between the connection point of the backgate terminal and the transfer gate of the MOSFET and the ground potential (where the MOSFET is an n-channel type) or supply potential (where the MOSFET is a p-channel type).

Abstract: A proportional to absolute temperature (PTAT) current generation circuit may include a current mirror unit and/or a level control unit. The current mirror unit may be connected between a first power supply voltage, a first node, and/or a second node. The level control unit may be connected between the first node, the second node, and/or a second power supply voltage. The level control unit may be configured to control a level of an output current of the current mirror unit based on a voltage level of the first node and a voltage level of the second node. The level control unit may include a first transistor connected between the first node and the second power supply voltage, at least one second transistor connected between the second node and a third node, the at least one second transistor configured to operate in a weak inversion region, and/or a third transistor connected between the third node and the second power supply voltage.

Abstract: A CPU outputs a high level ENB signal to a USB-IC via an ENB line and monitors, after outputting the ENB signal, whether or not there is an overcurrent in the USB-IC on the basis of the voltage level of the ENB line. The USB-IC outputs, when it receives the ENB signal, a 5 V voltage to a VBUS line and stops, when an overcurrent occurs, output of the 5 V voltage to the VBUS line. A connector changes the voltage level of the ENB line to a high voltage level using the 5 V voltage of the VBUS line and changes, when output of the 5 V voltage is stopped, the voltage level of the ENB line to a low level. Thus, the ENB line may be shared for outputting the ENB signal from the CPU and for providing notification of an overcurrent from the USB-IC.

Abstract: An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.

Abstract: The application discloses a voltage regulation method, and a corresponding HPM, chip, and chip system. The method is used to regulate a working voltage of the chip, which includes an AVS module and at least one HPM. The method includes: outputting, by the AVS module, a clock signal to the HPM; generating, by the HPM, a corresponding pulse signal according to the clock signal and at least performing first delaying for the pulse signal to acquire a first actual output value and performing second delaying for the pulse signal to acquire a second actual output value; and fitting, by the AVS module, the first and second actual output values at least according to weights of the first and second actual output values to acquire a fitting output value and determine, by comparing the fitting output value with a predetermined reference value, whether to regulate the working voltage of the chip.

Abstract: Systems and methods for generating internal chip supply bias from high voltage control line inputs are presented. One of a plurality of the high voltage control lines is selected and accordingly internal path switching circuitry is enabled to pass the selected high voltage control line while protecting the associated components from over-stress.

Abstract: In accordance with one exemplary embodiment, an electronic circuit is provided, wherein the electronic circuit comprises a first transistor and also a second transistor coupled in series with the first transistor. Furthermore, the electronic circuit comprises a capacitor, wherein a first terminal of the capacitor is coupled to a control terminal of the second transistor, and wherein a second terminal of the capacitor is coupled to an electrical potential which is dependent on a radio-frequency input signal of the electronic circuit.

Abstract: One aspect of the present invention provides a method for improving power amplification efficiency of a Doherty power amplifier. The method is applied to a Doherty power amplifier that has two paths of Doherty circuit units connected in parallel. The method includes: when output power of the Doherty power amplifier is within a low out power range, adjusting, by a bias circuit, gate voltages of main power amplifiers and peak power amplifiers in the two paths of Doherty circuit units connected in parallel, in order to cause the peak power amplifiers to be in an off state, and the main power amplifiers in the two paths of Doherty circuit units connected in parallel to be in a main power amplification state and a peak power amplification state respectively.

Abstract: An RF amplifier suitable for use in an RF transceiver has a circuit including a first transistor pair with the collector of each coupled to one of the two differential output nodes and a common base. A pair of Ft doublers is provided with the emitter of each Ft doubler coupled to one of the transistors in the first transistor pair. Each Ft doubler has a common emitter and a base coupled to one of the differential input nodes. As such, the first transistor pair and the Ft doubler pair are cascode-coupled to provide a wide bandwidth, high gain, and high input impedance RF amplifier.

Abstract: A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a wa

Abstract: There is provided a power amplifier including a bias circuit unit generating a bias voltage of an amplifying unit, a voltage drop unit disposed between the bias circuit unit and the amplifying unit to drop the bias voltage to a base voltage, and a bypass circuit unit including an impedance element connected to the voltage drop unit in parallel and performing a switching operation according to a magnitude of an input signal.

Abstract: According to embodiments of the present invention, an over-input signal may be limited to be within a range between adjustable upper limit voltage and lower limit voltage while suppressing deterioration of a noise figure. An amplifier circuit includes an input transistor; an input transistor; a resistor element having a first terminal connected to a gate of the input transistor and a second terminal connected to a bias voltage; and a protective circuit connected to the gate of the input transistor and limiting an input to the gate of the input transistor to be within a range between an upper limit voltage and lower limit voltage adjustable based on the bias voltage.

Abstract: There is provided a radio frequency amplifying apparatus having a protection voltage varying function, including a radio frequency amplifying unit amplifying a radio frequency signal, and a protection circuit unit connected between an output node of the radio frequency amplifying unit and a ground and limiting a voltage in the output node to a level of a preset protection voltage or less when the voltage in the output node is higher than the preset protection voltage, wherein the protection voltage is varied with a control signal.

Abstract: A multi-stage amplifier is provided that uses tunable transmission lines, as well as a calibration method for the multi-stage amplifiers. A multi-stage amplifier, comprises a plurality of tunable amplification stages, wherein each of the tunable amplification stages comprises a tunable resonator based on a transmission line having a tunable element. The tunable elements may vary a capacitance or an inductance to tune a frequency of an applied signal. A calibration method is provided for a multi-stage amplifier having a plurality of transmission lines, an input stage and an output stage. The multi-stage amplifier is calibrated by generating a signal to determine a frequency for a substantially maximum power; generating an error signal by comparing the frequency for the substantially maximum power with a desired frequency; varying a digital control code applied to each of the tunable transmission lines, input stage and output stage until the error signal satisfies predefined criteria.

Abstract: A method of forming a circuit includes forming a transimpedance amplifier having a first input node and a second input node. The method also includes forming a feedback circuit having a first transistor having a drain terminal connected to the first input node, a source terminal, and a gate terminal, a second transistor having a drain terminal connected to the second input node, a source terminal, and a gate terminal, and a third transistor having a drain terminal connected to the source terminal of the first transistor and the source terminal of the second terminal.

Abstract: A method includes determining a control setting and selectively stopping oscillation of an oscillator after a time period. The oscillator is configured to remain in an active mode after the time period. The method further includes applying the control setting to the oscillator.

Abstract: There is provided an oscillator arrangement for generating a clock signal. The oscillator arrangement comprises a current controlled oscillator, a frequency to voltage converter, and an operational amplifier. The oscillator arrangement is connectable to a supply voltage source. In one embodiment, the oscillator arrangement may achieve a stable clock frequency insensitive to supply and temperature variation with low current consumption and low area. This may be achieved by using Vref and Vout as input signals to the operational amplifier, both signals being directly derived from the supply voltage. In a further embodiment, a trimming resistor may be used in the frequency to voltage converter for adjusting the frequency.

Abstract: A method and a phase locked loop (PLL) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO). The PLL circuit includes a reference circuit generates a virtual ground node for biasing noise sensitive components, providing level shifted VCO increment and decrement tuning values from a phase detector coupled by a respective resistor to tune a varactor of the LC VCO, and providing a loop filter function. The virtual ground node tracks a logic power supply noise, incurring no jitter penalty, and eliminating the need for a separate power supply for the PLL circuit.

Abstract: A cascaded oscillator array includes a first oscillator array and a second oscillator array. The first oscillator array includes at least three oscillator elements coupled unidirectionally in a first ring such that the first oscillator array outputs a first oscillating signal. Each of the at least three oscillator elements is coupled to receive a signal from a sensing element. The second oscillator array includes at least three oscillator elements coupled unidirectionally in a second ring such that the second oscillator array outputs a second oscillating signal. A first number of the at least three oscillator elements of the first oscillator array is the same as a second number of the at least three oscillator elements of the second oscillator. Each oscillator element of the at least three oscillator elements of the second oscillator array is coupled to receive an output signal from a single oscillator element of the at least three oscillator elements of the first oscillator.

Abstract: The present invention is to provide a frequency jitter circuit and a method for generating frequency jitter. The frequency jitter circuit, comprising: an oscillating circuit, configured to generate an oscillating frequency output signal; a decoding circuit, configured to be controlled by said oscillating frequency output signal for generating several pulse output signals; a delay circuit, through which said oscillating frequency output signal is passed for generating a frequency jitter output signal that is delayed a period of time compared to said oscillating frequency output signal. Application of the invention into switched-mode power supply might reduce EMI average noise in the switched-mode power supply, and smooth energy spectrum density.

Abstract: A push-push oscillator circuit with a first oscillation branch with a first active device and a first tank adapted to provide a signal having a fundamental frequency f0, a second oscillation branch with a second active device and a second tank symmetrical to the first oscillation branch and adapted to provide a signal having the fundamental frequency f0. Output branches are coupled to the first oscillation branch and the second oscillation branch to provide signals having the second harmonic frequency 2f0 of the fundamental signal based on the signals having the fundamental frequency f0 and/or to provide signals having the fundamental frequency f0; The push-push oscillator circuit further comprises at least one terminal branch with a terminal adapted to provide a component of a differential signal having the second harmonic frequency 2f0 or the fundamental frequency f0. The at least one terminal branch comprises a RF stub.

Abstract: An amplifier and oscillator system includes a MEMS resonator and a two stage amplifier topology. The MEMS resonator is configured to generate a resonator signal. The two-stage amplifier topology is configured to amplify the resonator signal with a selected trans-impedance gain. Additionally, the two stage amplifier topology yields a feedback resistance that provides the selected trans-impedance gain.

Abstract: A method for reducing the phase noise of a oscillator includes monitoring a phase slope of a resonator, and controlling the resonator to operate the resonator at a high phase slope condition, wherein the resonator comprises a piezoelectric material, or piezoelectric quartz.

Abstract: Methods, apparatuses, systems and computer-readable media for addressing the aging of oscillation (XO) crystals are presented. Some embodiments may determine a change of age of the XO crystal since last prior use of the XO crystal. Embodiments may then determine that at least one calibration parameter is not suitable for use in at least one calibration technique of the XO crystal, based on the change of age of the XO crystal. Embodiments may then determine at least one fresh calibration parameter configured to update the at least one calibration parameter for suitable use in the at least one calibration technique of the XO crystal.

Abstract: A digitally-controlled oscillator (DCO) includes a first capacitor array and a second capacitor array responsive to an integer part and a fractional part of a digital control word, respectively. The mismatch measurement of the DCO includes a first settling phase and a second settling phase. In the first settling phase, the first capacitor array is fixed to have one capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to a target value. In the second settling phase, the first capacitor array is fixed to have another capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to the same target value. The capacitor mismatches are estimated according to characteristic values derived from the digital control word adaptively adjusted in the first setting phase and the second setting phase.

Abstract: A modulation method is provided. The modulation method includes the steps of receiving multiple sinusoidal signals, obtaining the maximum value of the sinusoidal signals, obtaining the median value of the sinusoidal signals, and obtaining the minimum value of the sinusoidal signals within a period to generate a difference between the maximum value and the minimum value, generating a difference according to an upper limit and a lower limit of a predetermined comparison value, and comparing the two differences to generate an optimized modulation signal.

Abstract: Rectangular-shape resonators as guard traces formed in a region between the victim and aggressor lines are disclosed. No shorting-vias or resistors are required. The rectangular resonators are found to have functions of improving far-end crosstalk (FEXT) and timing jitter in both frequency domain and time domain if the parameters are appropriated selected.

Abstract: A circuit substrate has three wiring layers, wherein a signal line is formed in a first wiring layer; a ground plane is formed in a second wiring layer; a resonant line is formed in a third wiring layer. A circumferential slit is formed in the ground plane, wherein an island electrode separated from the ground plane is formed inside the slit. The left end of the resonant line is connected to the island electrode through an interlayer-connecting via, while the right end of the resonant line is connected to the ground plane through an interlayer-connecting via. A transmission line (or a microstrip line) is formed using the signal line and the ground plane, and therefore a complex resonator is formed to embrace the transmission line. This achieves band elimination with regard to a signal component of a resonance frequency among signals propagating through the microstrip line.

Abstract: A stacked diode limiter, which can suppress and eliminate a malicious high-power electromagnetic pulse signal and an Intentional Electromagnetic Interference (IEMI) signal that are input to the antenna line of a wireless system and that include a communication service frequency component having a power of several kW or more, includes a stacked diode unit including one or more diode stack parts formed on a center electrode of a coaxial line formed between an input connector and an output connector, each diode stack part being configured such that a plurality of diodes are arranged in series and stacked on top of one another, and an impedance matching unit for configuring dielectrics between the connectors and the coaxial line as heterogeneous dielectrics and matching impedances between the connectors and the coaxial line.

Abstract: An antenna duplexer includes first and second filters connected to an antenna terminal. The first filter has a passband of a low frequency band. The second filter has a passband of a high frequency band. The second filter is a ladder-type filter including series-arm resonators and parallel-arm resonators. At least one parallel-arm resonator out of the parallel-arm resonators has a main resonance and an auxiliary resonance. Attenuation poles caused by the main resonance and the auxiliary resonance are within the low frequency band. This antenna duplexer has a high attenuation characteristic and a high isolation characteristic while maintaining a low insertion loss.

Abstract: A waveguide has distal, medial and proximal sections. The distal and medial sections rotate relative to each other and to the proximal section. In a first configuration, the waveguide transforms linearly polarized electromagnetic radiation at the proximal end of the proximal section to linearly polarized electromagnetic radiation at the distal end of the distal section and vice versa. In a second configuration, the waveguide transforms linearly polarized radiation at the proximal end of the proximal section into circularly polarized electromagnetic radiation at the distal end of the distal section and vice versa. Preferably, the distal and medial sections include respective eight-wavelength polarizers and the proximal section includes a quarter-wavelength polarizer. A multi-band antenna feed includes two such waveguides, one nested inside the other, for transforming electromagnetic radiation of respective frequency bands.

Abstract: An ortho-mode transducer may include a cylindrical common waveguide terminating in a common port, a rectangular vertical branch waveguide in-line with the cylindrical common waveguide and terminating in a vertical port, and a rectangular horizontal branch waveguide normal to the common waveguide and terminating in a horizontal port. The vertical branch waveguide may be configured to couple a first linearly polarized mode from the vertical port to the common waveguide. The horizontal branch waveguide may be configured to couple a second linearly polarized mode, orthogonal to the first linearly polarized mode, from the horizontal port to the common waveguide. A portion of the vertical branch waveguide may overlap a portion of the cylindrical common waveguide. A septum may span the vertical branch waveguide proximate to the overlapping portions of the vertical branch waveguide and the common waveguide. A rectangular symmetry cavity may be opposed to the horizontal branch waveguide.

Abstract: A vehicle-mounted noise filter which suppresses electric field coupling between input and output terminals in the FM radio band, thereby allowing noise attenuation performance, which should originally be provided to a noise filter circuit, to be exhibited even in the FM radio band. The vehicle-mounted noise filter comprises a coil (1) obtained by winding a conductive wire around a magnetic core, input and output terminals (2, 3) electrically connected to both terminals of the coil, and a shielding member (4). The shielding member (4) is made of a conductive member which is grounded and disposed so as to shield the electric field between the input and output terminals (2, 3). The noise filter can also be configured using a capacitor having one terminal electrically connected to the coil (1) and the other terminal grounded.

Abstract: A ferrite bead inductor comprises a ferrite bead element body having magnetic layers and inner electrodes stacked therein, and first and second outer electrodes arranged on first and second side faces of the ferrite bead element body. The inner electrode extends in the direction of shorter sides which are shorter than longer sides, so as to connect with the first and second outer electrodes. The ferrite bead element body has an interstice for allowing the magnetic layers adjacent to each other in the stacking direction to join together within an inner electrode region adapted to form the inner electrode on the magnetic layer.

Abstract: A noise filtering circuit for suppressing electromagnetic interference (EMI) is provided. The noise filtering circuit filters out high multiplied-frequency noise of a digital signal being transmitted and includes a reference voltage structure formed from conductors, a signal transmitting structure formed from a transmission conductor, a ground layer, and a ground structure electrically connected to the reference voltage structure and the ground layer. The ground structure is configured to form an inductor-capacitor oscillating structure in coordination with the electric-magnetical coupling between the reference voltage structure and the signal transmitting structure as well as the inductance of the ground structure, so that a digital signal is filtered out at a specific frequency and the passband of the digital signal can be transmitted.

Abstract: A common mode filter is disclosed. The common mode filter in accordance with an aspect of the present invention includes: a first dielectric layer having a first groove formed along an outer boundary portion thereof; a second dielectric layer coated on the first dielectric layer so as to cover a first coil laminated on the first dielectric layer, having a first protrusion corresponding to the first groove formed on one surface thereof being in contact with the first dielectric layer, and having a second groove formed on the other surface thereof; and a third dielectric layer coated on the second dielectric layer so as to cover a second coil laminated on the second dielectric layer, having a second protrusion corresponding to the second groove formed on one surface thereof being in contact with the second dielectric layer, and having a third groove formed on the other surface thereof.

Abstract: A surface acoustic wave SAW (SAW) device has a substrate and a filter provided at the substrate. The filter has a plurality of interdigital transducers (IDT) electrodes arranged along a propagation direction of a SAW. Each of the plurality of IDT electrodes has an electrode finger group including a plurality of electrode fingers which extent in a direction orthogonal to the propagation direction and are arranged along the propagation direction. At least one of the plurality of IDT electrodes has a wide pitch section including an adjacent first and second electrode finger among the plurality of electrode fingers. The interval between the first electrode finger and the second electrode finger is larger than the average value of the intervals between the remaining electrode fingers of the plurality of electrode fingers.

Abstract: A resonant element is provided with a multilayer board, comprising a plurality of conductor layers isolated by a dielectric, a signal via conductor, penetrating through the multilayer board, and a plurality of ground vias, penetrating thought the multilayer board and disposed around the signal via conductor. The multilayer board comprises a first conductor layer, a second conductor layer, and a corrugated conductor layer disposed between the first and the second conductor layers. The corrugated conductor layer comprises a corrugated signal plate, connected to the signal via conductor, and a corrugated ground plate, connected to the plurality of ground vias, isolated from the corrugated signal plate by the dielectric.

Abstract: A thin film resonator for a wireless power transmission is provided. The thin film resonator may include a first transmission line unit provided as a thin film type, a second transmission line unit also provided as the thin film type, and a capacitor inserted at a predetermined position of the first transmission line unit.

Abstract: An electromagnetic contactor has an arc extinguishing chamber housing a contact mechanism having a pair of fixed contacts and a movable contact that contacts with the pair of fixed contacts. The arc extinguishing chamber has a plate-shaped fixed contact support insulating substrate including through holes to fix at least the pair of fixed contacts and formed with a metal foil on an outer peripheral circumferential edge of one surface by a metalizing process. The pair of fixed contacts and a metal cylindrical body are brazed and joined to the metal foils of the fixed contact support insulating substrate, and an insulating cylindrical body is disposed on an inner peripheral surface of the metal cylindrical body.

Abstract: The invention relates to a novel permanent magnet electromagnetic actuator with triggering speed and drive torque improved relative to those of the prior art. The main target application is actuating an electromechanical switch-disconnector specifically for performing the operations to disconnect a mechatronic circuit-breaker for breaking high-voltage direct currents.

Abstract: A stepped portion is formed in an outer peripheral portion of a slide core and is stepped to reduce an outer diameter of one portion of the slide core located on one axial side of the stepped portion. A first conducting portion of a ring core covers an outer peripheral surface of the one portion of the slide core and is slidable along an outer peripheral surface of the one portion of the slide core. The first conducting portion conducts a magnetic flux between the first conducting portion and the slide core in a radial direction. A second conducting portion of the ring core is configured into a form of a flange and radially outwardly extends from the first conducting portion. The second conducting portion conducts the magnetic flux between the second conducting portion and a bottom wall portion of a yoke in an axial direction.

Abstract: A material containing a soft magnetic substance is subjected to a plastic deformation such as a roll processing to obtain a rod-shaped body. Then, the rod-shaped body or a shaped body obtained by processing the rod-shaped body into a shape other than a flat plate shape is subjected to a heat treatment in the presence of a magnetic field. The rod-shaped body or the shaped body is made magnetic-anisotropic by the heat treatment thereby to obtain a magnetic-anisotropic plastically deformed body.