Abstract: A plural-frequency capacitive occupancy sensing system comprises an antenna electrode and a detection circuit, which is configured to drive the antenna electrode at least with a first and a second signal at a first and a second frequency, respectively, so as to obtain at least a first and a second measurement value indicative of at least one of conductance, susceptance, resistance, reactance and capacitance between the antenna electrode and a reference node, at the first frequency and the second frequency, respectively. The detection circuit compares the capacitance between the antenna electrode and the reference node with a threshold capacitance, the threshold capacitance being derived from a difference between the first and second measurement values and/or the capacitance between the antenna electrode and the reference node being corrected based upon the difference between the measurement values. The detection circuit outputs an occupancy state signal depending on the comparison.

Abstract: The invention relates to a method for measuring the permittivity and/or perviousness of a sample of a nonconductive material, said method comprising: a) measuring a value representative of an admittance Ytestco, b) measuring a value representative of an admittance Ytestcc only from the amplitude and the phase of the electromagnetic waves reflected onto an interface between the sample and the end of a second waveguide having at least one conductive web separated from a conductive sheath by a layer of dielectric material, said second waveguide also including a short circuit between the central web and the sheath at the interface with the sample, and c) calculating the permittivity of the sample from the values representative of the admittances Ytestco and Ytestcc and/or calculating the perviousness of the sample from the values representative of the admittances Ytestco and Ytestcc.

Abstract: A semiconductor device and a detection method thereof are provided. The semiconductor device includes a resistor terminal, a dummy pull up driver, a comparator and a detection state machine. The resistor terminal is connected to an external resistor. The dummy pull up driver provides driving operations of 20 to 2N+1?1 stages, wherein N is a natural number. The comparator outputs a comparison signal in response to a test voltage and a reference voltage. The detection state machine controls the driving operation of the dummy pull up driver to generate and output a detection signal according to the comparison signal. The detection signal indicates an electric connection state of the resistor terminal is a connecting state of an operation voltage or a floating state, a connecting state of the external resistor, or a connecting state of a ground voltage.

Abstract: A low-voltage testing device for a high-voltage frequency converter of a serial superposition voltage type including a tap transformer, power portion, monitoring box, analog interface board, voltage detecting portion and remote control portion, in which the tap transformer is connected to the power portion, the power portion is connected to the voltage detecting portion, the monitoring box is connected to the power portion via an optical fiber and the analog interface board is connected to the monitoring box and the remote control portion respectively.

Abstract: A method for automatically measuring a property of a fluid associated with a drilling application, including obtaining a sample of the fluid, wherein the sample of the fluid is obtained by directing the fluid through an electrode probe assembly comprising an electrode probe and depositing the fluid in a probe gap between electrodes of the electrode probe, ramping up a voltage applied to the electrodes of the electrode probe until a threshold current is obtained, recording the breakdown voltage at the threshold current value, and using the breakdown voltage to compute the property of the sample of the fluid.

Abstract: A probe apparatus has probe wires with a contact pattern on one side. The contact pattern is for contacting a respective contact pattern on another test equipment or component, such as a circuit board. The probe wires have tips that probe a device desired for testing. Signals are transmitted through the probe wires from the probe card, for example, through a circuit board to other diagnostic equipment. The contact of the probe card with the circuit board allows signals to be transferred through the probe wires to the other diagnostic equipment. On another side of the probe card is a connector structure. The connector structure includes a retainer that can allow the probe card to be replaced from a test system, such as allowing it to be connected and disconnected from a holder.

Abstract: Various embodiments for detecting a high Intensity radiated field (HIRF) in a line replaceable unit are provided. In an embodiment, the internal detector comprises a receiving means for receiving HIRF and generating an AC signal proportional to the HIRF, an RF filter configured to sample the AC signal to create a DC signal; and a detecting section configured to compare the DC signal with a threshold and output a result of the comparison to a built-in test section. The internal detector may be used to test EMI filter pin connectors of a closed line replaceable unit.

Abstract: A method of detecting a fault in a de-icer probe for measuring a physical parameter on an airplane engine, the method including: prior to starting an engine, measuring a first value of the physical parameter with help of the probe; activating the probe de-icer; at an end of a determined duration from a start of de-icing, measuring a second value of the parameter with help of the probe; and comparing the first and second values and generating a fault signal if the difference between the first and second values is less than a determined threshold.

Abstract: A test device including cobra probes and a method of manufacturing is disclosed. The test device includes a conductive upper plate having an upper guide hole and a conductive lower plate having a lower guide hole. The test device also includes a conductive cobra probe disposed between the upper guide hole of the upper plate and the lower guide hole of the lower plate. A dielectric material insulates the cobra probe from the upper plate and the lower plate.

Abstract: A test carrier includes a film-shaped base film which has first bumps which contact test pads of a die; and a cover film which is superposed over the base film, and the test carrier holds the die between the base film and the cover film. The first bumps are relatively higher than second bumps which the die has.

Abstract: Various embodiments are described and illustrated for mitigating a potential system or screen freeze during an electrostatic discharge.

Abstract: Illustrative embodiments of systems and methods for variation-tolerant, self-repairing displays are disclosed. In one illustrative embodiment, a display panel may include one or more defective pixels and a compensation circuit may be configured to extend a charging time of each of the one or more defective pixels. In another illustrative embodiment, a method may include detecting one or more defective pixels in a pixel array and extending a charging time of each of the one or more defective pixels.

Abstract: A method of testing a packaged semiconductor device under test (DUT) including a leadframe having a plurality of pins and at least one thermal pad with a semiconductor die having topside bond pads wire-bonded by bond wires to the plurality of pins and secured to the thermal pad. A leadframe sheet is provided including a plurality of packaged DUTs including support members that connect to the packaged DUTs. The thermal pads are shorted to one another, and the leadframe sheet is trimmed for electrically isolating the pins from one another. A first electrical contact is provided to the thermal pad. Active pins of the plurality of pins are electrically contacted with a contactor. Automatic testing identifies shorts between the active pins and the thermal pad.

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Abstract: A transmission line driver including an output configured to have a load impedance is provided. The transmission line driver includes a pull-up circuit coupled in series with the output. The transmission line driver also includes a pull-down circuit coupled in series with the output. The transmission line driver includes a shunt circuit having an adjustable impedance. The shunt circuit is coupled in parallel to the output. The shunt circuit is coupled to the pull-up circuit and the pull-down circuit. The shunt circuit is configured to receive a shunt control signal to adjust the adjustable impedance to provide linear control of an output swing at the output.

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included.

Abstract: A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.

Abstract: A level shifter and integrated level shifter and metastability resolution flop circuit are disclosed. A circuit includes a generation circuit, in a first voltage domain, coupled to receive a logic signal via a single-ended input and configured to generate true and complementary values of the logic signal. The circuit further includes a storage circuit coupled to receive the true and complementary values of the logic signal from the generation circuit. The storage circuit is configured to store the true and complementary values of the logic signal. The storage circuit is in a second voltage domain. The circuit further includes an output circuit coupled to the storage circuit and configured to provide a differential output signal having true and complementary values corresponding to the true and complementary values of the logic signal. The circuit may be combined with a latch circuit coupled to receive the differential output signal.

Abstract: Apparatus and methods related to data transmission are disclosed. One such apparatus includes a transmitter, a receiver, and a channel. The transmitter includes a pair of current sources and a pair of switches. Each of the switches conducts one of the current sources to the channel in response to input data. The receiver includes a first node configured to receive a signal over the channel. The receiver also includes a resistance generating a voltage drop between the first node and a second node. The receiver further includes a first transistor and a second transistor that are together configured to provide a voltage level to the second node based at least partly on the voltage drop. The resistance provides a negative feedback to center the mean signal level, thereby reducing intersymbol interference.

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection; the first layer includes a first clock distribution structure, the first clock distribution structure includes a first clock origin, the second layer includes a second clock distribution structure, the second clock distribution structure includes a second clock origin, and the second clock origin is feeding the first clock origin.

Abstract: A semiconductor integrated circuit device includes a first flip-flop circuit receiving data in synchronization with a first clock signal, a logic circuit performing a predetermined process on data output from the first flip-flop circuit, a hold buffer delaying transmission of an output of the logic circuit, a second flip-flop circuit receiving an output of the hold buffer in synchronization with a second clock signal, and a power supply circuit capable of selecting a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage. A power supply voltage supplied to the hold buffer remains the same when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes between first and second power supply voltages.

Abstract: A digital cell for performing a logic operation on a logic input to produce a logic output, includes an evaluation block and a sense-amplifier block, both configured to receive input signals representative of the logic input, and to detect when the logic input and/or input signals validly encode at least one bit. The digital cell is configured to alternate between an evaluate state and a reset state. Upon the digital cell being in the reset state and the detection, the digital cell is switched from the reset state to the evaluate state in which the evaluation block generates a difference in its output signals, and the sense-amplifier block amplifies the difference so that the output signals encode at least one valid bit. Upon the digital cell being in the evaluate state, the digital cell can be triggered to reset to the reset state.

Abstract: A system includes an ADC that, based on a first clock signal, converts an analog signal into a digital signal. A first circuit generates a second clock signal based on the digital signal. An interpolator generates a phase delayed version of the second clock signal and a third clock signal. The third clock signal is generated based on the second clock signal and the phase delayed version and includes transitioning from the second clock signal to the phase delayed version. The third clock signal includes pulses each having a first pulse width and a pulse having a second pulse width. The second pulse width is different than the first pulse width due to the transition from the second clock signal to the third clock signal. A second circuit removes the pulse having the second pulse width from the third clock signal to generate the first clock signal.

Abstract: An electronic circuit includes: a weighting circuit configured to generate a first current by weighting and combining a first input signal and a second input signal in accordance with a modifiable coefficient and to generate a second current by weighting and combining a first inverted signal and a second inverted signal in accordance with the coefficient, the first inverted signal being an inverted signal of the first input signal, the second inverted signal being an inverted signal of the second input signal; and a decision circuit configured to decide on an output signal by comparing the first current with the second current.

Abstract: Various embodiments provide a method for processing a stimulation signal. The method may include monitoring an output voltage on an electrode, the electrode being provided with the stimulation signal; determining whether the output voltage is lower than a threshold voltage; if it is determined that the output voltage is lower than the threshold voltage, modifying the waveform of the stimulation signal; and providing the modified stimulation signal to an object via the electrode.

Abstract: The present invention is directed to prevent occurrence of a problem on a withstand voltage in a circuit group which receives supply of an internal power supply voltage. An error amplifier outputs a control voltage obtained by amplifying a difference voltage between a reference voltage and a divided voltage obtained by dividing an internal power supply voltage to an output node. A drive transistor supplies a drive current according to the control voltage of the output node of the error amplifier from an external power supply line to an internal power supply line. When the divided voltage exceeds a predetermined voltage, a clamp circuit changes the control voltage in the direction of decreasing the drive current.

Abstract: In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.

Abstract: An output driver and a data output driving circuit using the output driver includes a pull-up driver including at least three pull-up transistors connected between a high voltage and an output node in a stack structure of three stages or more and a pull-down driver including at least three pull-down transistors connected between a ground node and the output node in a stack structure of three stages or more.

Abstract: A method for driving a controllable power semiconductor switch, having a first input terminal and first and second output terminals coupled to a voltage supply and a load, the first and second output terminals providing an output of the power semiconductor switch, includes adjusting a gradient of switch-off edges of an output current and an output voltage of the power semiconductor switch by a voltage source arrangement coupled to the input terminal. A gradient of switch-on edges of an output current and an output voltage is adjusted by a controllable current source arrangement that is coupled to the input terminal and generates a gate drive current. The profile of the gate drive current from one switching operation to a subsequent switching operation, beginning at a rise in the output current and ending at a decrease in the output voltage, is varied at most within a predefined tolerance band.

Abstract: A voltage controlled switching element gate drive circuit makes it possible to suppress an occurrence of a malfunction, while suppressing surge voltage, surge current, and switching noise, when switching in a voltage controlled switching element. A gate drive circuit that supplies a gate voltage to the gate of a voltage controlled switching element, thus driving the voltage controlled switching element, includes a high potential side switching element and low potential side switching element connected in series, first variable resistors interposed between at least the high potential side switching element and a high potential power supply or the low potential side switching element and a low potential power supply, and a control circuit that adjusts the resistance values of the first variable resistors.

Abstract: A clock buffer circuit can include a low voltage drive circuit that receives a clock signal and provides a low voltage drive at a first power supply potential to a load. A boost drive circuit can provide a high voltage drive at a second power supply potential greater than the first power supply potential to the load. The boost drive circuit can provide the high voltage drive in response to a pulse signal generated in response to a transition of a clock input signal. A pulse generator circuit may generate the pulse signal to have a predetermined width to enable the high voltage drive until the load is charged essentially to the first power supply potential.

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract: A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

Abstract: A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.

Abstract: A semiconductor device may include first to fourth output lines, an input signal latch unit suitable for latching first to fourth input signals that are sequentially inputted in response to first to fourth clocks having sequential phases, respectively, a valid signal latch unit suitable for latching a valid signal in response to one clock among the first to fourth clocks, where the valid signal corresponds to one input signal among the first to fourth input signals and represents whether the corresponding input signal is valid or not, and a signal transfer unit suitable for transferring the latched input signals, which are obtained by latching the input signals in response to the first to fourth clocks, to the first to fourth output lines based on a correspondence relationship that is decided based on a valid signal latch result of the valid signal latch unit.

Abstract: A frequency synthesizer capable of generating a clock signal having reduced digital spurs and reduced jitter is described. An apparatus includes a frequency modulator configured to generate a divide control signal and a digital quantization error signal in response to a divide ratio. The apparatus includes a phase modulator configured to generate a phase error signal based on the digital quantization error signal. The phase modulator is an n-order sigma-delta modulator module, n being an integer greater than one. The apparatus may include an interpolative divider configured to generate a feedback signal in a phase-locked loop (PLL) based on an output signal of the PLL, the divide control signal, and the phase error signal. The interpolative divider may include the frequency modulator and the phase modulator. The phase modulator may have a unity gain signal transfer function.

Abstract: A synchronization circuit may include: a variable delay unit configured to delay a first clock signal by a first delay time set in response to a delay control signal and generate a second clock signal; a first path configured to detect a phase difference between the first clock signal and a third clock signal generated by delaying the second clock signal by a second delay time and generate a phase difference detection signal; a second path configured to generate a second phase difference detection signal in response to a phase difference between the first clock signal and a fourth clock signal; and a control unit configured to generate the delay control signal in response to the phase difference detection signal and vary an update period of the delay control signal in response to the second phase difference detection signal.

Abstract: A method and system is disclosed in which the phase detector in a phase-locked loop is able to run at the fastest speed appropriate for a reference signal. A frequency offset is added to the output frequency of the phase-locked loop, to alter the frequency fed to the frequency divider which would receive the output frequency in a conventional PLL to an intermediate frequency. The frequency offset is selected so that the ratio of the intermediate frequency to the reference frequency is a simple fraction, and preferably an integer, i.e., the intermediate frequency is a multiple of the reference frequency. In cases where the relationship between the output frequency and the reference frequency is largely relatively prime, the phase detector is thus able to receive signals at the frequency of the reference signal and operate at the fastest speed appropriate for the reference signal.

Abstract: A PLL includes an oscillator, a time-to-digital converter (TDC) and a system for the remaining functionality. The TDC measures the oscillator's phase against a reference clock. The measured phase has an integer part obtained from a modulus-K counter, and a fractional part measured by a fine TDC. The system compares the measured phase with a desired phase, and filters it to obtain a parameter that controls the oscillator frequency. The TDC may also include a synchronization block to align the fine TDC and a pulse hider to reduce the power used by the fine TDC. The system may include an integrator to calculate the integer part of the desired phase, a second integrator to calculate the fractional part, and an interpolator for an even finer fraction. A method to obtain fast lock includes using the phase error rate of change to control the oscillator frequency.

Abstract: A logic unit is configured with least one multiplexor distributed along a delay path of a logic unit, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs to control a particular programmable number of clock cycles of delay added to a signal from 1 to N clock cycles. The logic unit is configured with at least two latches distributed along the delay path of the logic unit, wherein each at least one latch is configured to add a clock cycle of delay, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the particular programmable number of clock cycles.

Abstract: A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.

Abstract: In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.

Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.

Abstract: A period signal generation circuit including a control voltage generator and a period controller. The control voltage generator selecting one of temperature-dependent voltages to output the selected temperature-dependent voltage as a control voltage. The first and second temperature-dependent voltages varying according to a temperature and the third temperature-dependent voltage is constant regardless of variation of the temperature. The period controller configured to determine an amount of a current discharging from an internal node in response to the control voltage and outputs a periodic signal whose cycle time is determined according to a level of an internal signal induced at the internal node.

Abstract: Embodiments of a flip-flip circuit are disclosed that may allow a reduction in data setup time and lower switching power. The flip-flop circuit may include an input circuit, an output circuit, a clock circuit, and a feedback circuit. The clock circuit may be operable to generate internal clocks dependent upon received data, and the generated internal clocks may enable the feedback and input circuits.

Abstract: To reduce power consumption of a circuit (TEDC) which detects timing errors in a main flip-flop by determining whether or not output data signals of the main flip-flop and a shadow flip-flop correspond. The TEDC includes a power gating circuit (PGC) which performs power gating of the shadow FF and a reset circuit (RSTC) which resets an output signal of the shadow FF. The PGC makes the shadow FF in an active mode only when error detection needs to be performed; other than that, the PGC makes the shadow FF in a power saving mode. The RSTC supplies a certain voltage to an output terminal of the shadow FF in the power saving mode to suppress malfunction of the TEDC. A transistor using an oxide semiconductor is used to supply the voltage to the output terminal.

Abstract: A flip-flop circuit includes an input stage circuit, a middle stage circuit, an output stage circuit and a set/reset circuit. The input stage circuit is arranged for receiving a first signal from a first node, and selectively outputting a second signal at a second node according to at least one control signal. The middle stage circuit is coupled to the input stage circuit, and arranged for receiving the second signal, and selectively outputting a third signal at a third node according to the at least one control signal. The output stage circuit is coupled to the middle stage circuit, and arranged for receiving the third signal to output an output signal. The set/reset circuit is coupled to the second node and the third node, and arranged to receiving a set signal and a reset signal, and selectively determining a voltage level of the third signal at the third node.

Abstract: A semiconductor integrated circuit and a method operating the same are provided. The semiconductor integrated circuit includes a first clock network configured to divide a clock signal into first output clock signals with a high frequency, a second clock network configured to divide the clock signal into second output clock signals with a non-high frequency, a plurality of selection circuits configured to be connected between the first clock network and the second clock network, and configured to output one of the first output clock signals and the second output clock signals, according to a power mode, and a plurality of clock sinks configured to sink output clock signals respectively output from the selection circuits.

Abstract: A fully on-chip clock generator on an integrated circuit (“IC”) includes a frequency detector for receiving a reference current and providing a first voltage; an error integrator for receiving the first voltage from the frequency detector, comparing it with a reference voltage, and providing a control voltage; a voltage controlled oscillator (“VCO”) for receiving the control voltage from the error integrator, and providing an output clock; and a logic controller on the IC, coupled between the VCO and the frequency detector, and generating logic control signals for controlling the frequency detector. The fully on-chip clock generator requires no external crystal, but its power consumption is significantly lower than a relaxation oscillator that generates the same clock frequency.

Abstract: A method for dealing with high inrush current when voltage is applied to mixed voltage logic integrated circuits is disclosed. A depletion N-Channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or junction Field Effect Transistor (JFET) is added to a linear voltage regulator in mixed voltage logic integrated circuits. The Field Effect Transistor (FET) is utilized to allow the core voltage to come up with Input/Output voltage prior to turn-on of linear voltage regulator. Turn-on state of FET allows the core voltage to rise with Input/Output voltage until the FET threshold is reached across the gate. When threshold is reached, the FET turns off to allow linear voltage regulator turn on and take over supply power.