Abstract: Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions, with individual pillars having a pair of opposing vertically-extending sides along a cross-section. First conductivity type regions may be along first sides of the pillars, and second conductivity type regions may be along second sides of the individual pillars; with the second conductivity type regions contacting interconnect lines. Vertical NAND strings may be over the pillars, and select devices may selectively couple the NAND strings with the interconnect lines. The select devices may have vertical channels directly against the semiconductor material pillars and directly against upper regions of the first and second conductivity type regions. Some embodiments include methods of forming NAND memory constructions.

Abstract: A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: A method of sorting a multi-bit per cell non-volatile memory includes programming and reading to test an n-bit-per-cell (n-bpc) non-volatile memory, which has a plurality of m-bpc pages, where m is a positive integer from 1 through n. If the m-bpc page fails the test, counting a block associated with the failed m-bpc page to (m-1)-bpc blocks, wherein each said m-bpc page is subjected to at most one time of programming and reading. When m is equal to 1, the 0-bpc block corresponds to a bad block.

Abstract: A computer readable medium, a system and a method for flash memory device parameter optimization, the method may include: receiving or generating an estimate of a wear level of at least one group of flash memory cells of the flash memory device, and finding erase parameters and programming parameters to be applied on one or more groups of flash memory cells of the flash memory device in response to estimate of the wear level.

Abstract: Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification.

Abstract: An instruction to write to a location in the Flash memory is received. It is determining if the Flash memory exposes a level placement setting associated with defining what voltage range corresponds to what level. In the event it is determined that the Flash memory exposes a level placement setting, an accurate coarse write is performed on the location, including by configuring the level placement setting to be a first value, and after the accurate coarse write is performed on the location, a fine write is performed on the location, including by configuring the level placement setting to be a second value, in response to receiving the instruction.

Abstract: A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation.

Abstract: Disclose is a non-volatile memory (NVM) cell sensing circuit. The sensing circuit may include a sense-side-line conditioning circuit segment adapted to condition a sense-side-line of the NVM cell. Conditioning may include adjusting a charge density within the NVM cell sense-side-line during a first NVM cell current sensing phase. The conditioning circuit segment may also be adapted to maintain an NVM cell current sensing condition during a second NVM cell current sensing phase. Adjusting a charge density within the NVM cell sense-side-line may include inducing current in the sense-side-line in a direction opposite to the sensing current.

Abstract: A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.

Abstract: The present inventive concept provides a driving method of memory controller controlling nonvolatile memory device using variable resistive element. The memory controller may control a plurality of first memory devices and a second memory device. A number of write drivers in the second memory device may be driven when a number of first memory devices among the plurality of first memory devices are used. A different number of write drivers in the second memory device may be driven when a different number of first memory devices among the plurality of first memory devices are used.

Abstract: Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.

Abstract: Provided is a semiconductor memory device in which a plurality of first and second data lines coupled to a memory cell array are alternately arranged. The semiconductor memory device includes a first write driving circuit configured to load a plurality of first write data transmitted through a plurality of third data lines into the plurality of first data lines in response to a first write enable signal; a second write driving circuit configured to load a plurality of second write data transmitted through a plurality of fourth data lines into the plurality of second data lines in response to a second write enable signal; and a column control circuit configured to activate at least one of the first and second write enable signals during a given period, in response to a plurality of data width option modes, during a parallel test mode.

Abstract: A device, a computer readable medium and a method that may include performing a shortened read attempt of multiple data memory cells that store data to provide an estimate of the data; wherein the shortened read attempt has a duration that is shorter than a duration of a full read attempt; performing a shortened read attempt of redundant memory cells that store redundant information to provide an estimate of the redundant information; wherein the estimate of the redundant information is indicative of an expected number of data memory cells that store a certain logic value; determining, based on the estimate of the data, an estimated number of data memory cells that store the certain logic value; comparing the expected number to the estimated number; and providing the estimate of the data as a read result if the expected number and the estimated number equal each other.

Abstract: According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.

Abstract: Integrated circuit memory devices include a memory cell configured to receive a power supply signal and a write assist circuit. The write assist circuit is configured to improve write margins by reducing a magnitude of the power supply signal supplied to the memory cell from a first voltage level to a lower second voltage level during an operation to write data into the memory cell. The memory device further includes at least one bit line electrically coupled to the memory cell and a read assist circuit. The read assist circuit may be configured to improve read reliability by partially discharging the at least one bit line from an already precharged voltage level to a lower third voltage level in preparation to read data from the memory cell.

Abstract: A semiconductor integrated circuit includes a write path coupled to a pad, a read path coupled to the pad, and a reference voltage output control block configured to apply a reference voltage to the pad through the write path in response to a reference voltage monitoring signal. The read path is electrically isolated from the pad in response to the reference voltage monitoring signal.

Abstract: A method of avoiding a write collision in single port memory devices from two or more independent write operations is described. A first write operation having a first even data object and a first odd data object is received from a first data sender. A second write operation having a second even data object and a second odd data object is received from a second data sender at substantially the same time as the first write operation. The second write operation is delayed so that the first even data object writes to a first single port memory device at a different time than the second even data object writes to the first single port memory device. The second write operation is delayed so that the first odd data object writes to a second single port memory device at a different time than the second odd data object.

Abstract: Methods and devices for charging unselected bit lines are disclosed. The rate at which inhibited (or unselected) bit lines are charged may depend on a program condition. The program condition may be completion of a program loop. As another example, the program condition may be a certain program state completing or nearly completing programming. As one example, the bit lines may be charged at a faster rate prior to the program condition occurring than after the program condition. As another example, the bit lines may be charged at a slower rate prior to the program condition than after the program condition. Charging the unselected bit lines at a slower rate may reduce current consumption. Charging the unselected bit lines at a faster rate may allow for faster programming.

Abstract: A column repair circuit of a semiconductor memory apparatus includes a plurality of mats and performs a column repair operation to replace failed cells among a plurality of memory cells provided in the mats. The column repair circuit includes two or more fuse units configured to perform the column repair operation. Each of the fuse units includes a plurality of fuses, and is configured in such a manner that m mats correspond to one fuse or n mats correspond to one fuse, where m and n are natural numbers equal to or more than 1 and different from each other.

Abstract: A nonvolatile memory device includes a memory cell array including a main cell area and a retention flag cell area, a retention check unit configured to compare a read result for retention flag cells included in the retention flag cell area to a reference value, and determine a retention state of the retention flag cells according to a comparison result, and a control logic configured to provide a retention check result based on the retention state to the external device in response to a retention check request provided from an external device.

Abstract: According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp FET connected between a first data bus and a second data bus, a first precharge FET connected between the first data bus and first potential, a second precharge FET connected between the second data bus and the first potential, a first storage area connected to the first data bus, and a second storage area connected to the second data bus. The control circuit is configured to generate a precharge state in which the first data bus is precharged to the first potential and the second data bus is precharged to a second potential lower than the first potential, when the data is transferred from the second storage area to the first storage area.

Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

Abstract: In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.

Abstract: A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element.

Abstract: To provide a semiconductor device including a plurality of circuit blocks each of which is capable of performing power gating by setting off periods appropriate to temperatures of the respective circuit blocks. Specifically, the semiconductor device includes an arithmetic circuit, a memory circuit configured to hold data obtained by the arithmetic circuit, a power supply control switch configured to control supply of the power supply voltage to the arithmetic circuit, a temperature detection circuit configured to detect the temperature of the memory circuit and to estimate overhead from the temperature, and a controller configured to set a period during which supply of the power supply voltage is stopped in the case where a power consumption of the arithmetic circuit during the period is larger than the overhead period and to control the power supply control switch.

Abstract: A first circuit is coupled to a second circuit, which is coupled to a third circuit. A high voltage value of a first input signal and of a first output signal of the first circuit are equal, and are less than a high voltage value of a second output signal of the second circuit. A low voltage value of the first input signal is higher than a low voltage value of the first output signal. A high voltage value of the second output signal and of a third output signal of the third circuit are equal. The low voltage value of the first output signal, the second output signal, and the third output signal are equal.

Abstract: Depth and tilt control systems for geophysical sensor streamers and methods of use are discussed. Such systems may include a plurality of tilt sensors disposed at spaced apart locations along the geophysical sensor streamer, each tilt sensor having a first tilt sensing element arranged to measure tilt of the geophysical sensor streamer proximate the associated spaced apart location, a plurality of LFD control devices, each disposed proximate one of the tilt sensors along the geophysical sensor streamer, and a plurality of microcontrollers, each microcontroller in signal communication with at least one of the LFD control devices and its associated tilt sensor, wherein each microcontroller is capable of utilizing the tilt measured by the associated tilt sensor to selectively operate the associated LFD control device to cause the geophysical sensor streamer to align with a selected depth profile.

Abstract: A seismic streamer includes a jacket covering an exterior of the streamer. At least one strength member extends the length of the jacket. The strength member is formed as a substantially flat belt having a width to thickness ratio of at least 10. At least one sensor holder is coupled to the at least one strength member. The at least one sensor holder includes at least one arcuate opening for receiving the at least one strength member. The at least one arcuate opening is laterally displaced from a center of the at least one sensor holder such that when the at least one strength member is disposed therein the at least one strength member is substantially tube shaped and substantially coaxial with the jacket.

Abstract: There is provided herein a system and method of seismic exploration that produces improved locations and timings for ocean bottom seismometers. The instant method utilizes linearized inversion in conjunction with a conventionally accurate clock to provide both time and positioning for each OBS unit with high accuracy as compared with the prior art approach. Inversion is one mathematical tool that effectively performs the requisite triangulation. Furthermore, the clock drift can be accounted for in the inversion scheme. The inversion not only determines the OBS position and shot timing errors, but also estimates the accuracy of the position and timing determination.

Abstract: The various embodiments of the present invention provide a method for removing a Scholte waves and similar ground roll type waves from a seismic sea bottom data in a shallow water. The method comprises acquiring seismic sea bottom data in a shallow waters, applying a time-frequency-wave number (t-f-k) transform on the acquired seismic sea bottom data, identifying a time-frequency relationship of a surface wave based on a specific wave number, identifying a frequency-wave number relationship of a surface wave based on a specific time, designing a time varying frequency-wave number filter in the time-frequency-wave number domain to separate the surface wave, applying a time varying frequency-wave number filtering process to remove an undesired energy and inversing a filtered record by applying an inverse S-Transform operation and an inverse Fourier Transform operation.

Abstract: Techniques for estimating velocity ahead of a drill bit include generating seismic waves at a surface from at least two different source positions in the vicinity of a borehole, receiving seismic waves reflected from a reflector ahead of the drill bit at one or more locations in the borehole, determining travel times of the seismic waves received at the one or more locations in the borehole, and inverting the travel times to determine a velocity of a formation ahead of the drill bit. One embodiment includes transforming the velocity into pore pressure of the formation.

Abstract: A device for conducting ultrasonic inspections comprises a base. In addition, the device comprises a probe housing pivotally coupled to the base with a suspension system. Further, the device comprises an ultrasonic probe disposed within the probe housing and configured to transmit ultrasonic signals. The suspension system is configured to permit the probe housing to pivot relative to the base to transmit ultrasonic signals in a plurality of directions.

Abstract: There is provided a method and associated apparatus for measurement. Specifically, a method for determining a distance travelled by a signal in a medium, or the time of flight of a signal travelled. The method comprises considering an unambiguous range wherein the unambiguous range greater than a distance to be travelled by a signal. A signal is then transmitted across the distance to be determined, the signal comprising at least two frequency components, the frequency components based on the unambiguous range and the speed of the signal in the medium. The distance travelled (or the time of flight) is determined by using the variance of the received phase characteristics, such as phase angle) of one frequency component of the received signal with the received phase characteristics of another frequency component of the received signal.

Abstract: Systems and method of processing information regarding weapon fire are set forth herein. In one exemplary implementation, a method of processing information regarding weapon fire, such as determining weapon fire location using projectile shockwave and muzzle blast time(s) of arrival data is disclosed.

Abstract: A method and system for ultrasonic locationing using time difference of arrival measurements includes an ultrasonic receiver including three microphones each disposed on a periphery of a housing and a fourth centrally-positioned microphone.

Abstract: Methods and apparatus determining a position of a submersible vehicle within a body of water are provided. A method comprises determining an initial position of the vehicle while the vehicle is at or near a water surface. The method further comprises coupling the vehicle and a base node to a weight and determining a position of the base node once the base node and vehicle have reached the floor of the body of water using acoustic modems of the vehicle and a surface vessel to aid in calculating the position as they descend, and acoustically transferring the at rest position on the seafloor from the vehicle to the node. The method further comprises decoupling the vehicle from the node and weight and determining a position of the vehicle based on the position of the base node and acoustic signals exchanged between acoustic modems of the vehicle and the base node.

Abstract: Methods and apparatus for using Fourier techniques to detect and isolate the fundamental frequency sweep of echolocation calls produced by bats, or of other narrow-band whistles as produced by other kinds of animals such as birds and whales. According to one example, a Fourier transform is applied on blocks of input samples to produce output frames, and a narrowband frequency modulated signal is detected and traced through the output frames. A filter is applied in each frame to attenuate frequencies above or below the narrowband signal, and an inverse Fourier transform is applied to produce an output signal. The resulting signal may then be analyzed with zero crossing techniques to measure the precise instantaneous frequency sweep.

Abstract: A oscillator in a liquid includes an actuator element oscillating in a reciprocating manner, and a sound-producing element attached to the actuator element, whereby the actuator element generates a motion in the sound-producing element for producing a sound. The oscillator is made open, whereby the pressure of liquid acts both on a first surface and on a second surface of the wall of the sound-producing element while the sound source is in the liquid. The material and/or structure of the wall of the sound-producing element is provided to be such that the distance between the first surface and the second surface of the wall varies as sound is produced.

Abstract: Aspects described herein relate to an electromagnetic seismic vibrator (EMSV) architecture that provide wide frequency range operation, ground force application with high fidelity, and low environmental impact. The EMSV architecture can include a base member that can support a force coil and mitigate electrical heating due, at least in part, to spurious currents. The EMSV architecture can include means for restricting movement of a reaction member included in the EMSV architecture relative to the base member. Such means can permit mitigation of damage of the EMSV architecture in scenarios in which control of the EMSV architecture may fail.

Abstract: Mechanism for displaying the day and phase of at least a first celestial body, comprising a gear train for a constant frequency gear drive on an output of a timepiece movement. This mechanism includes a means for the three-dimensional display of the day and phase of said first celestial body represented by a first mobile component, which is driven by the gear train, which includes a phase train and a day train, each in mesh on an output of this same movement. This phase train and/or this day train include at least one uncoupling means between the input and its output thereof.

Abstract: A date indication display device for a timepiece includes a support element having a plurality of display areas on which are arranged the indications of the days of the month. The support element moves behind an aperture arranged in a dial of the timepiece. The indications of the days of the month are divided into a first and a second group, the two groups being two different colors. A date indication of the first group is superposed on a date indication of the second group on each display area. A first optical filter whose transmittance is chosen to transmit the first color and to block the second color, and a second optical filter whose transmittance is chosen to transmit the second color and to block the first color, are alternately positioned behind the aperture.

Abstract: An electronic timepiece can adjust the input terminal and suppress power consumption. An electronic timepiece has: a reception unit 8 that receives a satellite signal containing time information from a positioning information satellite; a power supply unit 4 having a battery that supplies drive power; a remaining capacity detection unit 5 that measures the remaining battery capacity; and a control unit 9 that controls satellite signal reception by the reception unit 8. The control unit 9 includes a timekeeping unit 91 that keeps time, a time adjustment unit 99 that adjusts the time kept by the timekeeping unit 91 based on the satellite signal received by the reception unit 8, and a prohibition period setting unit 93 that sets a prohibition period in which receiving a satellite signal is prohibited based on the remaining battery capacity measured by the remaining capacity detection unit 5.

Abstract: An electronic timepiece has a case of which at least part is made from a conductive material; an annular antenna housed in the case; and a dial disposed inside the antenna. The antenna has an annular dielectric base. The base has a sloped surface that slopes toward the dial and decreases in height to the dial with proximity to the inside. The antenna element is made from a conductive material and is fed by the feed part of the antenna, and is disposed to the sloped surface of the base.

Abstract: A visual indicator display device includes a bracelet, a transparent capillary chamber, and a displacement member. The transparent capillary chamber is matched to an indicia and has a primary length and a width less than the primary length. The displacement member is functionally disposed at one end of the capillary chamber and is responsive to a measureable input for moving a fluid contained therein a defined amount.

Abstract: A device (100) for displaying time information with the aid of an indicator member (1), including a cam (2) the profile of which includes a flank (23); a lever (4) driving the indicator member (1); a follower (3) controlling the lever (4), pressed against the cam (2) by first spring means (6), adapted, during movement of the flank (23) in a first direction of movement of the cam (2), to control movement of the lever (4) intended to drive movement of the indicator member (1), characterized in that the follower (3) controlling the lever (4) is adapted to be moved relative to the lever (4) against the return action of second spring means (5) by an action force (F) exerted by the flank (23) of the cam (2) on the follower (3) during movement of the flank (23) in a second direction of movement of the cam (2).

Abstract: Provided are recording media, recording/reproducing apparatuses, and recording methods for use in long-term data retention. Recording medium information may be copied and stored in a new information zone in a data area. Accordingly, if medium recognition of a lead-in area and/or a lead-out area fails, a recording medium may be recognized using the data recorded in the new information zone.

Abstract: Systems and methods to determine a position of a base with respect to a playback device and evaluating whether the position is proper or improper given an orientation of the playback device are disclosed and described herein. In one aspect, a playback device is provided. The example playback device includes a first fastener located on a first side of the playback device, a processor, and memory having stored thereon instructions executable by the processor to cause the computing device to perform functions. The functions include determining that a base is not coupled to the playback device via the first fastener and, in response to determining that the base is not coupled to the playback device via the first fastener, adjusting a playback setting of the playback device. The functions further include facilitating output of content via the playback device according to the adjusted playback setting.

Abstract: Embodiments of the invention provide an apparatus for driving a voice coil motor actuator providing a driving signal to a coil for controlling a position of a lens barrel in which a magnet is equipped. The apparatus includes a plurality of hall sensors configured to detect the position of the lens barrel in which the magnet is equipped, and a voice coil motor driving integrated circuit configured to provide the driving signal to the coil based on outputs from the plurality of hall sensors and a received target position. The plurality of hall sensors are embedded in the voice coil motor driving integrated circuit along a moving direction of the magnet.

Abstract: A system and method for adjusting the radial tilt, tangential tilt, or a combination of radial and tangential tilt of an optical detection unit in an optical disc reading system can include applying different weighting factors to different signal components depending on which detection area detects the component, measuring a value of a signal characteristic, such as signal-to-noise ratio, of two signals with different sets of weighting factors, and determining an adjustment factor to the radial tilt as a function of the of the measured signal characteristic values.