Abstract: An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

Abstract: A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective main components. A first gate electrode is electrically connected to one of a second source electrode and a second drain electrode. The other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit. An output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element. The refresh control circuit is configured to control whether the switch element is turned on or off.

Abstract: An integrated circuit (IC) device can include a plurality of memory cells with programmable impedance elements. A circuit can be configured to read a data value stored by an element of a memory cell by application of at least one read voltage pulse and at least one relaxation voltage pulse across the terminals of the element; wherein the read voltage pulse has a same polarity as a voltage used to program the element, the relaxation voltage pulse has a different polarity than the read voltage pulse, and neither the read or relaxation voltage pulses program the element to a particular impedance state.

Abstract: A memory apparatus includes an array of bit cells arranged in rows and columns, multiple pairs of complementary bit lines, multiple power lines, and multiple voltage control circuits. Each column of the array is selectable by a corresponding pair of complementary bit lines. Each power line is coupled to the bit cells in a corresponding column. The voltage control circuits are coupled to respective columns of the array. Each voltage control circuit is configured to set a voltage level of a respective one of the power lines responsive to logic levels of the pair of complementary bit lines corresponding to the respective column.

Abstract: To reduce power consumption, a memory circuit includes a latch unit in which first data and second data are rewritten and read in accordance with a control signal, a first switch unit that controls rewrite and read of the first data stored in the latch unit by being turned on or off in response to the control signal, and a second switch unit that controls rewrite and read of the second data stored in the latch unit by being turned on or off in response to the control signal. The latch unit includes a first inverter and a second inverter. At least one of the first inverter and the second inverter includes a first field-effect transistor, and a second field-effect transistor that has the same conductivity type as the first field-effect transistor and has a gate potential controlled in accordance with the control signal.

Abstract: Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.

Abstract: Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell core. A stressor structure may exert a stress upon at least a portion of the cell core to effect the strain state of the free region. Also disclosed are semiconductor device structures and systems including such memory cells as well as methods for forming such memory cells.

Abstract: In a method of writing data in an MRAM device, a first operation unit is selected in a plurality of memory cells of the MRAM device. First to n-th switching pulses are sequentially applied to the first operation unit to write data in first to n-th groups of memory cells of the first operation unit, respectively. The n-th switching pulse may have a current level lower than that of an (n?1)th switching pulse, where n is an integer larger than at least 1. The n-th switching pulse may have a pulse width narrower than that of an (n?1)th switching pulse, where n is an integer larger than at least 1. The technique can be repeated for a second operation unit. A device and system are disclosed in which different current switching pulses are applied to multiple groups of memory cells within the first and/or second operation units.

Abstract: A device comprising: an assembly consisting of two, respectively upper and lower thin layers each forming a ferromagnetic element and separated by a thin layer forming a non magnetic element, said assembly being made up so that the layers forming the ferromagnetic elements are magnetically coupled through the layer forming a non magnetic element; an electrode, a layer forming a ferroelectric element in which the polarization may be oriented in several directions by applying an electric voltage through said layer, said layer forming a ferroelectric element being positioned between the layer forming a lower ferromagnetic element and the electrode; said device being configured so as to allow control of the magnetic configuration of the layers forming ferromagnetic elements by the direction of the polarization in the layer forming a ferroelectric element.

Abstract: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series.

Abstract: Decoding and decoder circuits in memory devices are disclosed. Array lines are biased or floated as memory device operations are performed in the memory device. In at least one embodiment, a decoder circuit includes complementary devices to bias array lines or float array lines in a memory device while particular memory device operations are performed.

Abstract: A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.

Abstract: A memory device comprises memory elements that are arranged in an array. The array includes rows associated with wordlines and columns associated with bitlines. The memory elements in a row share a wordline and memory elements in a column share a bitline. For each wordline, a wordline driver circuit is associated with the wordline. The memory device comprises a boost circuit that has an output coupled to the wordline driver circuits. The boost circuit is configured to provide a negative voltage to the wordlines during a read operation of the memory device such that unselected wordlines are held at a negative voltage below a ground potential while a selected wordline is held at a supply voltage during the read operation.

Abstract: Methods and apparatuses for reduction of Read Disturb errors in a memory system utilizing modified or extra memory cells.

Abstract: In one embodiment, a control circuit executes a first page writing operation, a first verify operations, a second page writing operation, a second verify operations, a step-up operation. The control circuit executes the first page writing operation which forms an intermediate distribution, and a first read operation which reads data form the intermediate distribution by using a determine voltage higher than a first verify voltage with a first value, and changes a second verify voltage based on the result of the first read operation.

Abstract: A memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes first memory blocks configured to store m-bit data per cell and second memory blocks configured to store n-bit data per cell. The memory controller is configured to control the nonvolatile memory device to close an open word line generated in a second memory block of the second memory blocks when a program operation is performed on the second memory block.

Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

Abstract: A memory repairing method for a rewritable non-volatile memory module and a memory controller and a memory storage apparatus are provided. The method includes monitoring a wear degree of the rewritable non-volatile memory module; determining whether the wear degree of the rewritable non-volatile memory module is larger than a threshold; and heating the rewritable non-volatile memory module such that the temperature of the rewritable non-volatile memory module lies in between 100° C.˜600° C. if the wear degree of the rewritable non-volatile memory module is larger than the threshold. Accordingly, deteriorated memory cells in the rewritable non-volatile memory module can be repaired, thereby preventing data loss.

Abstract: A nonvolatile memory apparatus includes a control unit, a main storage medium with an electrically reloadable nonvolatile memory adapted to be operable even when faulty memory cells exist therein, and a storage region storing registered address values of faulty regions of the main storage medium containing the faulty memory cells. Data which is stored in the electrically reloadable nonvolatile memory is divided into blocks, each block having a plurality of data to be administrated and which is assigned an access address by the control unit. An administrative information region is provided in each block. The control unit carries out access requests of the main storage medium and the administration of faulty regions and the number of occurrences of reloading of respective memory cells of the main storage medium.

Abstract: In an embodiment, each block of a plurality of blocks includes a respective plurality of strings of memory cells, where each of the plurality of strings of a block is coupled to a respective select transistor, and wherein each of the select transistors coupled to the plurality of strings of the block is coupled to a common first select line. The plurality of blocks includes N block sizes, where N may be an integer greater than or equal to three. N?1 blocks of one block size of the N block sizes collectively include a first number of second select lines. A group of blocks consisting of a respective block of each remaining block size of the N block sizes collectively include a second number of second select lines that is equal to the first number of select lines or that is less than the first number of second select lines.

Abstract: Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation for a CS2 situation is used in a subsequent programming operation.

Abstract: Disclosed is a 2-transistor flash memory that includes a memory cell array, a row driver, a read/write circuit, a charge pump generating a high voltage, and control logic configured to transfer the high voltage to the row driver, the read/write circuit, and the memory cell array. If programming, the row driver and the read/write circuit apply voltages such that a control gate of a cell transistor in an unselected memory cell on a different row from a selected memory cell is floated.

Abstract: Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.

Abstract: A method includes storing data in a memory, which includes multiple strings of analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines and a third dimension associated with sections, such that each string is associated with a respective bit line and a respective section and includes multiple memory cells that are connected to the respective word lines. For a group of the strings, respective values of a property of the strings in the group are evaluated. Source-side voltages are calculated for the respective strings in the group, depending on the respective values of the property, and respective source-sides of the strings in the group are biased with the corresponding source-side voltages. A memory operation is performed on the strings in the group while the strings are biased with the respective source-side voltages.

Abstract: According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality of physical blocks. Each of the plurality of physical blocks includes a plurality of string units. Each string unit has a plurality of NAND strings that shares a plurality of word lines connected to a plurality of memory cells, respectively. The memory region is disposed to one of the plurality of physical blocks. Each of the plurality of string units configures a first logical block, and when the first logical block is failed, information of the first failed logical block is stored in a first region of the memory region.

Abstract: A method of operation of a non-volatile memory system includes: providing a control field effect transistor having a source electrode and a body-tie electrode; coupling a resistive storage element to the source electrode; and opening a well switch coupled to the body-tie electrode for increasing a well voltage and resetting the resistive storage element by the source electrode floating on the well voltage.

Abstract: A semiconductor integrated circuit includes a transistor with a source region, a drain region, and a control gate electrode. The integrated circuit additionally includes a controller that selectively applies voltages to the control gate of the transistor. The controller may apply a first voltage that forms a permanent conductive path between the source and drain of the transistor.

Abstract: A method of reading a nonvolatile memory device comprises applying a read voltage to a memory cell array to read selected memory cells, counting a number of the selected memory cells that have a threshold voltage higher or lower than the read voltage, and comparing the counted number with a reference value to determine a number of bits stored in the selected memory cells.

Abstract: A non-volatile memory apparatus includes a memory cell array, a power supply configured to generate an operation voltage according to an operation mode and provide the memory cell array with the operation voltage, and a controller configured to provide the memory cell array with a first verification voltage and a second verification voltage in a program verification operation, detect a high speed program cell by the first verification voltage and the second verification voltage from selected memory cells to be programmed and set the high speed program cell to be in a program inhibition state, and detect a low speed program cell by the second verification voltage.

Abstract: Systems and methods are disclosed for reducing programming interference in solid-state memory using a program suspend command. A data storage system includes a non-volatile memory array including a plurality of non-volatile memory devices and a controller configured to partially program a first cell coupled to a first word line. When a programming criterion associated with the first cell is met, the controller executes a program suspend command after which a second cell coupled to the first word line is at least partially programmed. Programming of the first cell is resumed following said at least partial programming of the second cell.

Abstract: A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred.

Abstract: A method and apparatus to program data into a row of a non-volatile memory array and verify, internally to the non-volatile memory array, that the data was successfully programmed. The verification includes comparing the programmed data from the row of the non-volatile memory array to data in the plurality of high voltage page latches that were used to program the row.

Abstract: A nonvolatile memory device includes a discharge circuit configured to selectively connect circuit nodes to discharge terminals through corresponding discharge paths, and an accumulation device for accumulating electric charge. A driving circuit is for driving the discharge circuit in such a way to connect at least a part of such circuit nodes to the discharge terminals if the value of the external supply voltage falls below a corresponding threshold. A supply circuit is for supplying the driving circuit with an intermediate supply voltage. Each one of the intermediate supply voltages is the corresponding external supply voltage when the value of the external supply voltage is higher than the corresponding threshold, or it is an internal voltage locally generated by the supply circuit by exploiting the electric charge stored by the accumulation device when the value of the external supply voltage is lower than the corresponding threshold.

Abstract: In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.

Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a memory cell and a control unit. The memory cell has a gate electrode including a control gate and a charge storage region on a semiconductor substrate and has a channel region under the gate electrode in the semiconductor substrate. The control unit, during an erase operation where electric charges written in the charge storage region are extracted to the channel region, periodically varies a voltage which is to be applied between the control gate and the channel region.

Abstract: A flash memory device. In one embodiment, the flash memory device includes a flash memory, a diode, a controller, and a capacitor. The flash memory has a voltage source pin. The diode is coupled between a voltage source and the voltage source pin of the flash memory. The controller is coupled to the flash memory via a data bus. The capacitor is coupled between the voltage source pin of the flash memory and a ground, and supplies power to the flash memory to enable the flash memory to complete writing of at least one data page when the level of the voltage source is lowered.

Abstract: A volatile memory includes volatile memory cells in which data write and read operations are performed. The memory cells are arranged in rows and in columns and are distributed in first separate groups of memory cells for each column. The memory includes, for each column, a write bit line dedicated to write operations and connected to all the memory cells of the column and read bit lines dedicated to read operations. Each read bit line is connected to all the memory cells of one of the first groups of memory cells. Each memory cell in the column is connected to a single one of the read bit lines.

Abstract: A buffer control circuit of a semiconductor memory apparatus includes a delay unit configured to determine delay amounts for a command in response to a plurality of command latency signals, delay the command according to a clock, and generate a plurality of delayed signals; and a buffer control signal generation unit configured to receive the plurality of command latency signals and the plurality of delayed signals, and generate a buffer control signal.

Abstract: A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating node, the dynamic latch comprising a storage capacitor, a write transistor configured to write the data of the floating node to the storage capacitor, and a read transistor configured to read the data of the storage capacitor, and the write transistor and the read transistor sharing the floating node.

Abstract: Some embodiments relate to a sense amplifier output buffer configured to buffer an output of a sense amplifier. The sense amplifier output buffer includes a first pull-up element having a source coupled to a first DC supply terminal and having a drain coupled to an output terminal of the sense amplifier output buffer. A first pull-down element is in series with the first pull-up element and has a source coupled to a second DC supply terminal and has a drain coupled to the output terminal. A miller capacitance decoupling circuit is coupled between the drain of the first pull-up element and the drain of the first pull-down element. The miller capacitance decoupling circuit is configured to decouple miller capacitance associated with the drains of the pull-up and pull-down elements from the output terminal. Other embodiments are also disclosed.

Abstract: A semiconductor integrated circuit includes: a latch unit configured to latch data in response to an input control signal; and a latch control unit configured to determine whether or not any one of first and second memory areas is successively accessed, and adjust timing of the input control signal.

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

Abstract: Systems and methods are disclosed for decoding solid-state memory cells. In certain embodiments, a data storage device includes a controller configured to decode a non-volatile memory array by performing a first read of a plurality of code words from the non-volatile memory array using a first reference voltage level and performing a second read of the plurality of code words using a second reference voltage level on a first side of the first reference voltage level. The controller is further configured to generate a soft-decision input value associated with a first code word of the plurality of code words based on the first and second reads and decode the first code word using the soft-decision input value.

Abstract: A method of calibrating a data signal receiver configured to receive a multi-bit data signal and an associated data strobe signal, wherein transitions of the data strobe signal indicate sample points for the multi-bit data signal.

Abstract: A repair control circuit of controlling a repair operation of a semiconductor memory device includes a row matching block and a column matching block. The row matching block stores fail group information indicating one or more fail row groups among a plurality of row groups. The row groups are determined by grouping a plurality of row addresses corresponding to a plurality of wordlines. The row matching block generates a group match signal based on input row address and the fail group information, such that the group match signal indicates the fail row group including the input row address. The column matching block stores fail column addresses of the fail memory cells, and generates a repair control signal based on input column address, the group match signal and the fail column addresses, such that the repair control signal indicates whether the repair operation is executed or not.

Abstract: An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global bit line. The precharge logic may charge the global bit line to a precharge voltage for a non-read operation and a boosted voltage that is greater than a reference voltage for a read operation. The discharge logic may either maintain the global bit line at the boosted voltage for the first logical value or discharge the global bit line to a discharge voltage that is less than the reference voltage for the second logical value. The sense logic may output the first logical value when the global bit line has the boosted voltage or may output the second logical value when the global bit line has the discharge voltage.

Abstract: An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global bit line. The precharge logic may charge the global bit line to a precharge voltage for a non-read operation and a boosted voltage that is greater than a reference voltage for a read operation. The discharge logic may either maintain the global bit line at the boosted voltage for the first logical value or discharge the global bit line to a discharge voltage that is less than the reference voltage for the second logical value. The sense logic may output the first logical value when the global bit line has the boosted voltage or may output the second logical value when the global bit line has the discharge voltage.

Abstract: A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline row has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.

Abstract: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.

Abstract: A clock generating circuit includes a delay line that generates an internal clock signal, a phase-controlling unit that adjusts a phase of the internal clock signal by controlling the delay line, and a mode switching circuit that switches an operation mode of the phase-controlling unit. The phase-controlling unit has a first operation mode in which a phase of the internal clock signal is changed in synchronization with a sampling clock signal and a second operation mode in which the phase of the internal clock signal is fixed. The mode switching circuit shifts the phase-controlling unit to the first operation mode in response to a trigger signal, such as a refresh signal, and, shifts the phase-controlling unit to the second operation mode in a state where the internal clock signal attains a predetermined phase.