Abstract: A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the insulating layer and includes an oxide semiconductor layer; and a control terminal are provided. The control terminal is formed in the same step as a source and a drain of the second field-effect transistor, and a voltage for controlling a threshold voltage of the first field-effect transistor is supplied to the control terminal.

Abstract: A semiconductor package includes a substrate, a chip disposed over a top surface of the substrate, an electromagnetic interference (EMI) shielding layer disposed over the substrate such that the EMI shielding layer surrounds the chip, a ground pad disposed in the substrate to contact a bottom surface of the substrate, and a test pad disposed in the substrate to contact the bottom surface of the substrate and spaced apart from the ground pad. A method of testing the semiconductor package is performed using a loop circuit to which a current is applied, the loop circuit being formed by electrically coupling the ground pad, the EMI shielding layer, and the test pad.

Abstract: In a liquid crystal display device it is desirable to test in the state of TFT substrates, without reducing the number of TFT substrates to be obtained from one mother TFT substrate, and without increasing the overall size of the TFT substrates. Test terminals are formed on the outside of terminals for driving the liquid crystal display device. The test terminals of the specific TFT substrate are formed in another TFT substrate just below the specific TFT substrate. The area in which the test lines are formed is a space in which a sealing material is formed, between the display area and an end of the lower TFT substrate. Thus, the size of the TFT substrates is not actually increased. A test line area is not separately formed and not discarded, so that the number of TFT substrates to be obtained from one mother TFT substrate is not reduced.

Abstract: Non-crystalline inorganic light emitting diode. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a non-crystalline inorganic light emission layer and first and second semiconducting non-crystalline inorganic charge transport layers surrounding the light emission layer. The light emission layer may be amorphous. The charge transport layers may be configured to inject one type of charge carrier and block the other type of charge carrier.

Abstract: An array substrate for LCD devices and a method of manufacturing the same are provided. By using a structure where an empty space is secured in a data line area as in a DRD structure in which the number of data lines is reduced by half, a capacitance is sufficiently secured by forming a sub storage capacitor in the data line area of the empty space, and thus, an area of a main storage capacitor can be reduced. Accordingly, the cost can be reduced, and moreover, an aperture ratio can be enhanced.

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

Abstract: In a display apparatus including a switching transistor, a correction voltage for eliminating an effect of a variation in a characteristic of a driving transistor is stored in a storage capacitor. The switching transistor is disposed between one current terminal of the driving transistor and a light emitting element. The switching transistor turns off during the non-light emission period thereby to electrically disconnect the light emitting element from the one current terminal of the driving transistor thereby preventing a leakage current from flowing through the light emitting element during the period in which the correction unit operates, and thus preventing the correction voltage from having an error due to the leakage current.

Abstract: An active device array substrate includes a substrate, first signal lines, second signal lines, pixel units, selection units, an insulating layer, and a driving unit. The second signal lines and the selection lines are electrically connected with the driving unit. The insulating layer is disposed among he first signal lines, the second signal lines and the selection lines and has contact holes. The contact holes are disposed corresponding to the first signal lines, and a portion of the selection lines are electrically connected with the first signal lines via the contact holes. The selection line corresponding to the contact hole the farthest from the driving unit and the closest to a reference axis of the substrate and the selection line corresponding to the contact hole the closest to the driving unit and the reference axis respectively receive a start signal and a terminal signal provided by the driving unit.

Abstract: The present invention provides a pixel unit including a thin film transistor and a pixel electrode, the thin film transistor includes a gate, a source and a drain, and the pixel electrode is electrically connected to the drain through a via hole. An upper end surface of the via hole is connected to the pixel electrode, and a lower end surface of the via hole is connected to the drain. The via hole is a step-shaped hole, and an area of the upper end surface of the via hole is larger than that of the lower end surface of the via hole. The present invention also provides a method of fabricating the pixel unit, an array substrate including the pixel unit, and a display device including the array substrate.

Abstract: The invention relates to an array substrate for a display device and to a method for manufacturing an array substrate comprising a thin-film transistor (“TFT”). An array substrate according to an embodiment of the invention comprises a source electrode, a gate electrode and a drain electrode, wherein the gate electrode is located on a first metal layer, the source electrode and the drain electrode are located on a second metal layer, and in the case that dislocation occurs between the first metal layer and the second metal layer, the area of the overlapping region between the source electrode and the gate electrode keeps constant.

Abstract: It is an object of the present invention to form a pixel electrode and a metal film using one resist mask in manufacturing a stacked structure by forming the metal film over the pixel electrode. A conductive film to be a pixel electrode and a metal film are stacked. A resist pattern having a thick region and a region thinner than the thick region is formed over the metal film using an exposure mask having a semi light-transmitting portion. The pixel electrode, and the metal film formed over part of the pixel electrode to be in contact therewith are formed using the resist pattern. Accordingly, a pixel electrode and a metal film can be formed using one resist mask.

Abstract: To provide a plural-viewpoint display device having an image separating optical element such as a lenticular lens or a parallax barrier, which is capable of arranging thin film transistors and wirings while achieving substantially trapezoid apertures and high numerical aperture, and to provide a driving method thereof, a terminal device, and a display panel. A neighboring pixel pair arranged with a gate line interposed therebetween is connected to the gate line placed between the pixels, each of the pixels configuring the neighboring pixel pair is connected to the data line different from each other, and each of the neighboring pixel pairs neighboring to each other in an extending direction of the gate lines is connected to the gate line different from each other.

Abstract: A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.

Abstract: A method for fabricating a lateral gallium nitride (GaN) field-effect transistor includes forming a first and second GaN layer coupled to a substrate, removing a first portion of the second GaN layer to expose a portion of the first GaN layer, and forming a third GaN layer coupled to the second GaN layer and the exposed portion of the first GaN layer. The method also includes removing a portion of the third GaN layer to expose a portion of the second GaN layer, forming a source structure coupled to the third GaN layer. A first portion of the second GaN layer is disposed between the source structure and the second GaN layer. A drain structure is formed that is coupled to the third GaN layer or alternatively to the substrate. The method also includes forming a gate structure coupled to the third GaN layer such that a second portion of the third GaN layer is disposed between the gate structure and the second GaN layer.

Abstract: A semiconductor device includes: a substrate; nitride semiconductor layers disposed over the substrate; a source electrode and a drain electrode disposed over the nitride semiconductor layers; a first insulating layer disposed over the nitride semiconductor layers, the source electrode and the drain electrode; a second insulating layer disposed over the first insulating layer; a first opening disposed in the second insulating layer and the first insulating layer and between the source electrode and the drain electrode, a portion of the nitride semiconductor layer being exposed in the first opening; a second opening disposed in the second insulating layer and between the source electrode and the drain electrode, a portion of the first insulating layer being exposed in the second opening; and a gate electrode disposed over the second insulating layer to bury the first opening and at least a portion of the second opening.

Abstract: A semiconductor device includes: a first nitride semiconductor layer formed over a substrate; a second nitride semiconductor layer formed over the first nitride semiconductor layer; element isolation regions formed in a part of the second nitride semiconductor layer and the first nitride semiconductor layer; a gate electrode, source electrodes, and a drain electrode formed over the second semiconductor layer and the element isolation regions; and a drain field plate formed in such a manner as to project from upper portions of side surfaces of the drain electrode.

Abstract: A semiconductor device is provided, which includes a barrier layer 14 formed on a substrate 10 and made of InxAlyGa1-x-yN, a channel layer 16 formed on the barrier layer and made of GaN or InGaN, an electron supplying layer 18 formed on the channel layer and made of AlGaN, InAlN, or InAlGaN, and a gate electrode and ohmic electrodes 24 and 26 formed on the electron supplying layer. Relations between x and y for the barrier layer of x>0, y>0, x+y?1, and 0.533x<y<4.20x are satisfied.

Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer and a second device layer formed on a first device layer. The first device layer is formed on a substrate and includes a first channel structure configured to conduct a first current, the first channel structure including a first material capable of sustaining a first processing temperature. The second device layer includes a second channel structure configured to conduct a second current, the second channel structure including a second material capable of sustaining a second processing temperature, the second processing temperature being equal to or lower than the first processing temperature.

Abstract: A wafer-level chip scale package is disclosed, including a chip including a substrate and a GaN transistor disposed on the substrate. The GaN transistor includes a first electrode, a dielectric layer disposed on the chip, and a redistribution trace disposed on the first dielectric layer and electrically connected with the first electrode, wherein the redistribution trace has a linear side and a curved side on opposite sides along its longitudinal direction.

Abstract: The present invention provides a semiconductor device that can achieve both low on-resistance and high withstand voltage, while reducing the device size, improving the manufacturing yield, and reducing the cost. The semiconductor device 1 includes a substrate 5, an epitaxial layer 6 formed on the substrate 5 and formed with a gate trench 11, a gate insulating film 17 formed on the side surface 14 and the bottom surface 15 of the gate trench 11, a gate electrode 20 embedded in the gate trench 11 and opposed to the epitaxial layer 6 with the gate insulating film 17 therebetween, and a source layer 25, a channel layer 26, and a drift layer 27 formed in this order from a first surface to a second surface of the epitaxial layer 6, in which the on-resistance Ron represented by a variable “y” and the withstand voltage Vb represented by a variable “x” functionally satisfy the following relational expression (1): y?9×10?7x2?0.0004x+0.7001??(1).

Abstract: A silicon carbide epitaxial layer formed by a low concentration wide band gap semiconductor of a first conductivity type is formed on the surface of a silicon carbide substrate formed by a high concentration wide band gap semiconductor of the first conductivity type. A Schottky electrode is formed on the silicon carbide epitaxial layer. The interface between the Schottky electrode and the silicon carbide epitaxial layer is used as a Schottky interface. Plural impurity regions of a second conductivity type are disposed at predetermined intervals in a lateral direction, in the silicon carbide epitaxial layer, at a position in the lower portion of the Schottky electrode in the depth direction. Because of the shape of the impurity regions, any leak current can be suppressed without raising the ON-resistance.

Abstract: In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench.

Abstract: A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm. A method for manufacturing a semiconductor device according to the present invention includes: a step of forming a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, on the surface of a first conductive-type SiC semiconductor layer; and a step for heat treating the Schottky metal whilst the surface thereof is exposed, and structuring the junction of the SiC semiconductor layer to the Schottky metal to be planar, or to have recesses and protrusions of equal to or less than 5 nm.

Abstract: Non-destructive pretreatment methods are generally provided for a surface of a SiC substrate with substantially no degradation of surface morphology thereon. In one particular embodiment, a molten mixture (e.g., including KOH and a buffering agent) is applied directly onto the surface of the SiC substrate to form a treated surface thereon. An epitaxial film (e.g., SiC) can then be grown on the treated surface to achieve very high (e.g., up to and including 100%) BPD to TED conversion rate close to the epilayer/substrate interface.

Abstract: Methods for packaging a functional chip, methods for annealing a functional chip, and chip assemblies. A functional chip and an annealing chip are located inside a package. The functional chip includes an integrated circuit. The annealing chip includes an annealing element source comprised of an annealing element or a light source configured to emit electromagnetic radiation. The integrated circuit of the functional chip receives the annealing element, electromagnetic radiation, or both from the annealing chip in order to perform an annealing procedure that extends the useful lifetime of the packaged integrated circuit.

Abstract: Techniques are disclosed for integrating the LED lead frame into the LED circuit fabrication process. The LED packages within the lead frame may be spaced according to the final spacing of the LED packages on the finished circuit board, such that multiple LED packages may be attached to a circuit board at a time by applying the lead frame to circuit board and then removing portions of the lead frame, leaving the LED packages attached to the board. The LED packages may be attached using solder or conductive epoxy, in some embodiments. Alternatively, part of the lead frame may include conductive wires forming one or more strings of LED packages. An entire string of LED packages may then be removed from the lead frame in a single motion and placement may be performed for a string of LED packages all at once rather than for individual LED packages.

Abstract: A light emitting diode structure includes a patterned substrate, a light emitting diode die, and a first reflector. The light emitting diode die is disposed on the patterned substrate and emitting a light in wavelength ?. The first reflector is formed over the patterned substrate, covering the patterned substrate which is not covered by the light emitting diode die, to reflect the light emitted from the light emitting diode die. Also, plurality of light emitting diode die can be connected in series to form a high voltage light emitting diode structure.

Abstract: An optoelectronic semiconductor chip and a method for producing an optoelectronic semiconductor chip are disclosed. In an embodiment an optoelectronic semiconductor chip includes a support having a support top side, a semiconductor layer sequence having an active layer for generating electromagnetic radiation, wherein the active layer is located between an n-type n-layer and a p-type p-layer of the semiconductor layer sequence, wherein the semiconductor layer sequence, as seen in a plan view of the support top side, is patterned into emitter regions arranged next to one another and electrical conductor tracks located on a side of the semiconductor layer sequence facing away from the support, where the electrical conductor tracks include contact surfaces. The chip further includes an n-contact point and a p-contact point for electrically contacting the semiconductor chip, wherein the emitter regions are electrically connected in series via the at least two conductor tracks.

Abstract: In a first aspect of the present inventive subject matter, a lighting device includes a light-emitting element that includes a first electrode and a second electrode on a lower surface of the light-emitting element; a phosphor layer directly covering a peripheral side surface of the light-emitting element; and a light-reflecting layer that is in contact with an upper surface of the light-emitting element and in contact with an upper surface of the phosphor layer directly covering the peripheral side surface of the light-emitting element.

Abstract: A display device including a pixel array having a plurality of pixels arranged in a matrix form, each of the pixels including a sampling transistor configured to sample a data potential from a video signal line which is insulated from and intersects a control line in response to the change in potential of the control line, and a light-emitting element configured to emit light at the brightness commensurate with the magnitude of the post-sampling data potential.

Abstract: A light emitting diode (LED) package includes a package body having a recessed portion, a first lead electrode and a second lead electrode spaced apart from each other, and a light emitting device arranged in the recessed portion and electrically connected to the first lead electrode and the second lead electrode. The LED package is configured to be driven by an alternating current (AC) and by a voltage higher than that for driving one light emitting diode.

Abstract: The present invention relates to an optical device and a method for manufacturing the same. The technical object of the invention is to realize a surface emitting body which allows heat generated from a light-emitting chip to be easily dissipated, eliminates the need for an additional wiring layer, and allows a singular light emitting chips or a plurality of light emitting chips to be arranged in series, in parallel, or in series-parallel. The present invention discloses an optical device comprising: a substrate; a plurality of light emitting chips disposed on the substrate; a plurality of conductive wires which electrically connect the substrate with the light emitting chips such that the plurality of light emitting chips are connected to each other in series, in parallel or in series-parallel; and a protective layer which covers the plurality of light emitting chips and the plurality of conductive wires on the substrate.

Abstract: A light emitter and methods of constructing the same is disclosed. The light emitter is disclosed as including a jumper chip and one or more light sources, such as Light Emitting Diodes (LEDs). The light sources are connected to the jumper chip via conductive traces manufactured with semiconductor processing techniques. The jumper chip is disclosed as having a plurality of isolated conductive vias, thereby allowing the jumper chip to present multiple different bonding areas that are electrically isolated from one another.

Abstract: Provided is a compact and high-luminance semiconductor light-emitting device which has excellent color rendering characteristics and which enables arbitrary selection of emission color depending on the use of the device. The semiconductor light-emitting device includes a light-emitting element assembly configured by a plurality of fluorescent semiconductor light-emitting elements each of which has external connection electrodes respectively connected to an n-type semiconductor layer and a p-type semiconductor layer, wherein at least an outer surface other than the external connection electrodes of each of the fluorescent semiconductor light-emitting elements is coated with a resin containing a fluorescent material. The light-emitting element assembly is configured such that the external connection electrodes of the fluorescent semiconductor light-emitting elements are directly connected in series using solder.

Abstract: An LED (Light Emitting Diode) module includes an LED unit having one or more LED chips and a case. The case includes: a body including a base plate made of ceramic, the base plate having a main surface and a bottom surface opposite to the main surface; a through conductor penetrating through the base plate; and one or more pads formed on the main surface and making conductive connection with the through conductor, the pads mounting thereon the LED unit. The through conductor includes a main surface exposed portion exposed to the main surface and overlapping the LED unit when viewed from top, a bottom surface reaching portion connected to the main surface exposed portion and reaching the bottom surface. The pads cover at least a portion of the main surface exposed portion.

Abstract: Techniques are disclosed for making a flexible laminated circuit board using a metal conductor onto which a SMD may be attached. Conductive metal strips may be laminated to form a flexible substrate and the metal strips may then be perforated for the placement of LED package leads. The LED packages may be attached to the conductive strips using solder or a conductive epoxy and the upper laminate layer may include perforations exposing portions of the metal strips for the attachment of the LED packages. Alternatively, strings of LED packages may be fabricated by attaching LED packages to conductive strips and these strings may be laminated between flexible sheets to form a laminated LED circuit. Plastic housings may aid in attaching the LED packages to the conductive strips. The plastic housings and/or the laminate sheets may be made of a reflective material.

Abstract: To connect multiple LED devices, each LED device is placed in a holder. A first wire is connected to a first wire connection point on the holder and a second wire is connected to a second wire connection point on the holder. The first wire is also connected to a first wire connection point on a circuit board The second wire is also connected to a second wire connection point on the circuit board. A connector may be used to connect the wires to the wire connection points on the circuit board. The circuit board includes traces to connect the LED devices to each other or to other components.

Abstract: Tunable p-i-n diodes comprising Ge heterojunction structures are provided. Also provided are methods for making and using the tunable p-i-n diodes. Tunability is provided by adjusting the tensile strain in the p-i-n heterojunction structure, which enables the diodes to emit radiation over a range of wavelengths.

Abstract: A light-emitting device package including a substrate, a packaging lens, a light-emitting unit and a plurality of optical microstructures is provided. The packaging lens and the light-emitting unit are disposed on the substrate and the packaging lens wraps the light-emitting unit. The packaging lens has a bottom surface and includes at least one platform. The at least one platform has a side surface and a platform surface. The bottom surface of the packaging lens is connected with the platform surface through the side surface. The platform surface faces away from the light-emitting unit and the bottom surface. The optical microstructures are located on the platform surface of the at least one platform.

Abstract: An electrode structure includes a first diffusion barrier layer, an aluminum reflective layer formed over the first diffusion barrier layer. The aluminum reflective layer has a thickness from about 500 angstroms (?) to less than 2,000 ?, a second diffusion barrier layer formed over the aluminum reflective layer, and an electrode layer overlying the second diffusion barrier layer. The electrode structure is applicable in a light emitting diode device.

Abstract: The invention provides a light-emitting diode package. The light-emitting diode package includes a lead frame having a first lead and a second lead separated from each other by a space. A transparent plastic housing surrounds and encapsulates the lead frame to form a cup-shaped body having a recessed accommodating space. A bottom of the space is defined as a function area. The function area comprises an exposed surface of the first lead and an exposed surface of the second lead. A top of the space is defined as an opening for light emission. A light-emitting diode chip is mounted on the first lead in the function area, electrically connected to the second lead. A white reflective material is disposed on an isolation area in the function area, covering the first and second leads adjacent to the space. An encapsulation material fills the recessed accommodating space.

Abstract: A method for manufacturing a light-emitting diode is provided. First, a substrate having a front or top surface and a rear or bottom surface is provided. An uneven pattern is formed on the rear or bottom surface. A light-emitting semiconductor layer is formed by stacking a first semiconductor layer, an active layer, and a second semiconductor layer on the front or top surface of the substrate having the uneven pattern. The light-emitting semiconductor layer and the substrate are separated into a plurality of light-emitting cells.

Abstract: Embodiments of the invention include a light emitting device (LED 10), a first wavelength converting material (13, in a matrix 14 to form a layer 12), and a second wavelength converting material (forming layer 16). The first wavelength converting material includes a nanostructured wavelength converting material. The nanostructured wavelength converting material includes particles having at least one dimension that is no more than 100 nm in length. The first wavelength converting material (13) is spaced apart from the light emitting device (10).

Abstract: The light-emitting device, according to one embodiment, comprises: a light-emitting structure including a first conductive semiconductor layer, an active layer formed beneath the first conductive semiconductor layer, and a second conductive semiconductor layer formed beneath the active layer; a reflective electrode arranged beneath the light-emitting structure and having a first region beneath the second conductive semiconductor layer and a second region extending from the first region and penetrating through the second conductive semiconductor layer and the active layer; and an electrode electrically connected to the first conductive semiconductor layer.

Abstract: Provided is a light emitting device having a phosphor layer on a surface of a semiconductor light emitting element and achieving an even light distribution color, and a method of manufacturing the same. A method of manufacturing a light emitting device includes arranging a plurality of semiconductor light emitting elements spaced apart from each other on an expandable sheet, spraying a slurry containing a solvent, a thermosetting resin, and phosphor particles, onto an entire surface of the sheet having the arranged semiconductor light emitting elements to form a resin layer, pre-curing the resin layer, disuniting the resin layer formed on the surface of the semiconductor light emitting element from the resin layer formed on the sheet by expanding the sheet, and main curing the resin layer, which steps are performed in this order.

Abstract: The present application discloses a light-emitting device comprises a semiconductor light-emitting element, a transparent element covering the semiconductor light-emitting element, an insulating layer which connects to the transparent element, an intermediate layer which connects to the insulating layer; and a conductive adhesive material connecting to the intermediate layer.

Abstract: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device comprises a light emitting structure comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; a reflective layer under the light emitting structure; a first electrode layer on the first conductive semiconductor layer; a metal layer under the reflective layer; and a conductive support member under the metal layer. The reflective layer has a thickness of 650 nm to 1550 nm. A top surface of the first conductive semiconductor layer includes a flat first region adjacent to an edge and a rough second region adjacent to the first region. An edge region of a top portion of the conductive support member has a protrusion, and the edge region of the top portion of the conductive support member is not overlapped with the light emitting structure in a vertical direction.

Abstract: An emitter package comprising a light emitting diode (LED) mounted to the surface of a submount with the surface having a first meniscus forming feature around the LED. A matrix encapsulant is included on the surface and covering the LED. The outer edge of the matrix encapsulant adjacent the surface is defined by the meniscus forming feature and the encapsulant forms a substantially dome-shaped covering over said LED. A method for manufacturing an LED package by providing a body with a surface having a first meniscus holding feature. An LED is mounted to the surface with the meniscus holding feature around the LED. A liquid matrix encapsulant is introduced over the LED and the surface, the first meniscus holding feature holding the liquid matrix encapsulant in a dome-shape over the LED. The matrix encapsulant is then cured.

Abstract: A semiconductor light emitting device includes a semiconductor lamination including a p-type semiconductor layer, an active semiconductor layer, and an n-type semiconductor layer; opposing electrode structure including a first electrode structure formed above the p-type semiconductor layer, and a second electrode structure formed above the n-type semiconductor layer; and brightness grade producing structure including a surface layer of at least one of the p-type semiconductor layer and the n-type semiconductor layer and producing brightness grade gradually changing from one edge to opposite edge of light output plane.