Abstract: A three dimensional integrated circuit capacitor that includes a first conductive layer, a second conductive layer above the first conductive layer and a semiconductor layer above the second conductive layer. The semiconductor layer has an inter layer via (ILV) through the semiconductor layer. A third conductive layer is above the semiconductor layer and a fourth conductive layer is above the third conductive layer. A first conductive plate has fingers on at least two of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer. A second conductive plate has fingers on at least two of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer. An insulating layer is between the first conductive plate and the second conductive plate.

Abstract: A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.

Abstract: The invention provides a method for fabricating a transistor and a transistor, wherein the method for fabricating a transistor includes: growing a second oxide layer on the surface of a substrate on which a first oxide layer and a first base region are formed, wherein the second oxide layer is formed above the first base region; forming an emitter region in a first preset area on the second oxide layer; forming a contact hole in a second preset area on the second oxide layer, wherein the second preset area does not overlap with the first preset area; injecting doping elements into the surface of the first base region in the area of the contact hole; and thermally processing the substrate to activate the doping elements to form a second base region.

Abstract: Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.

Abstract: A method of forming a carbon-containing thin film and a method of manufacturing a semiconductor device using the method of forming the carbon-containing thin film are described. The method of forming a carbon-containing thin film includes the steps of introducing a substrate into a chamber, injecting hydrocarbon gas and at least nitrogen gas simultaneously into the chamber, and depositing a carbon-containing thin film including carbon and nitrogen on the substrate, thereby forming a carbon-containing thin film having high selectivity and uniform thickness.

Abstract: A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.

Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.

Abstract: A semiconductor package includes: a package base substrate; at least one first semiconductor chip disposed on the package base substrate; a first molding member disposed at a same level as the at least one first semiconductor chip and that does not cover an upper surface of the at least one first semiconductor chip; at least one second semiconductor chip stacked on the at least one first semiconductor chip so as to extend over the at least one first semiconductor chip and the first molding member, wherein the at least one first semiconductor chip and at least part of the first molding member are disposed between the package base substrate and the at least one second semiconductor chip; and a second molding member disposed at a same level as the at least one second semiconductor chip.

Abstract: Disclosed herein is a semiconductor device that includes a plurality of segment regions arranged with a first distance, each of segment regions including a plurality of first grooves arranged with a second distance that is smaller than the first distance, and a second groove enclosing the plurality of the segment regions with a third distance that is larger than the second distance.

Abstract: A semiconductor device configured to provide increased current gain comprises a semiconductor substrate having a first conductivity type. The device also comprises a first semiconductor region having a second conductivity type. The device further comprises a second semiconductor region in the first semiconductor region to having the first conductivity type. The device additionally comprises a third semiconductor region in the first semiconductor region having the second conductivity type. The device also comprises a fourth semiconductor region outside the first semiconductor region having the first conductivity type. The device further comprises a fifth semiconductor region outside the first semiconductor region adjacent the fourth semiconductor region and having the second conductivity type. The device additionally comprises a first electrode electrically connected to the third semiconductor region.

Abstract: A module IC package structure includes a substrate unit, an electronic unit, a package unit and a shielding unit. The substrate unit including a circuit substrate, a grounding layer disposed inside the circuit substrate, and an outer conductive structure disposed on the outer surrounding peripheral surface of the circuit substrate. The outer conductive structure includes a plurality of outer conductive layers. The grounding layer is exposed from the circuit substrate for directly contacting the outer conductive layers. The electronic unit includes a plurality of electronic components disposed on the circuit substrate. The package unit includes a package gel body disposed on the circuit substrate to enclose the electronic components. The shielding unit includes a metal shielding layer enclosing the package gel body and directly contacting the outer conductive structure. Whereby, the grounding layer is electrically connected to the metal shielding layer through the outer conductive structure directly.

Abstract: A module IC package structure includes a substrate unit, an electronic unit, a package unit and a shielding unit. The substrate unit includes a circuit substrate and a grounding layer disposed inside the circuit substrate. The grounding layer is exposed from the outer surrounding peripheral surface of the circuit substrate. The electronic unit includes a plurality of electronic components disposed on the circuit substrate. The electronic components are electrically connected to the grounding layer through the circuit substrate. The package unit includes a package gel body disposed on the circuit substrate to enclose the electronic components. The shielding unit includes a metal shielding layer disposed on the outer surface of the package gel body and the surrounding peripheral surface of the circuit substrate. The metal shielding layer directly contacts the grounding layer, thus the electronic components are electrically connected to the metal shielding layer through the grounding layer.

Abstract: Packaged microelectronic devices and methods of manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a stand-off layer over a plurality of microelectronic dies on a semiconductor workpiece, and removing selected portions of the stand-off layer to form a plurality of stand-offs with the individual stand-offs positioned on a backside of a corresponding die. The method further includes cutting the semiconductor workpiece to singulate the dies, and attaching the stand-off on a first singulated die to a second die.

Abstract: In one implementation, a semiconductor package includes a patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the patterned conductive carrier. The semiconductor package further includes a heat spreading conductive plate situated over a control source of the control FET and over a sync drain of the sync FET so as to couple the control source and the sync drain to a switch node segment of the patterned conductive carrier.

Abstract: A lead frame strip includes a plurality of connected unit lead frames, each unit lead frame having a die paddle and a plurality of leads connected to a periphery of the unit lead frame. A semiconductor die is attached to the die paddles. A molding compound covers the unit lead frames, including the semiconductor dies. Prior to testing or other processing of the lead frame strip, a gap is etched into a region of the leads which are shared by adjacent ones of the unit lead frames. The gap extends at least mostly through the shared leads. A partial cut is made in the molding compound around the periphery of the unit lead frames prior to the subsequent processing, including below the gap in the shared leads, to electrically isolate the leads of the unit lead frames.

Abstract: Embodiments described herein relate to a packaged component including a lead frame and a non-conductive plug disposed between two or more adjacent sections of the lead frame. The plug is composed of a non-conductive material and is adhered to the two or more adjacent sections of the lead frame. The plug functions to impede the flow of solder along edges of the two or more adjacent sections during second level solder reflow events that occur after encapsulation of the packaged component. The plug includes a main portion disposed within a space between the two or more adjacent sections, and one or more overlap portions extending from the main portion. The one or more overlap portions are disposed on an internal surface of at least one of the two or more adjacent sections. At least one component is mounted on one of the plurality of sections of the lead frame.

Abstract: The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging at a vacuum level of about 10 mTorr or less such as close to 1 mTorr (i.e. MEMS vacuum packaging).

Abstract: Example packaging of microelectronics and example methods of manufacturing the same are provided herein. The packaging can enable and/or improve the use of the microelectronics in a downhole, high temperature and/or high pressure setting. The microelectronics packaging can include double-sided active components, heat sinks, and/or three-dimensional stacking of dies.

Abstract: Provided are semiconductor packages and methods of fabricating the same. The method may include, stacking a lower semiconductor chip on a lower package substrate, forming a lower molding layer on the lower package substrate, forming a connecting through-hole and an element through-hole by performing a laser drilling process on the lower molding layer, and stacking an upper package substrate having a bottom surface to which a passive element is bonded on the lower package substrate to insert the passive element into the element through-hole.

Abstract: A semiconductor module with radiation fins includes a semiconductor module including a metal base. The metal base has an outer circumferential portion surrounding the same and a top panel portion surrounded by the outer circumferential portion. One side of the top panel portion is disposed with a plurality of semiconductor chips through a plurality of corresponding insulating substrates and the other side of the top panel portion is disposed with radiation fins. The plurality of semiconductor chips is connected to electric wiring to electrically connect to the outside of the semiconductor module. A thickness of the top panel portion is less than a thickness of the outer circumferential portion. The top panel portion between the insulating substrates includes a groove having an opening narrower than a bottom portion. The plurality of semiconductor chips is sealed together with the groove by resin.

Abstract: A semiconductor element housing package includes a rectangular ceramic package having a recess section on an upper surface thereof or a penetration section from the upper surface to a lower surface thereof, and a heat radiation plate attached to the lower surface of the ceramic package, extending from one side toward the other side of the lower surface up to a region in which the heat radiation plate overlays the recess section or the penetration section, which plate has a width on a side of the other side which is narrower than that on a side of one side. The package includes a plurality of first lead pins disposed on the lower surface of the ceramic package along the other side, and a pair of second lead pins disposed on the lower surface of the ceramic package on both sides of a narrow portion of the heat radiation plate.

Abstract: The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided.

Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.

Abstract: The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a metallic carrier with the chip inserted into a cavity of the metallic carrier, and the step of selectively removing portions of the metallic carrier to define a heat spreader for the chip. The heat spreader can provide thermal dissipation, electromagnetic shielding and moisture barrier, whereas the interposer provides a CTE-matched interface and fan-out routing for the chip.

Abstract: A method of forming a semiconductor package includes forming a thermal conductivity layer and attaching the thermal conductivity layer to a chip. The chip has a first surface and a second surface. The thermal conductivity layer is attached to the first surface of the chip. The thermal conductivity layer provides a path through which heat generated from the chip is dissipated to the ambient. A substrate is attached to the second surface of the chip. A molding compound is formed above the substrate to encapsulate the chip and the thermal conductivity layer.

Abstract: A semiconductor package includes a mold body having a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, a first semiconductor module including a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of second semiconductor channels and a second encapsulation layer disposed above the second semiconductor channels. The semiconductor package further includes a plurality of external connectors extending through one or more of the side faces of the mold body.

Abstract: A semiconductor device includes a carrier and a metallic structure including a metallic member, a pad and a via portion; wherein the metallic member is disposed inside the carrier, the pad is configured for receiving a solder bump and is disposed on a surface of the carrier, the via portion is configured for electrically connecting the metallic member and the pad, and the via portion is disposed proximal to an end of the pad. Further, a method of manufacturing a semiconductor device includes providing a carrier, removing a portion of the carrier for forming a via extending a surface of the carrier to an interior of the carrier, filling the via by a conductive material, and disposing the conductive material on the surface of the carrier, wherein the via is disposed proximal to an end portion of the conductive material.

Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.

Abstract: A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 ?m2 and about 1,300 ?m2.

Abstract: The disclosed technology relates to pillar-type microbumps formed on a semiconductor component, such as an integrated circuit chip or an interposer substrate, and a method of forming the pillar-type microbumps. In one aspect, a method of forming the pillar-type microbump on a semiconductor component includes providing the semiconductor component, where the semiconductor component has an upper metallization layer, and the metallization layer has a contact area. The method additionally includes forming a passivation layer over the metallization layer. The method additionally includes forming a plurality of openings through the passivation layer such that the contact area is exposed at a bottom of the openings. The method further includes forming the microbump over the contact area, where the microbump forms an electrical connection with the contact area through the openings.

Abstract: A semiconductor device includes a support body provided with a wiring layer that includes a first pad; a first semiconductor chip; a first relay substrate stacked on the first semiconductor chip through a first non-conductive adhesion layer and including a first conductive portion and a first protruding electrode electrically connected to the first conductive portion; a second semiconductor chip stacked on the first relay substrate through a second non-conductive adhesion layer, the first protruding electrode of the first relay substrate penetrating the second non-conductive adhesion layer to be connected to the second semiconductor chip; and a first metal wire formed at the first relay substrate to be connected to the first conductive portion for electrically connecting the first conductive portion with the first pad of the wiring layer of the support body.

Abstract: A semiconductor package and a method for manufacturing a semiconductor package that comprises a unit substrate, for example to which a semiconductor chip is attached, embedded in a base substrate on which a semiconductor device may be mounted. The base substrate may, for example, comprise vias between top and bottom surfaces thereof and/or vias between the top surface of the base substrate and a top surface of the unit substrate embedded within the base substrate.

Abstract: A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.

Abstract: A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Abstract: A device includes a metal pad, a passivation layer overlapping edge portions of the metal pad, and a first polymer layer over the passivation layer. A Post-Passivation-Interconnect (PPI) has a level portion overlying the first polymer layer, and a plug portion that has a top connected to the level portion. The plug portion extends into the first polymer layer. A bottom surface of the plug portion is in contact with a dielectric material. A second polymer layer is overlying the first polymer layer.

Abstract: Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer.

Abstract: According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.

Abstract: A semiconductor package substrate includes an insulating substrate, a circuit pattern on the insulating substrate, a protective layer formed on the insulating substrate to cover the circuit pattern on the insulating substrate, a pad formed on the protective layer while protruding from a surface of the protective layer, and an adhesive member on the pad.

Abstract: A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder treatment improves the adhesion between the exposed traces (e.g., the non-BOT traces) and a solder resist layer.

Abstract: Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.

Abstract: A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided.

Abstract: Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.

Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and H2SO4 can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.

Abstract: An integrated circuit device and a method for making it are provided. The integrated circuit device comprises plural conductive layers, plural dielectric layers and plural first stopping layers. The conductive layers are extending in a first direction. The dielectric layers are paralleled to the conductive layers, and the conductive layers and the dielectric layers are disposed in an alternative arrangement. The first stopping layers are disposed over the conductive layers and the dielectric layers. The first stopping layers make no contact with the conductive layers.

Abstract: This invention provides an ohmic contact structure including: a semiconductor substrate having a top surface which includes a plurality of micro-structures; and a conductive layer, which is formed on the micro-structures. An ohmic contact is formed by the conductive layer and the semiconductor substrate. The present invention also provides a semiconductor device having the ohmic contact structure.

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

Abstract: A manufacturing process, which we term Self-Aligned Capillarity-Assisted Lithography for manufacturing devices having nano-scale or micro-scale features, such as flexible electronic circuits, is described.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a carrier, a first redistribution layer (RDL) over the carrier, a semiconductor die over the first RDL, an adhesive layer between the semiconductor die and the first RDL, and a molding compound encapsulating the first RDL, the semiconductor die, and the adhesive layer. The first RDL includes at least one pattern electrically isolated from any component of the semiconductor structure. The present disclosure provides a method for manufacturing a semiconductor structure discussed herein. The method includes forming an RDL on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL.

Abstract: A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of semiconductor driver channels and a second encapsulation layer disposed above the semiconductor driver channels. The semiconductor driver channels are configured to drive the semiconductor transistor chips.

Abstract: The embodiments described provide methods and structures for forming support structures between dies and substrate(s) of a three dimensional integrated circuit (3DIC) structures. Each support structure adheres to surfaces of two neighboring dies or die and substrate to relieve stress caused by bowing of the die(s) and/or substrate on the bonding structures formed between the dies or die and substrate. The cost of the support structures is much lower than other processes, such as thermal compression bonding, to reduce the effect of bowing of dies and substrates on 3DIC formation. The support structures improves yield of 3DIC structures.