Patents Issued in December 15, 2015
  • Patent number: 9214186
    Abstract: A data storage device is disclosed comprising a disk comprising a plurality of tracks and a head actuated over the disk, wherein the head comprises a read element radially offset from a write element. A first pattern is written to a single track, and the first pattern is read from the single track to generate a first read signal from which a first quality metric is generated. A second pattern is written to the single track, wherein the second pattern is different from the first pattern. The second pattern is read from the single track to generate a second read signal from which a second quality metric is generated. The radial offset of the read element and write element is measured based on the first and second quality metrics.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: December 15, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventor: Phillip Scott Haralson
  • Patent number: 9214187
    Abstract: According to one embodiment, a magnetic medium's readback signal samples are processed iteratively to provide a slip-resistant read channel by feeding the decoder output decisions back to the read channel front end where they are used to drive the decision-aided digital signal processing functions and control loops. Since data decisions provided by the decoder are typically more reliable than those provided by the detector, a significant performance improvement is obtained. A more reliable operation of the digital front-end signal processing functions in turn allows improvements to the reliability of the decoded data. Usage of Error Correcting Code (ECC) schemes that are soft decodable makes the read channel technique, described according to various embodiments herein, particularly efficient.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: December 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer, Sedat Oelcer
  • Patent number: 9214188
    Abstract: A method is disclosed for selecting a rotation speed when servo writing a disk of a disk drive. A gas is injected into a head disk assembly (HDA) comprising the disk. The disk is rotated while reading data from the disk using a head to generate a read signal. A fly height modulation (FHM) of the head is measured in response to the read signal. When the FHM exceeds a threshold, the rotation speed is adjusted. The disk is servo written at the adjusted rotation speed. After servo writing the disk and evacuating the gas from the HDA, the disk is rotated at a normal rotation speed lower than the adjusted rotation speed used to servo write the disk, and manufacturing data is written to the disk at the normal rotation speed.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: December 15, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jern Khang Tan, Amar Nath, Boworn Panyavoravaj
  • Patent number: 9214189
    Abstract: An image editing method includes detecting positions of the moving object contained in the images for the stored series of images, detecting a locus of movement of the moving object based on the detected positions of the moving object contained in the series of images, specifying an image corresponding to a feature point of the detected locus of movement of the moving object, extracting, from the series of images stored in the memory, images which include the specified image and correspond to a second shooting time interval longer than the first shooting time interval, and storing the extracted series of images as an image file in a memory.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: December 15, 2015
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Kota Endo
  • Patent number: 9214190
    Abstract: An audio signal processing method includes the steps of: dividing an audio signal data stream into a plurality of selection segments; determining a target segment in the audio signal data stream, the target segment including a splice point for splicing a splice segment thereto; selecting one of the selection segments as the splice segment according to at least one parameter of the target segment; and processing the target segment and the splice segment to splice the splice segment to the target segment, and outputting a processed segment.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: December 15, 2015
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yi-Chun Lin, Wen-Haw Wang, Kai-Hsiang Chou
  • Patent number: 9214191
    Abstract: A method and a system of associating correlating metadata with data assets, such as video and audio files, so that the files are rendered as a combination presentation are described herein. The system includes a client a media capture device that provides on board storage, network connectivity, preprocessing, preview buffering, file management, and an eventing system. The method includes capturing the media, associating the media with other media via an identifier, and supports associating correlating metadata prior to time of media capture and during media capture on the capture device itself, and after media capture either on a local machine or on an on-line group. When the combination presentation is presented, additional associated advertising and annotations may be provided upon rendering.
    Type: Grant
    Filed: October 6, 2012
    Date of Patent: December 15, 2015
    Assignee: WHP Workflow Solutions, LLC
    Inventor: Thomas Guzik
  • Patent number: 9214192
    Abstract: A video processing system adaptively generates and processes volume/file structure and navigation data of different data format and converts data between different formats for decoding, recording and other applications. The system processes the volume/file structure and navigation data in distinct modes including (a) pre-processing, (b) contemporaneous and (c) post-processing modes. In addition, the system provides navigation information supporting navigation through different images of one or more video programs by parsing encoded packetized data representative of a sequence of individual images to determine parameters to support navigation through the sequence of individual images. The determined parameters are formatted into a predetermined data structure and incorporated into a pre-formed navigation data field.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: December 15, 2015
    Assignee: THOMSON LICENSING
    Inventors: Shu Lin, Donald Henry Willis, Mark Alan Schultz
  • Patent number: 9214193
    Abstract: An apparatus includes a display controller, a detecting unit, and a reproduction unit. The display controller is configured to control a display unit to display marks corresponding to a plurality of images. The detecting unit is configured to detect selection information entered by a user. The selection information includes path information and additional information. The reproduction unit is configured to reproduce at least one of the plurality of images based on the additional information.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: December 15, 2015
    Assignee: SONY CORPORATION
    Inventor: Sawako Kiriyama
  • Patent number: 9214194
    Abstract: The invention in at least one embodiment includes a system that includes a chassis having a frame present within a housing where the frame includes at least two plates having a base and two grills running widthwise along and on opposite ends of the base, a plurality of walls between the at least two plates, and at least one baffle running between the plates at an angle to the plates; at least one power supply; and a plurality of fans electrically connected to the at least one power supply; wherein there are at least two air flow paths through the chassis that pass through at least one fan and pass at least one baffle through a duct defined by the housing and the frame. In at least one embodiment, the chassis receives at least one storage drive.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 15, 2015
    Assignee: GreenTec-USA, Inc.
    Inventors: Stephen E. Petruzzo, David Hatchett
  • Patent number: 9214195
    Abstract: A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: December 15, 2015
    Assignee: SK Hynix Inc.
    Inventors: Seung Wook Kwak, Sang Hoon Shin, Keun Soo Song
  • Patent number: 9214196
    Abstract: A system and method for powering a wireless sensor device are disclosed. In a first aspect, the wireless sensor device comprises at least two electrodes configured to be attached to a body and at least two leads coupled to the at least two electrodes. The wireless sensor device also includes a system on chip (SoC) coupled to the at least two leads and a portable power source (Vbatt) coupled to the SoC. When the at least two electrodes are attached to the body, a difference in resistance is measured between the at least two leads by the SoC and the difference in resistance is utilized by the SoC to enable the portable power source to activate the wireless sensor device.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: December 15, 2015
    Assignee: VITAL CONNECT, INC.
    Inventors: Arshan Aga, Yun Yang
  • Patent number: 9214197
    Abstract: A secondary memory device includes a substrate configured to receive power from an external power source, at least one of non-volatile memory devices mounted on the substrate, a control device mounted on the substrate to control the non-volatile memory devices, and a secondary battery electrically connected to the substrate and configured to supply second power to the substrate when a power supply from the external power source is abnormally stopped.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: December 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-bo Shim, Cheol Kwon, Jong-yun Yun, Yeong-kyun Lee
  • Patent number: 9214198
    Abstract: An electronic device includes a subsystem, a plurality of energy storage elements coupled to the subsystem through one or more switches, and a charging and monitoring apparatus for concurrently charging the plurality of energy storage elements and monitoring operability of the energy storage elements. A first subset of the energy storage elements is coupled to a first node and a second subset of the energy storage elements is coupled to a second node of a bridge circuit. A power supply provides a DC charging voltage and an AC test voltage to both the first and second subsets of the energy storage elements. A monitoring circuit produces a predefined fault signal if a predefined electrical characteristic of the first subset of the energy storage elements differs from a same predefined electrical characteristic of the second subset of the energy storage elements by more than a predefined amount.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: December 15, 2015
    Assignee: SANDISK ENTERPRISE IP LLC
    Inventors: Robert W. Ellis, Gregg S. Lucas
  • Patent number: 9214199
    Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: December 15, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Oswin E. Housty, Gerald Talbot
  • Patent number: 9214200
    Abstract: A system includes a transmitter circuit and a receiver circuit that are coupled together through transmission lines. The transmitter circuit generates an early timing signal, a nominal timing signal, and a late timing signal. A multiplexer circuit selects between the early and the late timing signals based on a data signal to generate an encoded output signal that encodes the data signal. The nominal timing signal and the encoded output signal are transmitted through the transmission lines to the receiver circuit. The receiver circuit samples the encoded output signal in response to the nominal timing signal to generate even and odd sampled data signals. Complementary timing signals can be transmitted through transmission lines on opposite sides of the encoded output signal to provide crosstalk cancellation.
    Type: Grant
    Filed: February 26, 2011
    Date of Patent: December 15, 2015
    Assignee: Rambus Inc.
    Inventors: Michael Bucher, John Wilson
  • Patent number: 9214201
    Abstract: An operating access method for a DRAM is provided. A first address is obtained via an address bus and a first command is obtained via a command bus from a controller. A second address is obtained via the address bus and a second command is obtained via the command bus from the controller after the first command is obtained. The first address and the second address are combined to obtain a valid address, wherein the valid address is a row address when each of the first command and the second command is an active command. In addition, the valid address is a column address when the second command is an access command.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: December 15, 2015
    Assignee: MEDIATEK INC.
    Inventor: Der-Ping Liu
  • Patent number: 9214202
    Abstract: An input buffer includes a first buffer, a feedback circuit and a second buffer circuit. The feedback circuit includes a feedback resistor and a feedback inverter. The first buffer may be configured to output an amplification signal to an output node of the first buffer based on an input signal. The feedback circuit connected to the output node of the first buffer may be configured to control the amplification signal. The second buffer circuit may be configured to output a buffer output signal by buffering the amplification signal. The feedback resistor may receive the amplification signal from the output node of the first buffer and provide a feedback signal to a feedback node. The feedback inverter is connected between the feedback node and the output node. The feedback inverter may be configured to control the amplification signal based on the feedback signal.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: December 15, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Shim, Seung-Jun Bae, Won-Joo Yun
  • Patent number: 9214203
    Abstract: A sensing apparatus and data sensing method are provided. The sensing apparatus includes an initial circuit, a reference current generator and a sensing circuit. The initial circuit discharges a sensing end to a reference ground during a discharge period, and pre-charges the sensing end to a preset voltage level during a pre-charge period according to an output signal. The reference current generator draws a reference current from the sensing end. The sensing circuit senses a voltage level on the sensing end to generate the output signal. Wherein, the sensing end receives a cell current from a memory cell, and the pre-charge period is after the discharge period.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: December 15, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Po-Ping Wang, Cheng-Da Huang, Chun-Hung Lin
  • Patent number: 9214204
    Abstract: Apparatus for storing data and a method of adapting a duration of a wordline pulse in an apparatus for storing data are provided. Sensor circuitry comprises a calibrated bitcell which is calibrated to use a duration of wordline pulse which matches a longest wordline pulse required by any bitcell in an array of bitcells for a successful write operation to be carried out. The duration of wordline pulse is signalled to wordline pulse circuitry, which generates a wordline pulse for the array of bitcells with this wordline pulse duration. The sensor circuitry is configured to adapt the wordline pulse duration in dependence on current local conditions in which the apparatus operates to compensate for influence of the current local conditions on the longest wordline pulse required by any bitcell in the array of bitcells.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: December 15, 2015
    Assignee: ARM Limited
    Inventors: Vikas Chandra, Peter Beshay
  • Patent number: 9214205
    Abstract: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: December 15, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Atsuo Koshizuka
  • Patent number: 9214206
    Abstract: A method of testing a non-volatile memory device and a method of managing the non-volatile memory device are provided. The method of testing the non-volatile memory device includes calculating first and second values based on program loop frequencies corresponding to word lines of a memory area. A characteristic value of the memory area may be calculated based on the first and second values, and may be compared to a reference value to determine whether the memory area is defective.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: December 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-In Park, Boh-Chang Kim, Bu-il Nam, Dong-Ku Kang
  • Patent number: 9214207
    Abstract: A data decoding apparatus is provided, which includes at least one processor block, at least one hardware block, and a memory processing unit to control the at least one processor block or the at least one hardware block to access a memory and to read or write data with minimum delay.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 15, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Won Chang Lee
  • Patent number: 9214208
    Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: December 15, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Esin Terzioglu, Gil I. Winograd
  • Patent number: 9214209
    Abstract: Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: December 15, 2015
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Takashi Ishiguro, Masayuki Sato, Tetsuo Hironaka, Masato Inagi
  • Patent number: 9214210
    Abstract: A block decoder including a first selection unit configured to receive a block address signal and output a block select signal to any one of a plurality of blocks, and a second selection unit configured to receive a high voltage and control a potential level of the block select signal according to the block address signal.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 15, 2015
    Assignee: SK Hynix Inc.
    Inventor: Gyo Soo Chu
  • Patent number: 9214211
    Abstract: Respective die IDs are determined for a plurality of memory die commonly packaged as a memory device based on their respective Unique Identifiers (“UIDs”). An external controller initiates an internal Die ID (“DID”) determination process in which each die eventually asserts a signal on its inter-die signaling pin after a number of clocks as determined by its UID, and assigns itself a Die ID based on the number of signals asserted by other die prior to its own signaling response. Each die keeps track of the number of signals asserted by the other die prior to its own signaling response, as well as, optionally, the total number of signals on the signaling pin to determine the package die count for the device.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: December 15, 2015
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventor: Johnny Chan
  • Patent number: 9214212
    Abstract: A magnetic-assist, spin-torque transfer magnetic tunnel junction device and a method for performing a magnetic-assist, spin-torque-transfer write to the device are disclosed. In an exemplary embodiment, the magnetic tunnel junction device includes a first electrode, a pinned layer disposed on the first electrode, a free layer disposed on the pinned layer, and a barrier layer disposed between the pinned layer and the free layer. The device further includes a second electrode electrically coupled to the free layer, the second electrode containing a magnetic assist region. In some embodiments, the magnetic assist region is configured to produce a net magnetic field when supplied with a write current. The net magnetic field is aligned to assist a spin-torque transfer of the write current on the free layer.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chwen Yu
  • Patent number: 9214213
    Abstract: A magnetic memory according to an embodiment includes: a magnetic layer including a plurality of magnetic domains and a plurality of domain walls, and extending in a direction; a pinning layer formed with nonmagnetic phases and magnetic phases, extending in an extending direction of the magnetic layer and being located adjacent to the magnetic layer; an electrode layer located on the opposite side of the pinning layer from the magnetic layer; an insulating layer located between the pinning layer and the electrode layer; a current introducing unit flowing a shift current to the magnetic layer, the shift current causing the domain walls to shift; a write unit writing information into the magnetic layer; a read unit reading information from the magnetic layer; and a voltage generating unit generating a voltage to be applied between the pinning layer and the electrode layer.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: December 15, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shiho Nakamura, Hirofumi Morise, Tsuyoshi Kondo
  • Patent number: 9214214
    Abstract: One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: December 15, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaochun Zhu, Steven M. Millendorf, Xu Guo, David M. Jacobson, Kangho Lee, Seung H. Kang, Matthew Michael Nowak
  • Patent number: 9214215
    Abstract: Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: December 15, 2015
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Brian S. Doyle, Kaan Oguz, Satyarth Suri, Robert S. Chau, Charles S. Kuo, Mark L. Doczy, David L. Kencke
  • Patent number: 9214216
    Abstract: A semiconductor device includes: a plurality of memory cell blocks, a counting unit suitable for counting the number of active operations on each of the memory cell blocks, based on an active command and a row address, and a refresh control unit suitable for determining a target memory cell block among the memory cell blocks and controlling an additional refresh operation for the target memory cell block to be performed based on the counting result.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: December 15, 2015
    Assignee: SK Hynix Inc.
    Inventor: Chang-Hyun Kim
  • Patent number: 9214217
    Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.
    Type: Grant
    Filed: August 3, 2014
    Date of Patent: December 15, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Natsuki Ikehata, Kazuo Tanaka, Takeo Toba, Masashi Arakawa
  • Patent number: 9214218
    Abstract: Disclosed herein a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, and the device further includes a driver configured to drive a selected one of the word lines from an inactive level to an active and to drive the selected one of the word lines from the active level to an intermediate level at a first rate and from the intermediated level to the inactive level at a second rate. The intermediate level is between the active and inactive levels, and the first rate is greater than the second rate.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: December 15, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 9214219
    Abstract: Described are dynamic, random-access memories (DRAM) architectures and methods for subdividing memory activation into fractions of a page. Circuitry in support of sub-page activation is placed in the intersections of local wordline drivers and sense-amplifier stripes to allow independent control of adjacent arrays of memory cells without significant area overhead.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: December 15, 2015
    Assignee: Rambus Inc.
    Inventor: Thomas Vogelsang
  • Patent number: 9214220
    Abstract: A semiconductor memory apparatus includes a control signal generation unit configured to generate a control signal according to a mode control signal and a refresh signal; a first sense amplifier driving voltage generation unit configured to generate a first sense amplifier driving voltage according to the control signal, a first sense amplifier enable signal and a switching control signal; a switching control unit configured to generate the switching control signal according to the control signal and a second sense amplifier enable signal; a second sense amplifier driving voltage generation unit configured to generate a second sense amplifier driving voltage according to the second sense amplifier enable signal; and a switching unit configured to electrically couple or decouple output nodes of the first sense amplifier driving voltage generation unit and the second sense amplifier driving voltage generation unit according to the switching control signal.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: December 15, 2015
    Assignee: SK Hynix Inc.
    Inventor: Do Hong Kim
  • Patent number: 9214221
    Abstract: A semiconductor device is provided. The semiconductor device includes a logic circuit, an SRAM circuit coupled to a power line, and a switch coupled between the logic circuit and the power line. Before the switch is changed to an off position, a part of information held in the logic circuit is transferred to the SRAM circuit.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: December 15, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
  • Patent number: 9214222
    Abstract: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the read word line WLB corresponding to the selected memory cell 3. A write operation activates the write word line WLA corresponding to the selected memory cell 3. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: December 15, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichiro Ishii, Yoshikazu Saito, Shinji Tanaka, Koji Nii
  • Patent number: 9214223
    Abstract: A resistance memory device and a memory apparatus and data processing apparatus having the same are provided. The resistance memory device includes a pair of electrode layers and a variable resistance layer interposed between the pair of electrode layers. The variable resistance layer includes at least one variable resistance material layer and a piezoelectric material layer coupled to the at least one variable resistance material layer.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: December 15, 2015
    Assignee: SK HYNIX INC.
    Inventors: Hyun Mi Hwang, Hyung Dong Lee
  • Patent number: 9214224
    Abstract: A memory element includes a nonvolatile switch to be set to a first low resistance state by applying a voltage higher than a positive threshold voltage and to a second high resistance state by applying another voltage more negative than a negative threshold voltage. The memory element further includes a volatile switch in series with the nonvolatile switch, the nonvolatile switch to be set to a third low resistance state by applying a current higher than a threshold current and to fourth high resistance state by applying a current lower than the threshold current. A method for operating a memory array with memory elements with series volatile and nonvolatile switches is also provided.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: December 15, 2015
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Yoocharn Jeon
  • Patent number: 9214225
    Abstract: A 3D variable resistance memory device having a junction FET and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. A channel layer is formed on the column string selection switch. A plurality of gates stacked along a length of the channel layer and each of the gates contacts an outer side of the channel layer. A variable resistance layer is formed on an inner side of the channel layer, and contacts the channel layer.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: December 15, 2015
    Assignee: SK Hynix Inc.
    Inventor: Nam Kyun Park
  • Patent number: 9214226
    Abstract: A semiconductor memory device including a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: December 15, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki Toda
  • Patent number: 9214227
    Abstract: Provided is a nonvolatile memory device including a resistive memory cell and semiconductor system using the same that is capable of setting the reference resistance value using resistance values of a plurality of memory cells. The nonvolatile memory device comprises one or more column lines, two or more row lines, a plurality of memory cells configured to be connected to the column lines and each of the row lines, and a reference resistance setting unit configured to enable a subset or all of the column lines and row lines and to set a reference resistance value.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: December 15, 2015
    Assignee: SK Hynix Inc.
    Inventor: Kyu Sung Kim
  • Patent number: 9214228
    Abstract: A semiconductor memory device has a memory cell array including memory cells, the memory cell being disposed at an intersection of first lines and second lines, the second lines being disposed intersecting the first lines, and the memory cell including a variable resistance element; and a control circuit. The control circuit is configured to execute a forming operation sequentially on a plurality of the memory cells. The control circuit applies a forming voltage to a selected memory cell of the memory cells, and controls the forming voltage such that the forming voltage is lower as the forming operation progresses.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: December 15, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takamasa Okawa, Takayuki Tsukamoto, Yoichi Minemura, Hiroshi Kanno, Atsushi Yoshida
  • Patent number: 9214229
    Abstract: A family of phase change materials GewSbxTeyNz having a crystallization temperature greater than 410° C., wherein a Ge atomic concentration is within a range from 43% to 54%, a Sb atomic concentration is within a range from 6% to 13%, a Te atomic concentration is within a range from 14% to 23%, and a N atomic concentration is within a range of 15% to 27%, is described. A method for programming a memory device including such phase change materials is also described.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: December 15, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Huai-Yu Cheng, Hsiang-Lan Lung, Che-Min Lin
  • Patent number: 9214230
    Abstract: A cell of a resistive random access memory including (i) a resistive element and (ii) a switch. The resistive element includes (i) a first electrode, and (ii) a second electrode. The switch includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact has a shape including a first surface and a second surface that is opposite to the first surface. The shape of the third contact tapers inward from the first surface towards the second surface.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: December 15, 2015
    Assignee: Marvell World Trade LTD.
    Inventors: Pantas Sutardja, Albert Wu, Winston Lee, Peter Lee, Runzi Chang
  • Patent number: 9214231
    Abstract: Examples disclose a crossbar memory with a first crossbar to write data values corresponding to a word. The crossbar memory further comprises a second crossbar, substantially parallel to the first crossbar, to receive voltage for activation of data values across the second crossbar. Additionally, the examples of the crossbar memory provide an output line that interconnects with the crossbars at junctions, to read the data values at the junctions. Further, the examples of the crossbar memory provide a logic module to determine whether the second crossbar data values correspond to the word written in the first crossbar.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: December 15, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Matthew D Pickett, Frederick Perner
  • Patent number: 9214232
    Abstract: Methods and apparatuses for calibrating data sampling points are disclosed herein. An example apparatus may include a memory that may be configured to receive a calibration command and an attribute. The memory may include a first register that is configured to store a tuning data pattern and a second register that is configured to receive and store the tuning data pattern stored in the first register. The second register may be further configured to store the tuning data pattern responsive, at least in part, to the memory receiving the calibration command. The memory may be configured to execute an operation on at least one of the tuning data pattern stored in the first register or the tuning data pattern stored in the second register based, at least in part, on the attribute.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: December 15, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Paolo E. Mangalindan, Alberto Troia, Yihua Zhang, Poorna Kale
  • Patent number: 9214233
    Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: December 15, 2015
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo
  • Patent number: 9214234
    Abstract: According to one embodiment, a memory cell string stacked body includes first memory cell transistors above a semiconductor substrate, and second memory cell transistors below a first channel semiconductor film, and one of the first memory cell transistors and one of the second memory cell transistors share with a control gate electrode. The control gate electrodes of the first memory cell transistors cover an upper surface of a first charge storage layer and at least a part of a side surface in a second direction via a first insulating film in the one of the first memory cell transistors. The control gate electrodes of the second memory cell transistors cover only a lower surface of a second charge storage layer via a second insulating film in one of the second memory cell transistors.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: December 15, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideto Takekida
  • Patent number: 9214235
    Abstract: A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: December 15, 2015
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie