Abstract: The surface of a sapphire substrate having a c-plane main surface is patterned by ICP dry etching. The patterned sapphire substrate is thermally treated in a hydrogen or nitrogen atmosphere at a temperature of less than 700° C. or at a temperature of more than 800° C. to 1100° C. An AlN buffer layer is formed by magnetron sputtering on the surface on the patterned side of the sapphire substrate heated at a temperature of 200° C. to less than 700° C. On the buffer layer, a Group III nitride semiconductor layer having a c-plane main surface is formed so as to have a thickness of 1 ?m to 10 ?m by MOCVD.

Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure attached to a wafer handle having at least one aperture that extends through the wafer handle to an exposed portion of the semiconductor stack structure. A thermally conductive and electrically resistive polymer substantially fills the at least one aperture and contacts the exposed portion of the semiconductor stack structure. One method for manufacturing the semiconductor device includes forming patterned apertures in the wafer handle to expose a portion of the semiconductor stack structure. The patterned apertures may or may not be aligned with sections of RF circuitry making up the semiconductor stack structure. A following step includes contacting the exposed portion of the semiconductor stack structure with a polymer and substantially filling the patterned apertures with the polymer, wherein the polymer is thermally conductive and electrically resistive.

Abstract: There is provided a method for forming a graphene layer. The method includes forming an article that comprises a carbon-containing self-assembled monolayer (SAM). A layer of nickel is deposited on the SAM. The article is heated in a reducing atmosphere and cooled. The heating and cooling steps are carried out so as to convert the SAM to a graphene layer.

Abstract: Group III nitride semiconductor having reduced threading dislocation density and uniform Ga-polar surface is provided. Forming a capping layer on a buffer layer containing Al as an essential element at a temperature lower than a temperature at which an oxide of element constituting the buffer layer is formed. Heat treating the substrate having the buffer layer covered by the capping layer at a temperature higher than a temperature at which a crystal of body semiconductor grows without exposing the surface of the buffer layer. The substrate temperature is decreased to a temperature at which a crystal of the body semiconductor grows and the body semiconductor is grown.

Abstract: The embodiments of the disclosure may generally provide a method and apparatus for forming thin film transistor device that includes an indium gallium zinc oxide (IGZO) layer using a multi-component precursor gas. The embodiments of the disclosure may provide a plasma enhanced chemical vapor deposition system configured to form an IGZO layer on large area substrates. However, it should be understood that the disclosure has utility in other system configurations such other types of chemical vapor deposition systems and any other system in which distributing a multi-component precursor gas to and within a process chamber is desired.

Abstract: Method for manufacturing at least one semiconductor structure (130) on the surface (105) of a substrate (100) wherein the surface comprises silicon. The method comprises steps consisting of providing the substrate (100), forming in contact with an area (101) of the surface (105), referred to as the formation area, a layer (120) of a first material, the remainder (102) of the surface (105), referred to as the free area, remaining free from the first material, the dimensions of the formation area (101) and the first material being suitable for forming the structure (130), the first material comprising gallium, the formation of said layer (120) taking place at a temperature less than 600° C., and forming the structure (130) in contact with the layer (120).

Abstract: A method for producing a compound semiconductor crystal, includes; a sacrificial layer formation step of forming a sacrificial layer containing Cx1Siy1Gez1Sn1-x1-y1-z1 (0?x1<1, 0?y1?1, 0?z1?1, and 0<x1+y1+z1?1), on a base wafer whose surface is made of a silicon crystal; a crystal formation step of forming, on the sacrificial layer, a compound semiconductor crystal lattice-matching or pseudo lattice-matching the sacrificial layer; and a crystal removal step of removing the compound semiconductor crystal from the base wafer, by etching the sacrificial layer.

Abstract: A ZnSnO3/ZnO nanowire, a method of forming a ZnSnO3/ZnO nanowire, a nanogenerator including a ZnSnO3/ZnO nanowire, a method of forming a ZnSnO3 nanowire, and a nanogenerator including a ZnSnO3 nanowire are provided. The ZnSnO3/ZnO nanowire includes a core and a shell that surrounds the core, wherein the core includes ZnSnO3 and the shell includes ZnO.

Abstract: One embodiment relates to a pillar-supported array of micro electron lenses. The micro-lens array includes a base layer on a substrate, the base layer including an array of base electrode pads and an insulating border surrounding the base electrode pads so as to electrically isolate the base electrode pads from each other. The micro-lens array further includes an array of lens holes aligned with the array of base electrode pads and one or more stacked electrode layers having openings aligned with the array of lens holes. The micro-lens array further includes one or more layers of insulating pillars, each layer of insulating pillars supporting a stacked electrode layer. Another embodiment relates to a method of fabricating a pillar-supported array of micro electron lenses. Other embodiments, aspects and features are also disclosed.

Abstract: There is provided an ion implantation method, a composition for forming an ion implantation film and a resist underlayer film-forming composition. An ion implantation method including the steps of: forming a film by applying a film-forming composition containing a compound including an element in group 13, group 14, group 15, or group 16 and an organic solvent onto a substrate and baking the film-forming composition; and implanting impurity ions into the substrate from above through the film and introducing the element in group 13, group 14, group 15, or group 16 in the film into the substrate. The film-forming composition is a film-forming composition for ion implantation containing a compound including an element in group 13, group 14, group 15, or group 16, and an organic solvent. In addition, the underlayer film-forming composition contains a compound having at least two borate ester groups.

Abstract: Embodiments of the invention generally relate to apparatus and methods of thermal processing of semiconductor substrates using a pellicle to eliminate contamination of an aperture member. The aperture member is disposed between an energy source and a substrate to be processed. The pellicle may be a thin piece of membrane that is substantially transparent to selected forms of energy, such as pulses of electromagnetic energy from a laser that emits radiation at one or more appropriate wavelengths for a desired period of time. In one embodiment, the pellicle is mounted at a predetermined distance from the aperture member and covering pattern openings (i.e., apertures) formed on the aperture member such that any particle contaminants that may land on the aperture member will land on the pellicle. The pellicle keeps particle contaminants out of focus in the final energy field, thereby preventing particle contaminants from being imaged onto the processed substrate.

Abstract: A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

Abstract: A semiconductor device is fabricated by, inter alia, forming a sacrificial liner on an active portion of a semiconductor substrate, oxidizing the sacrificial liner to transform the sacrificial liner into a gate dielectric layer, and forming a gate on the gate dielectric layer.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern along side and bottom surfaces of the trench, forming a second metal gate film on the first metal gate film pattern and the insulation film, and forming a second metal gate film pattern positioned on the first metal gate film pattern by removing the second metal gate film to expose at least a portion of the insulation film and forming a blocking layer pattern on the second metal gate film pattern by oxidizing an exposed surface of the second metal gate film pattern.

Abstract: The performances of a semiconductor device are improved. A semiconductor device has a first electrode and a dummy electrode formed apart from each other over a semiconductor substrate, a second electrode formed between the first electrode and the dummy electrode, at the circumferential side surface of the first electrode, and at the circumferential side surface of the dummy electrode, and a capacitive insulation film formed between the first electrode and the second electrode. The first electrode, the second electrode, and the capacitive insulation film form a capacitive element. Further, the semiconductor device has a first plug penetrating through the interlayer insulation film, and electrically coupled with the first electrode, and a second plug penetrating through the interlayer insulation film, and electrically coupled with the portion of the second electrode formed at the side surface of the dummy electrode opposite to the first electrode side.

Abstract: A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the first and second side surfaces. The channel body has a depth between the first and second side surfaces less than a threshold channel body depth, combined with the gate structure which establishes an effective channel length of the cell greater than a threshold length. The combination of the channel body depth and effective channel length are related so that the cell channel body can be fully depleted, and sub-threshold leakage current can be suppressed when the memory cell has a high threshold state under a read bias.

Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, the ohmic contact structure has less than or equal to 5%, more preferably less than or equal to 2%, more preferably less than or equal to 1.5%, and even more preferably less than or equal to 1% degradation for 1000 hours High Temperature Soak (HTS) at 300 degrees Celsius. In another embodiment, the ohmic contact structure additionally or alternatively has less than or equal to 10% degradation, more preferably less than or equal to 7.5% degradation, more preferably less than or equal to 6% degradation, more preferably less than or equal to 5% degradation, and even more preferably less than 3% degradation for 1000 hours High Temperature operating Life (HToL) at 225 degrees Celsius and 50 milliamps (mA) per millimeter (mm).

Abstract: Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation.

Abstract: In a manufacturing method of sequentially forming a gate electrode film of the MOSFET, forming a gate electrode film of the non-volatile memory FET, patterning the gate electrode of the non-volatile memory FET, and patterning the gate electrode of the MOSFET, in order to form the MOSFET and the non-volatile memory FET on the same semiconductor substrate. The value of the product of S/L and H/L is specified in a case that the line of the gate electrode of the non-volatile memory FET is set to L, the space thereof is set to S, and the height thereof is set to H so that the thickness of a resist film on the gate electrode of the non-volatile memory FET which is formed in advance is set to a thickness which is not lost by etching for forming the gate electrode of the MOSFET.

Abstract: As device feature size shrinks, plasma induced damage is a major concern affecting micro-electronic and nano-electronic device fabrication. Pulsed plasmas are a means of mitigating the damages. However, in conventional standard etch chemistry, the etch rate for pulsed plasmas is reduced significantly resulting in a substantially decreased throughput of tech processes. A new etch chemistry is disclosed in the present invention to increase throughput in pulsed plasma applications driven mainly by the molecular radicals.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns.

Abstract: The present invention disclosed herein relates to a substrate treating apparatus and method. The substrate treating method includes: providing a substrate on which an oxide layer is formed; treating the oxide layer with a first process gas in a plasma state to substitute the treated oxide layer with a by-product layer; and heating the substrate to remove the by-product layer at a temperature which is above a first heating temperature at which the by-product layer is decomposed and is above a second heating temperature that is a boiling point of an additive by-product generated while the by-product layer is decomposed.

Abstract: A method of forming a semiconductor integrated circuit (IC) that has substantially equal gate heights regardless of different pattern densities in different regions of the IC includes providing a substrate with a first pattern density in a first region of the IC and a second pattern density in a second region of the IC, forming a first polysilicon layer above the substrate, the first polysilicon layer having an uneven upper surface, forming a stop layer above the first polysilicon layer, treating the stop layer to change its etch selectivity relative to the first polysilicon layer, forming a second polysilicon layer above the stop layer, removing the second polysilicon layer, the stop layer, and a top portion of the first polysilicon layer, the remaining portion of the first polysilicon layer having a planar upper surface.

Abstract: A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated.

Abstract: Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer.

Abstract: A method of manufacturing a semiconductor device, includes: placing a semiconductor element on an adhesive layer that is placed on a support body having a first through hole; placing a part in an area that includes a portion corresponding to the first through-hole, the portion being on the adhesive layer placed on the support body; forming a substrate on the adhesive layer by forming a resin layer on the adhesive layer, on which the semiconductor element and the part have been placed, the substrate including the semiconductor element, the part, and the resin layer; and detaching the substrate from the adhesive layer by pressing the part through the first through-hole.

Abstract: A method for producing an encapsulating layer-covered semiconductor element includes a disposing step of disposing a semiconductor element on a support, an encapsulating step of embedding and encapsulating the semiconductor element by an encapsulating layer in an encapsulating sheet including a peeling layer and the encapsulating layer laminated below the peeling layer and made from a thermosetting resin before complete curing, and a heating step of heating and curing the encapsulating layer after the encapsulating step. The heating step includes a first heating step in which the encapsulating sheet is heated at a first temperature, while being mechanically pressurized toward the support and a second heating step in which the encapsulating sheet is heated at a second temperature that is higher than the first temperature after the first heating step.

Abstract: Disclosed is a technique for preventing a water-repellent protective film formed on a resist film from peeling off during immersion exposure. A resist film is formed on the front surface of a substrate and then the peripheral edge portion of the resist film is removed. Before forming a water-repellent protective film onto the resist film, an adhesion-improving fluid, preferably hexamethyldisilazane gas, for improving the adhesion of the water-repellent protective film, is supplied to the region from which the resist film is removed.

Abstract: A substrate cleaning apparatus includes a supporting unit, provided in a processing chamber having a gas exhaust port, for supporting a substrate; one or more nozzle units, each for ejecting gas clusters to a peripheral portion of the substrate supported by the supporting unit to remove unnecessary substances from the peripheral portion; and a moving mechanism for changing relative positions of the supporting unit and the nozzle unit during ejecting the gas clusters. Each nozzle unit discharges a cleaning gas having a pressure higher than that in the processing chamber so that the cleaning gas is adiabatically expanded to form aggregates of atoms and/or molecules.

Abstract: A two-fluid nozzle 34 for spraying, toward a processing target object, droplets of a processing solution which are formed by mixing the processing solution discharged from a liquid discharge portion 48 and a gas discharged from a gas discharge opening 52 can uniformly spray the droplets of the processing solution having small diameters. Here, the liquid discharge portion 48 includes a multiple number of liquid discharge openings 47 arranged along a circle inside the gas discharge opening 52, and the multiple number of liquid discharge openings 47 discharge the processing solution in an outward direction of the circle.

Abstract: An apparatus for treating a substrate including a plurality of transfer rollers configured to transfer a substrate and simultaneously to be rotated to wet a back surface of the substrate; a plurality of chemical solution supply tanks configured to receive the chemical solution therein, the plurality of the chemical solution supply tanks arranged under the plurality of the transfer rollers, respectively, with being spaced apart a predetermined distance from each other; a main tank configured to surround the plurality of the chemical solution supply tanks; and an exhaustion unit configured to suck and exhaust fume generated in the process of wetting the back surface with the chemical solution and liquid drops of the chemical solution.

Abstract: The application describes an apparatus and a method for the thermal treatment of substrates, in particular thin film substrates for photovoltaic applications. The apparatus comprises at least one substrate carrier for supporting a substrate, a heating unit having at least one heating element for heating a substrate located on the substrate carrier and at least one heating element carrier for supporting the at least one heating element. The heating element carrier is designed to allow a local change in distance between the substrate carrier and the heating element, so as to be able to provide locally different heating intensities. In the method such a change in distance is carried out during the thermal treatment.

Abstract: Individually operable laser diodes in an array are associated with optical fibers for treatment of a material. Each laser diode has a generally Gaussian or similar profile. A guide block receives optical fiber terminal distal ends and enables irradiation of a surface for treatment with overlapping profiles. A control system controls individual laser diodes to achieve desired illumination profiles for a given process. The process is performed in a suitable environment which may include a vacuum system, controlled gaseous environment, or in a doping medium such as a surface coating or even a liquid. Optional relay optics interposed between the terminal distal ends and the treatment material allows distant relaying and reimaging. An optical isolator assembly may be interposed between the relay optics and the treatment material. The system and related methods allow direct irradiation from laser diodes to treat materials.

Abstract: An apparatus for dynamically adjusting the pitch between substrates in a substrate stack comprises first and second lift portions. The first lift portion supports a first group of the plurality of substrates, and the second lift portion supports a second group of the plurality of substrates. The first and second lift portions are operable to move the first and second groups of substrates in a first direction independently from each other. This independent movement enables the pitch, or spacing, between adjacent substrates to be dynamically adjusted so that an end effector of a robot can be positioned between such adjacent substrates to pick one of the substrates without inadvertently engaging another substrate that is not being picked. Other embodiments are disclosed.

Abstract: A substrate transfer device that transfers a substrate by allowing a substrate opening formed on a front surface of a substrate transfer vessel to face an opening formed on a partition wall from one side of the partition wall and separating a cover body of the substrate transfer vessel from the other side of the partition wall includes a door configured to open and close the opening from the other side of the partition wall; a reciprocating unit configured to straightly move the door back and forth between a first position where the opening is closed and a second position away from the first position toward the other side of the partition wall; and a rotating unit configured to rotate the door around a rotation axis in a straightly moving direction of the door between the second position and a third position deviated from a region facing the opening.

Abstract: In a loading area below a vertical furnace of a thermal treatment apparatus, a gas stream flows along a first direction from one side to the other side of the loading area into a first evacuation opening provided in the other side of the loading area. A thermal evacuation part is located, along the first direction, between a first evacuation opening and an upstream end of a substrate holding member located at an unload position that is located between the one side and the other side of the loading area. The thermal evacuation part includes a second evacuation opening that is arranged to oppose at least an upper part of the substrate holding member located at the unload position and evacuates an environment around the substrate holding member located at the unload position.

Abstract: A substrate processing system includes a processing unit, a substrate loading unit, a substrate unloading unit, and a carrying unit. A carrying device has a constitution in which a suction portion suctioning and holding a substrate is rotatable about an arm portion provided in a base portion and the substrate is rotated in the state where the substrate is held by a holding portion. A coating device has a constitution in which a liquid material is ejected from a nozzle to both surfaces of the substrate rotating in an upright state.

Abstract: A chuck includes a number of gas openings positioned to provide a gas flow to a backside of a wafer secured to the chuck. The chuck also includes a number of exhaust openings positioned to exhaust the gas at a distance from a topside edge of the wafer such that adverse thermal effects on the edge are reduced to a predetermined level.

Abstract: A microelectronic device includes a substrate having at least one microelectronic component on a surface thereof, a conductive via electrode extending through the substrate, and a stress relief structure including a gap region therein extending into the surface of the substrate between the via electrode and the microelectronic component. The stress relief structure is spaced apart from the conductive via such that a portion of the substrate extends therebetween. Related devices and fabrication methods are also discussed.

Abstract: An apparatus is provided for lifting a substrate. The apparatus comprises a first piece and a second piece. The apparatus further comprises a set of first contact points in a plane and a set of second contact points, where at least one contact point from each set is present on the first piece and the second piece. The apparatus also comprises an actuator that translates the first piece, substantially parallel to the plane, between a first position and a second position relative to the second piece. Additionally, the first position arranges the set of first contact points so that all of the contact points of the set of first contact points are able to engage the substrate, and the second position arranges the set of second contact points so that all of the contact points of the second set of contact points are able to engage the substrate.

Abstract: A substrate mounting stage that prevents poor attraction of substrates so as to improve the operating rate of a substrate processing apparatus. The substrate mounting stage is disposed in the substrate processing apparatus and has a substrate mounting surface on which a substrate is mounted. The arithmetic average roughness (Ra) of the substrate mounting surface is not less than a first predetermined value, and the initial wear height (Rpk) of the substrate mounting surface is not more than a second predetermined value.

Abstract: Embodiments of the present invention provide a methods for forming silicon recess structures in a substrate with good process control, particularly suitable for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming recess structures in a substrate includes etching a first portion of a substrate defined by a second portion formed in the substrate until a doping layer formed in the substrate is exposed.

Abstract: A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

Abstract: A bonded SOS substrate having a semiconductor film on or above a surface of a sapphire substrate is obtained by a method with the steps of implanting ions from a surface of a semiconductor substrate to form an ion-implanted layer; activating at least a surface from which the ions have been implanted; bonding the surface of the semiconductor substrate and the surface of the sapphire substrate at a temperature of 50° C. to 350° C.; heating the bonded substrates at a maximum temperature from 200° C. to 350° C. to form a bonded body; and irradiating visible light from a sapphire substrate side or a semiconductor substrate side to the ion-implanted layer of the semiconductor substrate for embrittling an interface of the ion-implanted layer, while keeping the bonded body at a temperature higher than the temperature at which the surfaces of the semiconductor substrate and the sapphire substrate were bonded.

Abstract: Method of making a bonded SOS substrate with a semiconductor film on or above a sapphire substrate by implanting ions from a surface of the semiconductor substrate to form an ion-implanted layer; activating at least a surface of one of the sapphire substrate and the semiconductor substrate from which the ions have been implanted; bonding the surface of the semiconductor substrate and the surface of the sapphire substrate at a temperature of from 50° C. to 350° C.; heating the bonded substrates at a maximum temperature of from 200° C. to 350° C.; and irradiating visible light from a sapphire substrate side or a semiconductor substrate side to the ion-implanted layer of the semiconductor substrate to make the interface of the ion-implanted layer brittle at a temperature of the bonded body higher than the temperature at which the surfaces were bonded, to transfer the semiconductor film to the sapphire substrate.

Abstract: A semiconductor device includes a substrate, a conductive pattern, a side spacer, and an air gap. The substrate includes an interlayer insulating layer and a trench penetrating the interlayer insulating layer. The conductive pattern is disposed within the trench of the substrate. The side spacer is disposed within the trench. The side spacer covers an upper side surface of the conductive pattern. The air gap is disposed within the trench. The air gap is bounded by a sidewall of the trench, the side spacer, and a lower side surface of the conductive pattern. A level of a bottom surface of the conductive pattern is lower than a level of bottom surfaces of the side spacer.

Abstract: A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of the first and second portions of the spacer is spaced apart from a metal silicide layer of the contact plug. Thus reliability of the semiconductor device may be improved. Related fabrication methods are also described.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned adhesion layer is formed on the substrate. A metal layer is deposited on the patterned adhesion layer. An elevated temperature thermal process is applied to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) and a dielectric layer is deposited between SFMFs.

Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.

Abstract: A method of fabricating a semiconductor device includes forming a passivation layer on a least one capping layer of the semiconductor device, and forming an encapsulant layer on the passivation layer. The method further includes patterning the encapsulant layer to expose a portion of the passivation layer and forming a final via opening in the passivation layer. A conductive material is deposited in the final via opening. The method further includes planarizing the conductive material until reaching a remaining portion of the encapsulant layer such that the conductive material is flush with the encapsulant layer and the passivation layer is preserved.