Patents Issued in December 15, 2015
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Patent number: 9214386Abstract: Some embodiments include methods of forming electrically conductive contacts. An opening is formed through an insulative material to a conductive structure. A conductive plug is formed within a bottom region of the opening. A spacer is formed to line a lateral periphery of an upper region of the opening, and to leave an inner portion of an upper surface of the plug exposed. A conductive material is formed against the inner portion of the upper surface of the plug. Some embodiments include semiconductor constructions having a conductive plug within an insulative stack and against a copper-containing material. A spacer is over an outer portion of an upper surface of the plug and not directly above an inner portion of the upper surface. A conductive material is over the inner portion of the upper surface of the plug and against an inner lateral surface of the spacer.Type: GrantFiled: July 1, 2015Date of Patent: December 15, 2015Assignee: Micron Technology, Inc.Inventor: Zengtao T. Liu
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Patent number: 9214387Abstract: A radio frequency (RF) module comprises RF-shielding structure for providing three-dimensional electromagnetic interference shielding with respect to one or more RF devices disposed on the module. The RF-shielding may comprise wirebond structures disposed adjacent to or surrounding an RF device. Two or more intramodule devices may have wirebond structures configured to at least partially block certain types of RF signals disposed between the devices, thereby reducing effects of cross-talk between the devices.Type: GrantFiled: September 27, 2013Date of Patent: December 15, 2015Assignee: Skyworks Solutions, Inc.Inventors: Howard E. Chen, Matthew Sean Read, Anthony James LoBianco, Hoang Mong Nguyen, Guohao Zhang, Dinhphuoc Vu Hoang
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Patent number: 9214388Abstract: Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.Type: GrantFiled: February 28, 2013Date of Patent: December 15, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, Zhengwen Li, Zhijiong Luo, Huilong Zhu
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Patent number: 9214389Abstract: Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry.Type: GrantFiled: April 29, 2014Date of Patent: December 15, 2015Assignee: Micron Technology, Inc.Inventors: Niccolo′ Righetti, Sara Vigano, Emilio Camerlenghi
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Patent number: 9214390Abstract: A semiconductor device and method for forming the same provide a through silicon via (TSV) surrounded by a dielectric liner. The TSV and dielectric liner are surrounded by a well region formed by thermal diffusion. The well region includes a dopant impurity type opposite the dopant impurity type of the substrate. The well region may be a double-diffused well with an inner portion formed of a first material and with a first concentration and an outer portion formed of a second material with a second concentration. The surrounding well region serves as an isolation well, reducing parasitic capacitance.Type: GrantFiled: June 10, 2014Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chi-Yeh Yu
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Patent number: 9214391Abstract: Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having a plurality of microelectronic dies. The individual dies include an integrated circuit and a terminal electrically coupled to the integrated circuit. In one embodiment, the method includes forming an opening in the workpiece in alignment with the terminal. The opening can be a through-hole extending through the workpiece or a blind hole that extends only partially through the substrate. The method continues by constructing an electrically conductive interconnect in the workpiece by depositing a solder material into at least a portion of the opening and in electrical contact with the terminal. In embodiments that include forming a blind hole, the workpiece can be thinned either before or after forming the hole.Type: GrantFiled: September 19, 2008Date of Patent: December 15, 2015Assignee: Micron Technology, Inc.Inventor: Kyle K. Kirby
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Patent number: 9214392Abstract: A method of forming a contact hole includes providing a substrate. A nitrogen-containing dielectric layer, a first material layer, a second material layer, an oxygen-containing dielectric layer and a patterned photoresist layer cover the substrate from bottom to top. Then, the oxygen-containing dielectric layer is etched by taking the second material layer as a first etching stop layer to form a patterned oxygen-containing dielectric layer. Latter, the second material layer is etched by taking the first material layer as a second etching stop layer to form a patterned second material layer. Subsequently, the first material layer is etched by taking the nitrogen-containing dielectric layer as a third etching stop layer to form a patterned first material layer. Finally, the nitrogen-containing dielectric layer is etched until the substrate is exposed.Type: GrantFiled: October 30, 2014Date of Patent: December 15, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
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Surface tension modification using silane with hydrophobic functional group for thin film deposition
Patent number: 9214393Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.Type: GrantFiled: April 2, 2012Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lai Wan Chong, Wen Chu Hsiao, Ying Min Chou, Hsiang Hsiang Ko -
Patent number: 9214394Abstract: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.Type: GrantFiled: August 27, 2014Date of Patent: December 15, 2015Assignee: MICRON TECHNOLOGY, INC.Inventor: Suraj Mathew
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Patent number: 9214395Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.Type: GrantFiled: March 13, 2013Date of Patent: December 15, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Hsiang Hung, Chung-Fu Chang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
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Patent number: 9214396Abstract: A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.Type: GrantFiled: June 3, 2014Date of Patent: December 15, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Stefan Flachowsky, Jan Hoentschel, Gerd Zschaetzsch
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Patent number: 9214397Abstract: A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.Type: GrantFiled: March 7, 2013Date of Patent: December 15, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Bruce B. Doris, Kangguo Cheng, Steven J. Holmes, Ali Khakifirooz, Pranita Kerber, Shom Ponoth, Raghavasimhan Sreenivasan, Stefan Schmitz
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Patent number: 9214398Abstract: A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region. A well pickup region is disposed in the well region, wherein the well pickup region is at a back side of the semiconductor substrate. A through-via penetrates through the semiconductor substrate, wherein the through-via electrically inter-couples the well pickup region and the source/drain region.Type: GrantFiled: September 9, 2013Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jam-Wem Lee
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Patent number: 9214399Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.Type: GrantFiled: July 30, 2014Date of Patent: December 15, 2015Assignee: Efficient Power Conversion CorporationInventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Yanping Ma, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
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Patent number: 9214400Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, an insulating buried layer, and a semiconductor layer, wherein the insulating buried layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the insulating buried layer; adjacent MOSFETs formed in the SOI wafer, wherein each of the adjacent MOSFETs comprises a back gate formed in the semiconductor substrate and a back gate isolation region formed completely under the back gate; and a shallow trench isolation, wherein the shallow trench isolation is formed between the adjacent MOSFETs to isolate the adjacent MOSFETs from each other, wherein a PN junction is formed between the back gate and the back gate isolation region of each of the adjacent MOSFETs. According to embodiments of the present disclosure, a PN junction is formed between the back gate isolation regions of the adjacent MOSFETs.Type: GrantFiled: November 18, 2011Date of Patent: December 15, 2015Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Huilong Zhu, Qingqing Liang, Zhijiong Luo, Haizhou Yin
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Patent number: 9214401Abstract: A display substrate includes a base substrate including a display area and a peripheral area surrounding the display area, a switching element in the display area, a main-test-line in the peripheral area, extending in the second direction and electrically connected with a data line, a sub-test-line in the peripheral area, and a test pad in the peripheral area and electrically connected with the main-test-line and the sub-test-line. The switching element is electrically connected with a gate line extending in a first direction and the data line extending in a second direction crossing the first direction. The sub-test-line is electrically connected with the data line. The sub-test-line is in a different layer from the main-test-line.Type: GrantFiled: June 24, 2014Date of Patent: December 15, 2015Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Dong-Hyun Yoo, Seong-Young Lee, Jae-Won Kim, Hyung-Jun Park
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Patent number: 9214402Abstract: A pressure sensor device includes a gel retainer that is mounted or formed on a substrate. The gel retainer has a cavity and a pressure sensing die is mounted inside the cavity. The die is electrically connected to one or more other package elements. A pressure-sensitive gel material is dispensed into the cavity to cover an active region of the pressure sensing die. A mold compound is applied on an upper surface of the substrate outside of the gel retainer.Type: GrantFiled: January 10, 2014Date of Patent: December 15, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Kee Cheong Fam, Mohd Rusli Ibrahim, Lan Chu Tan
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Patent number: 9214403Abstract: A stacked semiconductor package including a first printed circuit board and a second printed circuit board is provided. The first printed circuit board may include a first surface upon which a first semiconductor chip is mounted and a second surface upon which at least one connecting structure is attached. The first printed circuit board may further include at least one thermal via and a heat sink and the at least one thermal via and the heat sink may be disposed under the first semiconductor chip with the heat sink being disposed between the first surface and the second surface. The second printed circuit board may include a third surface upon which a second semiconductor chip is mounted. The second printed circuit board may be disposed under the first printed circuit board with the at least one connecting structure connecting the first printed circuit board to the second printed circuit board.Type: GrantFiled: May 17, 2013Date of Patent: December 15, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Seok-Chan Lee
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Patent number: 9214404Abstract: A method and apparatus for mounting microelectronic chips to a thermal heat sink. The chips are arranged in a desired configuration with their active faces all facing a common direction and with their active faces defining a common planar surface for all of said chips. A metallic material is applied to the chip, preferably by electroplating to backsides of the chips, the metallic material being electro-formed thereon and making void-free contact with the backsides of the chips.Type: GrantFiled: November 14, 2013Date of Patent: December 15, 2015Assignee: HRL Laboratories, LLCInventors: Alexandros D. Margomenos, Miroslav Micovic
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Patent number: 9214405Abstract: A semiconductor module includes a control board, and a shield plate arranged opposing the control board. A metal first heat dissipating portion is provided on a surface of the control board. A metal second heat dissipating portion is provided on a first surface of the shield plate, opposing the surface of the control board. A dielectric body is arranged between the first heat dissipating portion and the second heat dissipating portion.Type: GrantFiled: January 22, 2014Date of Patent: December 15, 2015Assignee: Toyota Jidosha Kabushiki KaishaInventor: Tadashi Tsukamoto
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Patent number: 9214406Abstract: In an electronic control device, semiconductor modules are disposed in a power region of a substrate, and on a surface of a substrate adjacent to a housing to radiate heat from rear surfaces to the housing through a heat radiation layer. Therefore, a heat radiation performance improves. Further, a first distance from an end surface of a power region corresponding part corresponding to the power region to the substrate is shorter than a second distance from an end surface of a control region corresponding part corresponding to a control region of the substrate to the substrate. Therefore, a closed circuit bridged by parasitic capacitances is formed mainly in an area of the power region and the power region corresponding part. A noise generated from the semiconductor modules is returned to noise sources through the closed circuit without affecting the control region.Type: GrantFiled: December 22, 2014Date of Patent: December 15, 2015Assignee: DENSO CORPORATIONInventors: Tomoaki Yoshimi, Takayuki Uchida
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Patent number: 9214407Abstract: A synthetic diamond heat spreader, the synthetic diamond heat spreader comprising: a synthetic diamond material including a surface layer having a 13C content of less than a natural isotopic abundance (1.1%) and a support layer which is thicker than the surface layer and which has an isotopic abundance of 13C which is closer to the natural isotopic abundance than the surface layer, wherein at least 50% of a thickness of the synthetic diamond material is formed of the support layer; and a non-diamond thermal transfer layer disposed in contact with the surface layer of the synthetic diamond material for transferring heat into the surface layer.Type: GrantFiled: November 19, 2013Date of Patent: December 15, 2015Assignee: ELEMENT SIX TECHNOLOGIES LIMITEDInventor: Daniel Twitchen
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Patent number: 9214408Abstract: A fluid cooled thermal management technique for a high-density composite focal plane array (CPFA) is disclosed. In one embodiment, a high density CFPA assembly includes a plurality of imaging dies mounted on a front surface of a printed wiring board (PWB) and a base plate. The base plate has a substantially matched coefficient of thermal expansion (CTE) to that of the high density CFPA. Further, the high density CFPA is disposed on a front side of the base plate. Furthermore, the base plate has a plurality of integral serpentine fluid flow channels configured to receive and circulate fluid and further configured such that the heat generated by the CFPA is transferred via conduction into the base plate and to the integral serpentine fluid flow channels and to the circulating fluid to dissipate the generated heat.Type: GrantFiled: September 5, 2012Date of Patent: December 15, 2015Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Gerard A. Esposito, Dennis P. Bowler
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Patent number: 9214409Abstract: Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.Type: GrantFiled: March 6, 2013Date of Patent: December 15, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Hyuk Yoo, Dae-Hyun Jang, Yoo-Chul Kong, Kyoung-Sub Shin
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Patent number: 9214410Abstract: Stack packages are provided. The stack package includes a first chip and a second chip. The first chip includes a first chip body, first through electrodes penetrating the first chip body, and an insulation layer disposed on a bottom surface of the first chip body. The second chip includes a second chip body and bumps disposed on a top surface of the second chip body. The first and second chips are vertically stacked such that the bumps penetrate the insulation layer to pierce the first through electrodes and the top surface of the second chip body directly contacts the insulation layer. Related fabrication methods, electronic systems and memory cards are also provided.Type: GrantFiled: April 4, 2014Date of Patent: December 15, 2015Assignee: SK Hynix Inc.Inventors: Jong Hoon Kim, Han Jun Bae
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Patent number: 9214411Abstract: Integrated circuit (IC) devices are provided including: a first multi-layer wiring structure including a plurality of first wiring layers in a first region of a substrate at different levels and spaced apart from one another, and a plurality of first contact plugs between the plurality of first wiring layers and connected to the plurality of first wiring layers; a through-silicon via (TSV) landing pad including a first pad layer in a second region of the substrate at a same level as that of at least one first wiring layer from among the plurality of first wiring layers, and a second pad layer at a same level as that of at least one first contact plug from among the plurality of first contact plugs and contacts the first pad layer; a second multi-layer wiring structure on the TSV landing pad; and a TSV structure that passes through the substrate and is connected to the second multi-layer wiring structure through the TSV landing pad.Type: GrantFiled: October 6, 2014Date of Patent: December 15, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwa Park, Kwang-jin Moon, Suk-Chul Bang, Byung-Iyul Park, Jeong-gi Jin, Tae-seong Kim, Sung-hee Kang
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Patent number: 9214412Abstract: A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.Type: GrantFiled: June 15, 2014Date of Patent: December 15, 2015Assignee: Renesas Electronics CorporationInventors: Katsuhiko Funatsu, Yukihiro Sato, Yuichi Yato, Tomoaki Uno
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Patent number: 9214413Abstract: A semiconductor die is packaged by providing a die assembly that includes a semiconductor die with an active surface and an opposite mounting surface with an attached thermally conductive substrate. The die assembly is mounted on a first surface of a lead frame die flag so that the thermally conductive substrate is sandwiched between the die flag and the semiconductor die. Bonding pads of the die are electrically connected with bond wires to lead frame lead fingers. A mold compound then encapsulates the semiconductor die, bond wires, and thermally conductive substrate. A second surface of the die flag is exposed through the mold compound.Type: GrantFiled: November 23, 2014Date of Patent: December 15, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Zhijie Wang, Zhigang Bai, Aipeng Shu, Yanbo Xu, Huchang Zhang, Fei Zong
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Patent number: 9214414Abstract: A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region.Type: GrantFiled: December 4, 2014Date of Patent: December 15, 2015Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Kazunori Oda, Masaki Yazaki
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Patent number: 9214415Abstract: A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).Type: GrantFiled: February 17, 2014Date of Patent: December 15, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Brian Ashley Carpenter, Osvaldo Jorge Lopez, Juan Alejandro Herbsommer, Jonathan Noquil
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Patent number: 9214416Abstract: A new Power DFN and Power QFN package architecture that accommodates Bump-chip die and other components in cavities on the bottom-side of the matrix leadframe, and the technique is also applicable to laminated substrate packages like the BGA and LGA. The package is especially suited for high speed power compound semiconductor devices like GaN and SiC. The package enables single and multiple power switch configurations, and well controlled paralleling of high speed power die switches. It enables co-packaging of associated components like cascoded switchs, gate drivers, isolators and protection devices, which must be tightly coupled at high switching speeds. The architecture accommodates components on the top-side of the leadframe as well allowing for multi-chip functions with extremely low interconnect inductance and resistance, and higher circuit and power densities.Type: GrantFiled: June 9, 2014Date of Patent: December 15, 2015Inventor: Courtney Furnival
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Patent number: 9214417Abstract: A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.Type: GrantFiled: February 21, 2014Date of Patent: December 15, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Yueh-Se Ho, Hamza Yilmaz, Yan Xun Xue, Jun Lu
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Patent number: 9214418Abstract: A lead frame with a radiator plate on which a semiconductor chip 50 is to be mounted is provided with a radiator plate 30, and a lower surface side lead frame 40 including an upper surface 41 and a lower surface 42. The lower surface side lead frame 40 overlaps and fixes the radiator plate 30 with the lower surface 42 making contact with the radiator plate 30. A through hole 43 piercing the lower surface side lead frame 40 from the upper surface 41 to the lower surface 42 is formed at a position where the lower surface side lead frame 40 overlaps the radiator plate 30, and an opening area of the through hole 43 at the lower surface 42 is larger than an opening area of the through hole 43 at the upper surface 41.Type: GrantFiled: March 2, 2015Date of Patent: December 15, 2015Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Tomohiro Kuroda
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Patent number: 9214419Abstract: A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units.Type: GrantFiled: February 28, 2014Date of Patent: December 15, 2015Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu
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Patent number: 9214420Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.Type: GrantFiled: December 3, 2012Date of Patent: December 15, 2015Assignee: Intel CorporationInventors: Nachiket Raravikar, Daewoong Suh
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Patent number: 9214421Abstract: A semiconductor device and a method of manufacturing the same are provided. A semiconductor device comprises a substrate, a conductive pattern formed on the substrate, and at least a conductive pillar having a predetermined height formed on the conductive pattern. The conductive pillar can be formed under a focus ion beam (FIB) or an electron beam environment. In one embodiment, a diameter of the conductive pillar is no more than 10 ?m.Type: GrantFiled: September 30, 2013Date of Patent: December 15, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ming Tsai, Yi-Hsuan Huang, Yueh-Ping Chung, Ya-Hui Lu
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Patent number: 9214422Abstract: A semiconductor apparatus includes a first wiring substrate, a second wiring substrate positioned above the first wiring substrate, multiple connection terminals provided between the first wiring substrate and the second wiring substrate and configured to electrically connect the first wiring substrate and the second wiring substrate, an electronic component provided on at least one of the first wiring substrate and the second wiring substrate. The multiple connection terminals include a signal terminal and ground terminals provided on both sides of the signal terminal. The signal terminal and the ground terminals have side surfaces that face each other. The signal terminal and the ground terminals are adjacently arranged, so that intervals between the side surfaces of the signal terminal and the ground terminals are constant from a plan view.Type: GrantFiled: January 31, 2014Date of Patent: December 15, 2015Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Tomoharu Fujii
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Patent number: 9214423Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.Type: GrantFiled: February 6, 2014Date of Patent: December 15, 2015Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Ali Salih, Chun-Li Liu, Gordon M. Grivna
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Patent number: 9214424Abstract: A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.Type: GrantFiled: April 20, 2012Date of Patent: December 15, 2015Assignee: Infineon Technologies Austria AGInventors: Matthias Stecher, Markus Menath, Andreas Zankl, Anja Gisslbl
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Patent number: 9214425Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.Type: GrantFiled: August 1, 2014Date of Patent: December 15, 2015Assignee: Tessera, Inc.Inventors: Ilyas Mohammed, Belgacem Haba, Cyprian Emeka Uzoh
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Patent number: 9214426Abstract: Methods and apparatuses for reducing excess on die capacitance. The method couples a first die pad to a first via. The method couples a second die pad to a second via. The method couples a first inductor to the first die pad and the second via. The method couples a second inductor to the second die pad and the first via.Type: GrantFiled: July 11, 2014Date of Patent: December 15, 2015Assignee: QUALCOMM IncorporatedInventors: Siamak Fazelpour, Priyatharshan Pathmanathan, John Stephen Loffink
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Patent number: 9214427Abstract: Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.Type: GrantFiled: May 13, 2015Date of Patent: December 15, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Cathryn J. Christiansen, Andrew H. Norfleet, Kirk D. Peterson, Andrew A. Turner
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Patent number: 9214428Abstract: A semiconductor device includes a copper-containing post overlying and electrically connected to a bond pad region. The semiconductor device further includes a protection layer on a surface of the copper-containing post, where the protection layer includes manganese.Type: GrantFiled: December 19, 2013Date of Patent: December 15, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Shi Liu, Chen-Hua Yu
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Patent number: 9214429Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.Type: GrantFiled: December 5, 2013Date of Patent: December 15, 2015Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: John H. Zhang, Hsueh-Chung Chen, Lawrence A. Clevenger, Yann Mignot, Carl Radens, Richard Stephen Wise, Yannick Loquet, Yiheng Xu
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Patent number: 9214430Abstract: Provided are a semiconductor device in which abrasive grain marks are formed in a surface of a semiconductor substrate, a dopant diffusion region has a portion extending in a direction which forms an angle included in a range of ?5° to +5° with a direction in which the abrasive grain marks extend, and the dopant diffusion region is formed by diffusing a dopant from a doping paste placed on one surface of the semiconductor substrate; and a method for manufacturing the semiconductor device.Type: GrantFiled: November 7, 2012Date of Patent: December 15, 2015Assignee: Sharp Kabushiki KaishaInventor: Yasushi Funakoshi
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Patent number: 9214431Abstract: Magnetic coupling of noise sources can have a negative impact on the net performance of sensitive circuits. A magnetic shielding loop can advantageously minimize magnetic coupling associated with a circuit on an integrated circuit (IC) by including on-chip components, off-chip components, and interface components connecting the on-chip and off-chip components. The components can include conductive paths and contact pads on a die, package, and printed circuit board. The magnetic shielding loop magnetically isolates at least one of input terminals and noise-generating elements of the circuit.Type: GrantFiled: May 25, 2006Date of Patent: December 15, 2015Assignee: QUALCOMM IncorporatedInventor: Manolis Terrovitis
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Patent number: 9214432Abstract: A semiconductor module has a carrier, a semiconductor chip mounted on the carrier, a bond wire, a module housing, and a first sound absorber. The module housing has a housing side wall. The bond wire is arranged in the module housing. At least a section of the first sound absorber is arranged between the semiconductor chip and the housing side wall.Type: GrantFiled: September 29, 2014Date of Patent: December 15, 2015Assignee: Infineon Technologies AGInventors: Guido Boenig, Olaf Hohlfeld
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Patent number: 9214433Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.Type: GrantFiled: May 21, 2013Date of Patent: December 15, 2015Assignee: XILINX, INC.Inventors: Qi Xiang, Xiao-Yu Li, Cinti X. Chen, Glenn O'Rourke
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Patent number: 9214434Abstract: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.Type: GrantFiled: September 4, 2013Date of Patent: December 15, 2015Inventors: Jin Young Kim, Doo Hyun Park, Seung Jae Lee
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Patent number: 9214435Abstract: Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.Type: GrantFiled: May 21, 2012Date of Patent: December 15, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Mukta G. Farooq, Troy L. Graves-Abe, Spyridon Skordas, Kevin R. Winstel