Patents Issued in February 16, 2016
  • Patent number: 9262162
    Abstract: A register file is provided. The register file includes a plurality of registers configured to form at least one register cluster, each of the registers being configured to have a virtual index defined for each cluster and a physical index defined for each register, and an index converting unit configured to convert the virtual index to the physical index.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bernhard Egger, Dong-Hoon Yoo, Won-Sub Kim
  • Patent number: 9262163
    Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventors: Tsvika Kurts, Ofer Levy, Itamar Kazachinsky, Gabi Malka, Zeev Sperber, Jason W. Brandt
  • Patent number: 9262164
    Abstract: A digital system is provided. The digital system includes an execution unit, a level-zero (L0) memory, and an address generation unit. The execution unit is coupled to a data memory containing data to be used in operations of the execution unit. The L0 memory is coupled between the execution unit and the data memory and configured to receive a part of the data in the data memory. The address generation unit is configured to generate address information for addressing the L0 memory. Further, the L0 memory provides at least two operands of a single instruction from the part of the data to the execution unit directly, without loading the at least two operands into one or more registers, using the address information from the address generation unit.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: February 16, 2016
    Assignee: SHANGHAI XIN HAO MICRO ELECTRONICS CO. LTD.
    Inventors: Kenneth Chenghao Lin, Haoqi Ren
  • Patent number: 9262165
    Abstract: A vector processor includes an instruction fetching unit configured to acquire an instruction, a decoding/issuing unit configured to decode the instruction and issuing the instruction, an operation group configured to include a plurality of operation units and a register configured to store the element data column, wherein the plurality of operation units include a first operation unit processes a first type instruction and a second operation unit processes a second type instruction and the first type instruction; and when a plurality of divided instructions, for which the element data of an instruction to be issued has been divided, are processed by the second operation unit, in a case where the second type instruction is not present, the decoding/issuing unit issues the divided instructions, and in a case where the second type instruction is present, the decoding/issuing unit issues the instruction to be issued without performing division.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: February 16, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Hiroshi Hatano, Koichi Suzuki
  • Patent number: 9262166
    Abstract: Various embodiments are directed to a heterogeneous processor architecture comprised of a CPU and a GPU on the same processor die. The heterogeneous processor architecture may optimize source code in a GPU compiler using vector strip mining to reduce instructions of arbitrary vector lengths into GPU supported vector lengths and loop peeling. It may be first determined that the source code is eligible for optimization if more than one machine code instruction of compiled source code under-utilizes GPU instruction bandwidth limitations. The initial vector strip mining results may be discarded and the first iteration of the inner loop body may be peeled out of the loop. The type of operands in the source code may be lowered and the peeled out inner loop body of source code may be vector strip mined again to obtain optimized source code.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: February 16, 2016
    Assignee: INTEL CORPORATION
    Inventors: Xiaozhu Kang, Biju George, Ken Lueh
  • Patent number: 9262167
    Abstract: A system and method for testing whether a computer processor is capable of executing a requested instruction set. The system includes a computer processor configured to receive an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implement the encoded conditional branch instruction unconditionally, based on underlying hardware architecture of the computer processor. The Method for testing whether a computer processor is capable of executing a requested instruction set, the method including, receiving an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implementing the encoded conditional branch instruction unconditionally, based on underlying hardware architecture of the computer processor.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jose E. Garza, Stephen J. Hobson
  • Patent number: 9262168
    Abstract: A system and method for testing whether a computer processor is capable of executing a requested instruction set. The system includes a computer processor configured to receive an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implement the encoded conditional branch instruction unconditionally, based on underlying hardware architecture of the computer processor. The Method for testing whether a computer processor is capable of executing a requested instruction set, the method including, receiving an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implementing the encoded conditional branch instruction unconditionally, based on underlying hardware architecture of the computer processor.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jose E. Garza, Stephen J. Hobson
  • Patent number: 9262169
    Abstract: Embodiments relate to branch prediction table install source tracking. An aspect includes a system for branch prediction table install source tracking. The system includes memory configured to store instructions accessible by a processor. The processor includes a branch target buffer, where the processor is configured to perform a method. The method includes receiving at the branch target buffer a request to install a branch target buffer entry corresponding to a branch instruction for branch prediction, and identifying a source of the request as an install source of the branch target buffer entry. The method further includes storing an install source identifier in the branch target buffer based on the install source.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: James J. Bonanno, Brian R. Prasky
  • Patent number: 9262170
    Abstract: Reclaiming checkpoints in a system in an order that differs from the order when the checkpoints are created. Reclaiming the checkpoints includes: creating one or more checkpoints, each of which having an initial state using system resources and holding the checkpoints state; identifying the completion of all the instructions associated with the checkpoint; reassigning all the instructions associated with the identified checkpoint to an immediately preceding checkpoint; and freeing the resources associated with the identified checkpoint. The checkpoint is created when the instruction that is checked is a conditional branch having a direction that cannot be predicted with a predetermined confidence level.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anil Krishna, Ganesh Balakrishnan, Gordon B. Bell
  • Patent number: 9262171
    Abstract: Systems and methods for identification of dependent instructions on speculative load operations in a processor. A processor allocates entries of a unified pick queue for decoded and renamed instructions. Each entry of a corresponding dependency matrix is configured to store a dependency bit for each other instruction in the pick queue. The processor speculates that loads will hit in the data cache, hit in the TLB and not have a read after write (RAW) hazard. For each unresolved load, the pick queue tracks dependent instructions via dependency vectors based upon the dependency matrix. If a load speculation is found to be incorrect, dependent instructions in the pick queue are reset to allow for subsequent picking, and dependent instructions in flight are canceled. On completion of a load miss, dependent operations are re-issued. On resolution of a TLB miss or RAW hazard, the original load is replayed and dependent operations are issued again from the pick queue.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: February 16, 2016
    Assignee: Oracle America, Inc.
    Inventors: Robert T. Golla, Matthew B. Smittle, Xiang Shan Li
  • Patent number: 9262172
    Abstract: A method for rolling back speculative threads in symmetric-multiprocessing (SMP) environments is disclosed. In one embodiment, such a method includes detecting an aborted thread at runtime and determining whether the aborted thread is an oldest aborted thread. In the event the aborted thread is the oldest aborted thread, the method sets a high-priority request for allocation to an absolute thread number associated with the oldest aborted thread. The method further detects that the high-priority request is set and, in response, modifies a local allocation token of the oldest aborted thread. The modification prompts the oldest aborted thread to retry a work unit associated with its absolute thread number. The oldest aborted thread subsequently initiates the retry of a successor thread by updating the successor thread's local allocation token. A corresponding apparatus and computer program product are also disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Martin Ohmacht, Raul E. Silvera, Mark G. Stoodley, Kai-Ting A. Wang
  • Patent number: 9262173
    Abstract: A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values to be written to those address location of subsequent potential lock release instruction are compared to the address loaded from by the lock instruction and the value load by the lock instruction. If the addresses and values match, it is determined that the lock release instruction matches the lock instruction. A prediction entry stores a reference to the lock instruction, such as a last instruction pointer (LIP), and an associated value to represent the lock instruction is to be elided upon subsequent detection, if it is determined that the lock release instruction matches the lock instruction.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventors: Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan
  • Patent number: 9262174
    Abstract: One embodiment sets forth a technique for dynamically mapping addresses to banks of a multi-bank memory based on a bank mode. Application programs may be configured to perform read and write a memory accessing different numbers of bits per bank, e.g., 32-bits per bank, 64-bits per bank, or 128-bits per bank. On each clock cycle an access request may be received from one of the application programs and per processing thread addresses of the access request are dynamically mapped based on the bank mode to produce a set of bank addresses. The bank addresses are then used to access the multi-bank memory. Allowing different bank mappings enables each application program to avoid bank conflicts when the memory is accesses compared with using a single bank mapping for all accesses.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: February 16, 2016
    Assignee: NVIDIA Corporation
    Inventors: Michael Fetterman, Stewart Glenn Carlton, Douglas J. Hahn, Rajeshwaran Selvanesan, Shirish Gadre, Steven James Heinrich
  • Patent number: 9262175
    Abstract: Systems, methods, and apparatus for use with at least one virtual agent. In some embodiments, at least one processor is programmed to store a receipt for an interaction between the at least one virtual agent and one or more users, wherein the receipt comprises at least some information provided by the one or more users to the at least one virtual agent during the interaction.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: February 16, 2016
    Assignee: Nuance Communications, Inc.
    Inventors: Timothy Lynch, Kenneth S. Harper, Carey Radebaugh
  • Patent number: 9262176
    Abstract: Arrangements for executing enterprise resource planning software in a plurality of modes are presented. A graphical user interface may allow an administrator to select from the plurality of modes for executing the enterprise resource planning software, such as a test mode and a production mode. A selection of one of the modes may be received. The selected mode may be linked with a particular initialization file that is used to initialize the enterprise resource software. The enterprise resource planning software may be initialized and run using the selected initialization file.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: February 16, 2016
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Steven M. Fillipi, Joseph Michael Guerra
  • Patent number: 9262177
    Abstract: Embodiments of the present invention provide a method for initializing a plurality of processors of a multi-processor system by executing, at each respective processor of the plurality of processors, at least a portion of local initialization code stored on the respective processor. Receiving, at a designated processor of the plurality of processors, external initialization code stored in external memory, wherein the remainder of the plurality of processors do not have access to the external initialization code stored in external memory. Determining, the designated processor, send at least a portion of the external initialization code to a processor of the remainder of the plurality of processors.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Van H. Lee, David D. Sanner, Thi N. Tran
  • Patent number: 9262178
    Abstract: Methods, systems and computer program products are disclosed for enhanced system boot processing that is faster to launch an operating system, as certain devices such as user input hardware devices may not be initialized unless it is determined that a user-interruption to the boot process is likely. That is, although an interface for the devices is exposed, no initialization occurs unless a call to the interface occurs. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventors: Michael A. Rothman, Vincent J. Zimmer, Mark S. Doran, Michael D. Kinney
  • Patent number: 9262179
    Abstract: Mapping logic information associating a particular type of input with a particular response may be stored in memory. Data including information regarding a display of the host device may be received. Such information may be used to identify multiple descriptions of the host device display. Each description is mapped to a response based on the stored mapping logic. For example, a status bar may be used by the host device to show status updates. The map allows for a different type of response to status updates on the client device, such as a translucent pop-up window. Instructions may be generated for the client device, such that the client device response to input information is based on the mapped description.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: February 16, 2016
    Assignee: HOPTO INC.
    Inventor: Robert W. Currey
  • Patent number: 9262180
    Abstract: A computer implemented method and apparatus for recommending product features in a software application in real time comprising analyzing an object to detect at least one issue to be addressed in the object; identifying at least one user action taken to address the at least one issue in the object; accessing a recommendations library to find at least one recommendation to address the at least one issue in the object; and displaying the at least one recommendation.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: February 16, 2016
    Assignee: ADOBE SYSTEMS INCORPORATED
    Inventors: Anand M. Menon, Gaurav Singh, Anuj Mittal
  • Patent number: 9262181
    Abstract: A computer program product for process allocation is configured to determine a set of two or more processes of a plurality of processes that share at least one resource in a multi-node system, wherein each of the set of two or more processes is running on different nodes of the multi-node system. The program code can be configured to calculate a value based on a weight of the resource and frequency of access of the resource by each process. The program code can be configured to determine a pair of processes of the set of processes having a greatest sum of calculated values by resource. The program code can be configured to allocate a first process of the pair of processes from a first node in the multi-node system to a second node in the multi-node system that hosts a second process of the pair of processes.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Neil Anthony Campbell, Chaitanya Mangla
  • Patent number: 9262182
    Abstract: A method for dynamically modifying a characteristic for an electronic device. The method includes activating by a processor a first profile having a first characteristic setting and a first state for an input/output (IO) device. Once the first profile is activated, receiving an input by a sensor and communicating the input to the processor. The method then includes activating by the processor a second profile having a second characteristic setting and a second state for the IO device. The second profile modifies a component of the IO device to include a second characteristic setting and a second state.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: February 16, 2016
    Assignee: Apple Inc.
    Inventors: Christopher T. Mullens, Jesse Michael Devine, Marco Sebastiani, Nima Parivar
  • Patent number: 9262183
    Abstract: Individual datasets are accessed using an application programming interface (API). Multiple APIs may be combined into a composite API that allows a user to access multiple datasets using a single query. The composite API may be designed to provide a simpler way to consume information from multiple datasets in response to a particular scenario or problem. The composite API may comprise multiple levels of intermediate APIs that call on each other to access desired datasets. A user may select the datasets that the composite API accesses and/or the composite API may require certain specific datasets. The composite API may be offered for sale or use by other users via a website, such as a data market.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: February 16, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Christian Liensberger, Roger Mall, Piotr Milosz Puszkiewicz
  • Patent number: 9262184
    Abstract: An OS on a virtual computer at the (n+m)-th stage (n and m represent natural numbers) is caused to recognize a device driver that runs on an OS on the n-th stage virtual computer. Specifically, a shared region is generated in a memory, and the OS at the second stage is caused to recognize, in a pass-through manner, the device driver that runs on the OS at the second stage.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: February 16, 2016
    Assignee: HITACHI, LTD.
    Inventors: Sachie Tajima, Hitoshi Ueno
  • Patent number: 9262185
    Abstract: A dynamic document template having static data, dynamic data, and/or procedural statements may be called by an application on a server. The dynamic document template is separate from the application program and is processed to form an interim script, which is then executed by a host computer system. The script generates document records in HTML or XML format that are output to a document. The data and procedural statements in the dynamic document template may be distinguished through interpreting mark-up language surrounding the data and procedural statements. The dynamic document templates execute in a separate namespace from the application and preserve the state of data in the application. A given application may call more than one dynamic document template to generate different portions of the output document. Additionally, the dynamic document templates may be replaced with new templates without affecting the application.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: February 16, 2016
    Assignee: Unisys Corporation
    Inventors: Michael J. Hill, John C. Horton
  • Patent number: 9262186
    Abstract: Provided is an code rearranger and method for a virtual machine that uses a just-in-time-compiler (JITC) to manage a location of machine code stored in a code cache. The apparatus may rearrange consecutively-executable machine codes from among those stored in the code cache to be placed successively.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: February 16, 2016
    Assignees: Samsung Electronics Co., Ltd., SNU R&DB Foundation
    Inventors: Hyeong-Seok Oh, Hyung-Kyu Choi, Dong-Heon Jung, Soo-Mook Moon, Kue-Hwan Sihn
  • Patent number: 9262187
    Abstract: An extension point virtualization system uses operating system-provided reparse points to provide minimal extension point registration. Reparse points preserve application isolation while removing the scale problem of writing custom extension point proxies for each extension point. Instead, the system can use a single file system filter that generically handles application virtualization reparse points, and store reparse point data for extension points that need redirection. Many extension points can be handled by redirecting the operating system from a typical location for an application resource to a virtualized safe location for the application resource. Thus, the system simplifies the process of handling new extension points by allowing an application virtualization system to simply register new locations that should be handled with reparse points and to then handle registered locations generically.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 16, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: John M. Sheehan
  • Patent number: 9262188
    Abstract: Techniques are disclosed for managing assets, such as virtual assets, in a computing system implemented with distributed virtual infrastructure. In one example, a method comprises the following steps. Operational information associated with a plurality of virtual assets in a data center is obtained in a trusted manner. The data center is implemented via a distributed virtual infrastructure. At least a portion of the operational information for at least a portion of the plurality of virtual assets in the data center is reported. The operational information reported is operational information pertaining to one or more virtual assets that the data center provides for a tenant of the data center. The obtaining and reporting steps are performed by at least one processing device operating as a virtual asset manager operatively coupled to the distributed virtual infrastructure.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: February 16, 2016
    Assignee: EMC Corporation
    Inventors: Ziye Yang, Chenhui Fan, Lintao Wan, Qiyan Chen, Stephen Todd
  • Patent number: 9262189
    Abstract: A method is provided for use in a system that includes a host computing machine configured to implement a virtualization intermediary and that includes a physical storage adapter, the configures a virtual machine (VM) and a virtual function (VF) to support IO operations to physical storage through a direct IOV path to the VF of the physical storage adapter, the method comprises: creating by the virtualization intermediary mapping information that includes a first mapping between virtual disks and physical regions of physical storage and that includes a second mapping between virtual disks and virtual disk addresses; transmitting the mapping information from the virtualization intermediary over the physical storage adapter from a physical function (PF) of the physical storage adapter to the VF; associating a virtual port with the mapping information within the virtualization intermediary; binding the virtual port to the VF; communicating virtual disk addresses indicated within the second mapping within the tra
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 16, 2016
    Assignee: VMware, Inc.
    Inventors: Edward J. Goggin, Hariharan Subramanian, Sanjana Aswani
  • Patent number: 9262190
    Abstract: The disclosed embodiments illustrate methods and systems for managing virtual machines in a distributed computing environment. The method includes determining an estimated execution time for each job type in one or more jobs received from users and subscribing to virtual machines from the distributed computing environment to execute jobs of each type. The virtual machines are subscribed based on service level agreement (SLA) terms, quality of service (QoS) metrics, and/or the estimated execution time. Further, an actual job execution time for each job executed on an associated subscribed virtual machine is monitored. Thereafter, one or more under-performing virtual machines are identified based on the actual execution time, the estimated execution time, and a tolerance value for each type of job. The one or more under-performing virtual machines are released, while a new set of virtual machines are re-subscribed, such that the SLA terms and the QoS metrics are met.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: February 16, 2016
    Assignee: Xerox Corporation
    Inventors: Barry G Gombert, Lee C Moore, Francisco M Valeriano
  • Patent number: 9262191
    Abstract: A method, an apparatus, and a system for processing a service flow, which belong to the field of communications. Correspondence between a service application attribute and a service application identifier is preconfigured on an NSP board so that after a service flow carrying the service application attribute is received, the service application identifier of the service flow may be determined, which service application corresponding to a service flow may be known according to the service application identifier corresponding to the service flow, and when a plurality of service applications is deployed on an NSP at the same time, a service flow can be correctly sent to a virtual machine of a corresponding service application for service processing.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: February 16, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yungui Wang, Fuqing Sun, Xiaohua Yang, Wei E, Jun Guo
  • Patent number: 9262192
    Abstract: Systems and techniques are described for allocating data store queues to virtual machines. A described technique includes allocating a respective queue to each of a plurality of threads, wherein the queue is configured to queue data requests from the respective thread and for a first data store, determining, for each of a plurality of threads, a respective maximum quantity of pending requests for the thread, wherein a quantity of pending requests sent from the respective queue to the first data store is equal to the maximum quantity of pending requests determined for the thread, determining, for each of the threads, a respective current quantity of operations per second, determining, for each of one or more first threads in the plurality of threads, a respective updated quantity of pending requests, and adjusting, for each first thread, the quantity of pending requests of the first thread sent to the first data store.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 16, 2016
    Assignee: VMware, Inc.
    Inventors: Ajay Gulati, Sachin Manpathak, Mustafa Uysal, Luis Useche
  • Patent number: 9262193
    Abstract: A multi-tier platform-as-a-service (PaaS) deployment reduced to a single-tier architecture for development is disclosed. A method of the disclosure includes mapping multiple tiers of a PaaS system to a consolidated environment executable on a virtual machine (VM), wherein networking stacks of the VM maintain a separation between the multiple tiers in the consolidated environment, and providing the consolidated environment as a development instance of the PaaS system for execution on the VM, the consolidated environment facilitating testing of code changes to the PaaS system.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: February 16, 2016
    Assignee: Red Hat, Inc.
    Inventors: Matthew Hicks, Michael P. McGrath, Daniel C. McPherson
  • Patent number: 9262194
    Abstract: Apparatus, systems, and methods may operate to emulate a virtual device with bidirectional communication capability using a hypervisor. A virtual machine, started by the hypervisor, is capable of receiving hypervisor information from, and transmitting virtual machine information to the hypervisor via the bidirectional communication capability. Further activity may include detecting the existence of the hypervisor information by detecting a logical connection of the virtual device, and masking the existence of the virtual device from a virtual machine user inside the virtual machine. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: February 16, 2016
    Assignee: APPLE INC.
    Inventor: Gosukonda Naga Venkata Satya Sudhakar
  • Patent number: 9262195
    Abstract: A system and method for waking hibernating virtual machines (VMs) are disclosed. In particular, a host operating system (OS) may decide to wake a hibernating VM in response to a message received by the host, such as an incoming networking packet, a message generated by an external event (e.g., a hardware device fault, an interrupt, etc.), etc. In accordance with one embodiment, the decision whether to wake a hibernating VM may be based on a sender of the message.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: February 16, 2016
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Dor Laor
  • Patent number: 9262196
    Abstract: A method and related apparatus and planner are provided. The method comprises receiving information about relationship of activation items in a plurality of virtual machines as well as information including activation item descriptive parameters. In addition, the method comprises of steps of optimizing an activation order of the activation items in said virtual machines according to said relationship among the activation items and generating an activation logical file according to the optimized activation order and said activation item descriptive parameters.
    Type: Grant
    Filed: January 5, 2014
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Xing Jin, Le He, Wu Yu Hui, Qing Bo Wang, Bao Hua Cao
  • Patent number: 9262197
    Abstract: Methods and systems for I/O acceleration using an I/O accelerator device on a virtualized information handling system include pre-boot configuration of first and second device endpoints that appear as independent devices. After loading a storage virtual appliance that has exclusive access to the second device endpoint, a hypervisor may detect and load drivers for the first device endpoint. The storage virtual appliance may then initiate data transfer I/O operations using the I/O accelerator device. The data transfer operations may be read or write operations to a storage device that the storage virtual appliance provides access to. The I/O accelerator device may use direct memory access (DMA).
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: February 16, 2016
    Assignee: Dell Products L.P.
    Inventors: Gaurav Chawla, Robert Wayne Hormuth, Shyamkumar T. Iyer, Duk M. Kim
  • Patent number: 9262198
    Abstract: A host computer has one or more physical central processing units (CPUs) that support the execution of a plurality of containers, where the containers each include one or more processes. Each process of a container is assigned to execute exclusively on a corresponding physical CPU when the corresponding container is determined to be latency sensitive. The assignment of a process to execute exclusively on a corresponding physical CPU includes the migration of tasks from the corresponding physical CPU to one or more other physical CPUs of the host system, and the directing of task and interrupt processing to the one or more other physical CPUs. Tasks of the process corresponding to the container are then executed on the corresponding physical CPU.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: February 16, 2016
    Assignee: VMware, Inc.
    Inventors: Haoqiang Zheng, Lenin Singaravelu, Shilpi Agarwal, Daniel Michael Hecht, Garrett Smith
  • Patent number: 9262199
    Abstract: A system and method for reordering storage levels in a virtualized environment includes identifying a virtual machine (VM) to be transitioned and determining a new storage level order for the VM. The new storage level order reduces a VM live state during a transition, and accounts for hierarchical shared storage memory and criteria imposed by an application to reduce recovery operations after dynamic resource allocation actions. The new storage level order recommendation is propagated to VMs. The new storage level order applied in the VMs. A different storage-level order is recommended after the transition.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: February 16, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Claris Castillo, Canturk Isci
  • Patent number: 9262200
    Abstract: A method for provisioning a virtualized resource includes directing, by a provisioning machine, a server-executed hypervisor to provision a virtual machine. The provisioning machine directs generation of an organizational unit within a first organizational unit within a multi-tenant directory service separated from a second organizational unit in the multi-tenant directory service by a firewall. The provisioning machine associates the virtual machine with the first organizational unit. The provisioning machine establishes at least one firewall rule on the virtual machine restricting communications to the virtual machine to communications from explicitly authorized machines, which including at least one other machine within the organizational unit. The provisioning machine receives a request to provision a virtualized resource for at least one user. The provisioning machine updates data associated with the organizational unit to include an identification of the at least one user.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: February 16, 2016
    Assignee: IndependenceIT, Inc.
    Inventors: Charles F. Buck, Jason A. Shivok
  • Patent number: 9262201
    Abstract: Methods, apparatuses, and computer program products for performing collective operations on a hybrid distributed processing system are provided. Embodiments include determining by at least one task that a parent of the task has failed to send the task data through the tree topology; and determining whether to request the data from a grandparent of the task or a peer of the task in the same tier in the tree topology; and if the task requests the data from the grandparent, requesting the data and receiving the data from the grandparent of the task through the second networking topology; and if the task requests the data from a peer of the task in the same tier in the tree, requesting the data and receiving the data from a peer of the task through the second networking topology.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Archer, James E. Carey, Matthew W. Markland, Philip J. Sanders
  • Patent number: 9262202
    Abstract: A method, computer program product, and system for performing a hybrid dependency analysis is described. According to an embodiment, a method may include computing, by one or more computing devices, one or more dynamic hints based on a finite set of executions of a computer program. The method may further include performing, by the one or more computing devices, a hybrid dependence analysis of one or more statements of the computer program.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventor: Omer Tripp
  • Patent number: 9262203
    Abstract: A computerized method, computer system, and computer program product for processing an execution request within different computing environments. Execution requests and generated reference information are forwarded to the different computing environments, where the requests are executing using the reference information. Results of the processed execution requests are collected from the different computing environments. The results are compared to identify whether a discrepancy exists giving indication of a software or hardware error.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Utz Bacher, Hai Huang, Brian Peterson, Stefan Raspl
  • Patent number: 9262204
    Abstract: Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: February 16, 2016
    Assignee: THROUGHPUTER, INC.
    Inventor: Mark Henrik Sandstrom
  • Patent number: 9262205
    Abstract: Techniques are disclosed for qualified checkpointing of a data flow model having data flow operators and links connecting the data flow operators. A link of the data flow model is selected based on a set of checkpoint criteria. A checkpoint is generated for the selected link. The checkpoint is selected from different checkpoint types. The generated checkpoint is assigned to the selected link. The data flow model, having at least one link with no assigned checkpoint, is executed.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Eric A. Jacobson, Yong Li, Shyam R. Mudambi, Xiaoyan Pu
  • Patent number: 9262206
    Abstract: When executed, a transaction-begin instruction specifies an initial value for a transaction-count-to-completion (CTC) value for a transaction. The initial value indicates a predicted duration of the transaction. The CTC value may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. The adjusted CTC value indicates how far the transaction is from completion. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Cain, III, Maged M. Michael, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9262207
    Abstract: When executed, a transaction-begin instruction specifies an initial value for a transaction-count-to-completion (CTC) value for a transaction. The initial value indicates a predicted duration of the transaction. The CTC value may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. The adjusted CTC value indicates how far the transaction is from completion. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Cain, III, Maged M. Michael, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9262208
    Abstract: Distributed execution of commands and scripts may comprise a script execution manager having access to a library of executable objects comprising at least one or more of commands or scripts or combination of commands and scripts. A script execution console may be operable to present a graphical user interface for selecting an executable object from the library to execute and for selecting one or more managed computers, on which to execute the selected executable object. The script execution console may be further operable to present a dynamically updated collation of results from execution of the selected executable object. One or more script execution agents may be operable to run on the selected respective one or more managed computers and further operable to communicate with the script execution manager.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Shang Q. Guo, Ramesh S. Palakodeti, Rajeev Puri, Daniela Rosu, Cashchakanithara Venugopal, Frederick Y. Wu, Sai Zeng
  • Patent number: 9262209
    Abstract: In an embodiment, a scheduler coordinates timings at which cores execute processes, for any two sequential processes to consecutively be executable. The processes are executed in order scheduled by the scheduler by concentrating on a specific core processes obstructing the consecutive execution such as an external interrupt and an internal interrupt. The scheduler does not always cause processes of another application to be executed during all standby time periods while the scheduler determines whether a length of a standby time period is shorter than a predetermined value, and does not cause any process of the other application to be executed when the length is shorter than that.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 16, 2016
    Assignee: Fujitsu Limited
    Inventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara
  • Patent number: 9262210
    Abstract: A method, computer program product and system for workload management for an Extract, Transform, and Load (ETL) system. A priority of each workload in a set of workloads is determined using a priority rule. In response to determining that the priority of a workload to be checked has a highest priority, it is indicated that the workload has the highest priority. It is determined whether at least one logical resource representing an ETL metric is available for executing the workload. In response to determining that the workload has the highest priority and that the at least one logical resource is available, it is determined that the workload is runnable.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Brian K. Caufield, Yong Li, Xiaoyan Pu
  • Patent number: 9262211
    Abstract: Provided is an apparatus for software migration between devices in a mobile environment. The software migration apparatus may include a policy manager configured to select a migration method for target software according to a migration environment, and a migration manager configured to perform migration of the target software according to the migration method. In addition, provided herein is a software migration method which is performed in a mobile environment. The software migration method may involve analyzing a current migration environment, selecting a migration method according to the analyzed current migration environment, and performing the migration of the target software.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Dok Mo, Sung-Min Lee