Abstract: The provisioning of a volume that has multiple tiers corresponding to different trait sets. The volume to be provisioned is identified along with multiple tiers that are to be in the volume. For each of the tiers that are to be provisioned within the volume, a corresponding trait set is identified as to be applied to each tier. This corresponding trait set may be based on underlying storage systems that are available at the time of provisioning, or which are anticipated to be available. The volume is then caused to be provisioned with the corresponding tiers having the corresponding trait sets. Also, the provisioning of a file, which is determined to have one or more storage traits. Based on these storage traits, the file is then caused to be assigned to an appropriate tier.

Abstract: A data transfer device includes a FIFO memory and a control unit which obtains a data amount of the FIFO memory to control the FIFO memory and outputs a selection signal corresponding to the obtained data amount of the FIFO memory. An output data generation unit generates output data including either one of the second output data and an interpolation data selected based on the selection signal, and a first output data stored in a frame memory.

Abstract: A method for data storage in a memory that includes multiple analog memory cells, includes defining, based on a characteristic of the memory cells, an uneven wear leveling scheme that programs and erases at least first and second subsets of the memory cells with respective different first and second Programming and Erasure (P/E) rates. Data is stored in the memory in accordance with the uneven wear leveling scheme.

Abstract: In at least one embodiment, a data storage system includes a non-volatile memory array, such as a flash memory array, and a controller coupled to the memory array. The controller records, for each of a plurality of valid pages in the memory array, a respective indication of a dwell time of each valid page.

Abstract: Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device.

Abstract: A system including a processor, a memory controller, and a flash memory module. The processor is configured to generate a request to retrieve information corresponding to an address. The memory controller module includes a cache memory configured to store information, and a cache control logic module configured to determine whether the cache memory stores the information corresponding to the address, if the cache memory stores the information corresponding to the address, retrieve the information from the cache memory and provide the information to the processor, and if the cache memory does not store the information corresponding to the address, generate a flash memory read request based on the address. The flash memory module is configured to, in response to receiving the flash memory read request, provide the information corresponding to the address to the memory controller module.

Abstract: The present invention is directed to a method for increasing the operational lifetime of a flash memory device, wherein, the method comprises varying the operating parameters of the flash memory device over the lifetime of the flash memory device. The advantage of providing a method which varies the operating parameters of a flash memory device is that the operational lifetime of the flash memory device will be increased. Relatively low voltages and relatively short voltage periods may be used initially to write to, read from and erase the flash cells in the flash memory device. As time passes, the flash cells in the flash memory device will begin to degrade and it will be necessary to increase the voltage and the period of the voltage applied to the flash memory device in order to ensure that the correct write, read and/or erase commands are carried out. The invention is also directed towards a flash memory device.

Abstract: Embodiments relate to tracking a transactional execution footprint. An aspect includes receiving a store instruction which includes store data. It is determined if the store instruction is executing within a transaction that effectively delays committing stores to a shared cache until the transaction has completed. The store data is stored to a cache line in a local cache. The cache line is marked as dirty if the transaction is active. The stored data that was marked as dirty in the local cache is invalidated if the transaction has terminated abnormally. The stored data is un-marked if it is determined that the transaction has successfully ended.

Abstract: A storage controller that includes a cache receives a command from a host, wherein a set of criteria corresponding to read and write response times for executing the command have to be satisfied. The storage controller determines ranks of a first type and ranks of a second type corresponding to a plurality of volumes coupled to the storage controller, wherein the command is to be executed with respect to the ranks of the first type. Destage rate corresponding to the ranks of the first type are adjusted to be less than a default destage rate corresponding to the ranks of the second type, wherein the set of criteria corresponding to the read and write response times for executing the command are satisfied.

Abstract: A method includes storing architectural state data associated with a processing unit in a cache memory using an allocate without fill mode. A system includes a processing unit, a cache memory, and a cache controller. The cache controller is to receive architectural state data associated with the processing unit and store at least a first portion of the architectural state data in the cache memory using a first fill mode responsive to a first value of a fill mode flag and store at least a second portion of the architectural state data in the cache memory using a second fill mode responsive to a second value of a fill mode flag, wherein the first fill mode differs from the second fill mode with respect to whether previous values of the architectural state data are retrieved prior to storing the first or second portions in the cache memory.

Abstract: A cache cluster is configuration-aware such that client initialization, access to replicated cached data and changes to the underlying structure of the cache cluster can be dynamically updated. For example, a management system monitoring a cache cluster notices a large number of requests for a key that causes a significant load on a first memory caching node. To reduce the load on the first memory caching node, the management system may cause cached data related to the key to be replicated to a second memory caching node. A configuration stored in one or more of the memory caching nodes may be updated by the management system to allow both memory caching nodes to serve the requests for the key to clients.

Abstract: Mechanisms are provided for performing a write operation on a shared resource in a cluster of data processing systems. The mechanisms determine whether a locally cached copy of the shared resource is present in a local cache memory. The mechanisms, in response to a determination that a locally cached copy is present, determine whether the locally cached copy is a latest version of the shared resource. The mechanisms, in response to determining that that locally cached copy is a latest version: perform the write operation on the locally cached copy to generate an updated locally cached copy, and transmit a cluster event notification to other data processing systems of the cluster indicating the shared resource was written to and which data processing system performed the write operation. The cluster event notification is logged in at least one change log data structure associated with the other data processing systems.

Abstract: A heterogeneous memory system includes a network interface card, a main memory arrangement, a first-level cache, and a memory management unit (MMU). The main memory arrangement, first-level cache and the MMU are disposed on the network interface card. The first-level cache includes an SRAM arrangement and a DRAM arrangement. The MMU is configured and arranged to read first data from the main memory arrangement in response to a stored first value associated with the first data and indicative of a start time. The MMU selects one of the SRAM arrangement or the DRAM arrangement for storage of the first data and stores the first data in the selected one of the SRAM arrangement or DRAM arrangement. The MMU reads second data from one of the SRAM arrangement or DRAM arrangement and writes the data to the main memory arrangement in response to a stored second value associated with the second data and indicative of a duration.

Abstract: A memory system is disclosed. The memory system includes first and second memory devices, and a memory controller configured to selectively enable one of the memory devices, the memory controller having a first line coupled to the first and second memory devices and a second line coupled to the first and second memory devices. The first memory device is configured to provide a notification to the memory controller on the first line and the second memory device is configured to provide a notification to the memory controller on the second line. The first memory device is further configured not to load the first line and the second memory device is further configured not to load the second line when the memory controller is writing to the enabled memory device.

Abstract: An apparatus may comprise a cache file having a plurality of cache lines and a hit predictor. The hit predictor may contain a table of counter values indexed with signatures that are associated with the plurality of cache lines. The apparatus may fill cache lines into the cache file with either low or high priority. Low priority lines may be chosen to be replaced by a replacement algorithm before high priority lines. In this way, the cache naturally may contain more high priority lines than low priority ones. This priority filling process may improve the performance of most replacement schemes including the best known schemes which are already doing better than LRU.

Abstract: Cache hit information is used to manage (e.g., cap) the prefetch distance for a cache. In an embodiment in which there is a first cache and a second cache, where the second cache (e.g., a level two cache) has greater latency than the first cache (e.g., a level one cache), a prefetcher prefetches cache lines to the second cache and is configured to receive feedback from that cache. The feedback indicates whether an access request issued in response to a cache miss in the first cache results in a cache hit in the second cache. The prefetch distance for the second cache is determined according to the feedback.

Abstract: In one embodiment, a method performed by one or more computing devices includes receiving at a host cache a first request for data comprising at least one snapshot of a cached logical unit number (LUN), sending, by the host cache, the data comprising at least one snapshot of the cached LUN in response to the first request, and in response to the completing sending the data comprising at least one snapshot of the cached LUN, sending, by the host cache, a first response indicating that sending the data is complete.

Abstract: A one-dimensional array is allocated in an in-memory cache for each column in a set of tabular data. The data type of each one-dimensional array is set to be the same as the data type of the corresponding column in the tabular data. Once the one-dimensional arrays have been allocated in memory, a portion of the data from each column in the tabular data is stored in a corresponding one-dimensional array. The tabular data stored in the one-dimensional arrays in the cache may then be utilized to generate an on-screen display of a portion of the tabular data.

Abstract: A memory buffer with a set of one or more structures is created by a process of a first software program. The first memory buffer comprises a predetermined amount of memory. It is determined that a structure of the set of one or more structures has been or will be consumed by a second software program that supports the first software program. The consumption of the structure of the set of one or more structures indicates that memory associated with the structure of the set of one or more structures is being reclaimed. In response to the determination that the structure of the set of one or more structures has been or will be consumed, data is written from a first location to a second location. The first location is in memory allocated to the first software program and the second location is indicated for data storage.

Abstract: A memory buffer with a set of one or more structures is created by a process of a first software program. The first memory buffer comprises a predetermined amount of memory. It is determined that a structure of the set of one or more structures has been or will be consumed by a second software program that supports the first software program. The consumption of the structure of the set of one or more structures indicates that memory associated with the structure of the set of one or more structures is being reclaimed. In response to the determination that the structure of the set of one or more structures has been or will be consumed, data is written from a first location to a second location. The first location is in memory allocated to the first software program and the second location is indicated for data storage.

Abstract: Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.

Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.

Abstract: Memory modules and methods of operating memory modules re-build mapping information from data read from last valid physical pages. Corruption of mapping information is detected. A last valid physical page associated with logical data blocks is read. Mapping information is obtained from the data read from the last valid physical page, and mapping information is re-built using the mapping information obtained from the last valid pages.

Abstract: Embodiments of the invention describe an apparatus, system and method for utilizing a page miss handler having wear leveling logic/modules for memory devices. Embodiments of the invention may track an amount of writes directed towards cells of a memory device, and determine whether a linear address specified by a system write transaction is included in a translation-lookaside buffer (TLB). In response to determining the linear address is not included in the TLB, resulting in a TLB miss, embodiments of the invention may perform a page table walk to obtain a corresponding physical address, and convert the physical address to a device address for accessing the memory device based the tracked amount of writes. Thus, embodiments of the invention are more efficient compared to prior art solutions, as instead of all memory operations, only those that miss in the TLB incur additional wear leveling address translation overhead.

Abstract: A translation lookaside buffer (TLB) of a computing device is a cache of virtual to physical memory address translations. A TLB flush promotion threshold value indicates when all entries of the TLB are to be flushed rather than individual entries of the TLB. The TLB flush promotion threshold value is determined dynamically by the computing device by determining an amount of time it takes to flush and repopulate all entries of the TLB. A determination is then made as to the number of TLB entries that can be individually flushed and repopulated in that same amount of time. The threshold value is set based on (e.g., equal to) the number of TLB entries that can be individually flushed and repopulated in that amount of time.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: A method, computer program product, and storage device for managing a computerized memory for storing data are disclosed. Data updates are performed by writing data updates out-of-place where data updates to outdated data are written to a subunit different from a subunit containing the outdated data. The subunit containing the outdated data is invalid, while a subunit containing up-to-date data is a valid subunit. A data structure is maintained for providing the m units in a sorted way. A first subset of n units is selected out of the set of m units with n<m by selecting units from n positions in the data structure. It is searched in the first subset to identify a unit that matches a predetermined criterion, and data of valid subunits of a unit identified in the first subset is rewritten into at least another unit.

Abstract: A system can include a processor coupled to a bus; a first memory coupled to the bus, configured to limit access to a privileged portion according to at least protection values; a second memory coupled to the bus and having a privileged supervisory portion configured to be section erasable, access to the second memory being limited according to at least the protection values; and a boot sequence stored in the privileged portion that configures the processor to decode values stored in the supervisory portion into the protection values for storage in protection value registers.

Abstract: A microcomputer including a CPU, a plurality of protection information storages configured to store memory protection information specifying an access permission state or access prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information, and a reset apparatus configured to output a reset signal to the plurality of protection information storages according to a reset request output from the CPU according to a switching of programs executed by the CPU. Each of the plurality of protection information storages is set to a second memory protection state according to the reset signal from a first memory protection state.

Abstract: A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.

Abstract: A memory access operand of an instruction that accesses memory may be treated as a transaction atomic access. The processor may execute one or more processor state setting instructions, causing state information to be set in the processor. Upon executing a transaction policy override instruction, the default conflict detection policy is overridden for one or more subsequent memory accessing instructions.

Abstract: Provided are techniques for local locking in a bi-directional synchronous mirroring environment. In response to receiving a write operation for a block of data on a first volume, a lock is obtained on a corresponding block of data on a second volume to obtain exclusive access to that block of data on the second volume. in response to determining that an active write indicator is set to indicate that there is not an active write on the second volume, updated data for the corresponding block of data is written to cache for the second volume, the lock is released to remove exclusive access to the corresponding block of data on the second volume, and a transfer complete message is sent to the first volume.

Abstract: A data control system facilitates transfer of a virtual disk from a primary storage system to a secondary storage system. The data control system, responsive to an instruction to transfer the virtual disk, wherein the virtual disk comprises a plurality of data blocks, determines whether each of the plurality of data blocks is allocated or unallocated; for each data block of the plurality of data blocks determined to be allocated, the data control system reads the data block from memory in the primary storage system and transfers the data block for storage in the secondary storage system; and for each data block of the plurality of data blocks determined to be unallocated, the data control system refrains from reading the data block from memory in the primary storage system.

Abstract: A method generates input/output (IO) commands by plural different applications that execute on a host. The method prioritizes the applications by inserting different classifiers into the IO commands at a host bus adapter (HBA) located in the host. A storage device receives the IO commands and processes the IO commands according to priorities based on the classifiers for the applications.

Abstract: In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

Abstract: The MMU services data requests associated with isochronous (ISO) data (referred to herein as “ISO requests”) with a high priority to meet a fixed latency requirement. Such data includes display data for transmission to the display device or other display devices. Conversely data requests associated with non-isochronous (NISO) data are serviced with a relatively lower priority. Such data requests include requests received from the CPU, video requests and copy requests. The MMU utilizes a buffering mechanism to buffer ISO and NISO requests. The size of the buffer that stores ISO requests controls the amount of memory bandwidth that is allocated to the ISO requests and the amount of memory bandwidth available for NISO requests.

Abstract: A memory content access interface may include, but is not limited to: a read-path memory partition; a write-path memory partition; and a memory access controller configured to regulate access to at least one of the read-path memory partition and the write-path memory partition by an external controller.

Abstract: One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved values, where the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values. The controller is configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory. The de-interleaving module is configured to de-interleave the interleaved values in at least one of the portions to generate a de-interleaved portion such that processing downstream of the de-interleaving module can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module.

Abstract: Dynamically sharing information among a plurality of adapters in a multipath input/output (MPIO) system, selecting one of the adapters to receive an input/output request based on the shared information, and sending the input/output request to that adapter.

Abstract: The access device comprises a memory and a device controller configured to send and receive a data control right between the data recording device and a central controller provided in a host device. When having received a request to interrupt transfer of data from the central controller while data is being transferred from the data recording device, the device controller releases the data control right from the data recording device, and has the data recording device determine whether or not mismatching has occurred in file system management information for data stored in the memory. The device controller then returns the data control right to the data recoding device when it is determined that mismatching has occurred in the file system management information. The data recording device releases the data control right after eliminating the mismatching in the file system management information according to the returned data control right.

Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

Abstract: Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.

Abstract: A controller as an embodiment of the present disclosure controls a timing of transmitting an access request that has been received from an initiator (or its transmission interval). The controller includes: transmitting and receiving circuitry configured to receive an access request related to burst accesses from a first initiator that is connected via a first bus to, and adjacent to, the transmitting and receiving circuitry and configured to transmit the access request to a second bus implemented as a network; and a transmission interval controller configured to control the timing of transmitting the access request that has been received from the first initiator according to density of the burst accesses during a period in which the burst accesses continue and an access load on the second bus.

Abstract: An arbiter device arbitrating resource requests received at a plurality of input ports is proposed, which comprises an arbiter circuit that selects an input port to which a resource request is to be granted and successively grants a number of resource requests received at the selected input port.

Abstract: Input/output (I/O) requests generated by processes are typically stored in I/O queues. Because the queued I/O requests may not be associated with the processes that generated them, changing a process' priority may not affect the priority of the I/O requests generated by the process. Therefore, after the process' priority has been increased, it may be forced to wait for an I/O handler to service its I/O request, which may be stuck behind an I/O request generated by a lower priority process. Functionality can be implemented to associate the processes' priorities with the I/O requests generated by the processes. Also, reordering the queued I/O requests to reflect changes in the processes' priorities can ensure that the I/O requests from high priority processes are serviced before the I/O requests from low priority processes. This can ensure efficient processing and lower wait times for high priority processes.

Abstract: An ExpressCard adapter able to accept a PCI-E-type or a USB-type ExpressCard in a single ExpressCard slot includes the ExpressCard slot, a PCI-E port, a data conversion unit, a switch unit, and a detection unit. The data conversion unit is connected to the PCI-E port, and converts between USB data and PCI-E data. The switch unit connects the ExpressCard slot to the PCI-E port or to the data conversion unit. The detection unit detects the type of ExpressCard which is inserted and controls the switch unit to connect the ExpressCard slot either to the PCI-E port or to the data conversion unit as required.

Abstract: Disclosed is a method, system, and computer program product for automated implementation of pipeline flip-flops in an electronic design. Two operating modes can be used either together or separately to implement pipeline flip-flops. An analysis mode is employed to perform a determination of the number of stages of pipeline flip-flops needed for particular portions of an electronic design. A placement stage is used to place the pipeline flip-flops in the layout.

Abstract: In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed.

Abstract: Embodiments of the present invention provide I/O systems, methods, and devices for interfacing pump controller(s) with control device(s) which may have different interfaces and/or signaling formats. In one embodiment, an I/O interface module comprises a processor, a memory, and at least two data communications interfaces for communicating with a pumping controller and a control device. The I/O interface module can receive discrete signals from the control device, interpret them accordingly and send the packets to the pump controller. The pump controller reads the packets and takes appropriate actions at the pump. The I/O interface module can interpret packets of data received from the pump controller and assert corresponding discrete signals to the control device. The I/O interface module is customizable and allows a variety of interfaces and control schemes to be implemented with a particular multiple stage pump without changing the hardware of the pump.

Abstract: A system is disclosed that may compensate for bus timing that may vary over operating conditions of a bus. The system may include a communication bus, a first functional unit configured to transmit data via the communication bus, and a second functional unit configured to receive data via the bus. The first functional unit may transmit a first value via the communication bus to the second functional unit. The first functional unit may be further configured to assert a data valid signal responsive to a determination that a first time period has elapsed since the transmission of the first data value. The second functional unit may be configured to receive the first data value and sample the first data value dependent upon the data valid signal.