Abstract: A controller includes a link interface that is to couple to a first link to communicate bidirectional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: A particular device includes a resistance-based memory device, a tag random-access memory (RAM), and a bit recovery (BR) memory. The resistance-based memory device is configured to store a data value and error-correcting code (ECC) data associated with the data value. The tag RAM is configured to store information that maps memory addresses of a main memory to wordlines of a cache memory, where the cache memory includes the resistance-based memory device. The BR memory is configured to store additional error correction data associated with the data value, where the BR memory corresponds to a volatile memory device.

Abstract: The technology disclosed herein provides a method of verifying data read from a data block when the cell number of the data block does not match an ECC value stored in the data block. In particular, the method includes accessing a data block in an indexed sequence of data blocks based on a cell number, wherein each data block in the indexed sequence includes a stored ECC value; retrieving an offset associated with the cell number of the data block; generating an ECC value based on the cell number and the offset; and determining whether the generated ECC value and the stored ECC value satisfy an integrity condition.

Abstract: A storage system has a RAID group configured by storage media, a system controller with a processor, a buffer memory coupled to storage devices and the processor by a communication network, and a cache memory coupled to the processor and the buffer memory by the network. A processor that stores first data, which is related to a write request from a host computer, in a cache memory, specifies a first storage device for storing data before update, which is data obtained before updating the first data, and transfers the first data to the specified first storage device. A first device controller transmits the first data and second data based on the data before update, from the first storage device to the system controller. The processor stores the second data in the buffer memory, specifies a second storage device, and transfers the stored second data to the specified second storage device.

Abstract: Integrated circuit memory systems and methods include comparing a number of erase cycles of a memory block corresponding to a read request to a first value and reading data stored in the memory block according to a first read condition corresponding to a first reliability improvement operation when the number of erase cycles of the memory block is less than the first value. An error of the data read according to the first read condition may be corrected using an error correction code (ECC) when the error of the data read according to the first read condition is correctable.

Abstract: A paging scheme for a Solid State Drive (SSD) error correction mechanism that exchanges portions of a parity component, such as a page, between SRAM and less expensive DRAM, which stores the remainder of a context of pages. A parity operation applies an XOR function to corresponding memory positions in the pages of the context. Dedicated error correction (parity) SRAM need only enough memory for portions of memory, typically a cache line of a page, upon which the parity operation (XOR) is operating. The remaining portions in the context are swapped, or paged out, by cache logic such that the entire context is iteratively processed (XORed) by the parity operation.

Abstract: An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified based on error rate variations. The controller may be configured to write user data and error-correction data to the memory. The user data and the error-correction data are organized as a super-page. The super-page includes a plurality of sub-pages. The plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using more than one of the plurality of page types.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

Abstract: A method of improving fault tolerance in a computing system arranged to find a computational solution, the method comprising: computing at least two versions of the solution by using a hierarchy of at least two different solvers in parallel; and if there is a fault during execution of a solver resulting in a missing value, substituting a value from a solver that is lower in the hierarchy to replace the missing value.

Abstract: A power cap agent establishes a power cap. The power cap agent throttles a first power priority virtual machine. The power cap agent determines that the first power priority virtual machine and the additional power priority virtual machine contribute to power consumption above the power cap among the plurality of servers. The power cap agent throttles the additional power priority virtual machine, wherein the first power priority virtual machine has a first power priority lower than an additional power priority of the additional power priority virtual machine. The power cap agent determines that the first power priority virtual machine and the additional power priority virtual machine contribute to power consumption above the power cap, responsive to throttling the first power priority virtual machine and throttling the additional virtual machine.

Abstract: Techniques are described for managing access of executing programs to non-local block data storage. In some situations, a block data storage service uses multiple server storage systems to reliably store block data that may be accessed over one or more networks by programs executing on other physical computing systems. Users may create block data storage volumes that are each stored by at least two of the server block data storage systems, and may initiate use of such volumes by one or more executing programs, such as in a reliable manner by enabling an automatic switch to a second volume copy if a first volume copy becomes unavailable. A group of multiple server block data storage systems that store block data volumes may in some situations be co-located at a data center, and programs that use volumes stored there may execute on other physical computing systems at that data center.

Abstract: A method, system and computer-usable medium are disclosed for persisting Lightweight Memory Trace (LMT) data across reboots of a system. One or more LMT traces are stored in a predetermined pinned memory area with a server's operating system (OS) through a system reboot. A pointer to each LMT is likewise stored in nonvolatile storage (NVS) at a known memory location. The pointers in NVS point to a page which describes where the LMT trace and other kernel structures are in real memory. During initialization, the OS guards these preserved pages to prevent them from being used. By keeping the current and prior address within NVS, the current LMT and prior traces can be retrieved and processed to determine the cause of the system reboot.

Abstract: A system for archiving data objects using secondary copies is disclosed. The system creates one or more secondary copies of primary copy data that contains multiple data objects. The system maintains a first data structure that tracks the data objects for which the system has created secondary copies and the locations of the secondary copies. To archive data objects in the primary copy data, the system identifies data objects to be archived, verifies that previously-created secondary copies of the identified data objects exist, and replaces the identified data objects with stubs. The system maintains a second data structure that both tracks the stubs and refers to the first data structure, thereby creating an association between the stubs and the locations of the secondary copies.

Abstract: A system and method for managing storage of a digital stream including writing data of the stream to a network storage device, while monitoring availability of the network storage device, switching to writing additional data of the stream to a standby storage device while continuing monitoring the availability of the network storage device, if the network storage device becomes unavailable, switching back to writing additional data of the stream to the network storage device while continuing monitoring the availability of the network storage device, when the network storage device becomes available, and writing to the network storage device the additional data that was written to the standby storage device while the network storage device was unavailable, concurrently with the writing of the additional data of the stream to the network storage device.

Abstract: A method and system for requesting, cross-referencing, extracting and storing historical records of data backup activity by using a software component that interfaces to a plurality of data backup software devices is disclosed. Through the use of a system and method in accordance with the present invention, the aforementioned database can be made self-refreshing, requiring minimal ongoing intervention subsequent to initial configuration. In addition, the aforementioned data refreshes can be manually invoked at any time.

Abstract: A data storage system may be configured to allocate replica-sets in a balanced manner and mark some of these balanced replica-sets as being spares. As one or more drives or machines fail, the data storage system may move all copies of an affected replica-set to a marked spare replica-set and mark the affected replica-set as being inactive or invalid. As the failed drives are replaced, the data storage system may reconfigure those inactive replica-sets and use them as new spares. The data storage system may implement a coordinator module that handles the balancing and allocation of spares within a sub-cluster. The coordinator may also reallocate entire replica-sets across sub-clusters to maintain balance at the cluster level.

Abstract: A method of classifying and monitoring database operations based on a recovery cost may include receiving an indication of a recoverable operation. A count in a persistent storage, such as a catalog, corresponding to an occurrence of the recoverable operation is incremented.

Abstract: A backup client de-duplicates backup data sets using a locally stored, memory resonant, root tag vector and hash cache. To create a new backup data set, the client queries a backup server to determine which of the root hashes in the root tag vector are available on the backup server. If one or more are no longer available, the backup server re-uses a root tag vector entry corresponding to one of the no longer available root hashes. If all are available, the client ages out a root hash for re-use based on a combination of age and represented size. Data is de-duplicated by chunking and hashing it and comparing the resulting hashes to hashes in the hash cache. To prevent the hash cache from growing too large, entries in the hash cache are aged out based on a combination of age and size of data represented by the entries.

Abstract: A single system merges primary data storage, data protection, and intelligence. Intelligence is provided through in-line data analytics, and data intelligence and analytics are gathered on protected data and prior analytics, and stored in discovery points, all without impacting performance of primary storage. As data is written it is automatically mirrored for data protection as part of a High Availability (HA) process. Real-time analysis is done in-line with the HA processing, enabling a variety of data analytics. Data content can mined from within files or blocks. The gathered intelligence is used to tag objects with extended metadata, enabling both valuable search options and rapid restore options. Data recovery begins with metadata restoration, followed by near-instantaneous access to “hot” regions of data being restored, allowing site operation to continue or resume while a restore is ongoing.

Abstract: The embodiments herein provide a system and method for synchronization of data and recovery of failures during synchronization between two systems. The system for executing synchronization between the source and target systems comprises a connector framework, a process framework, a mapping manager, a recovery manager, a conflict manager and a failure manager. A method for bidirectional data synchronizing and integrating involves keeping information about integration user in integration database for each entity and update along with update time and audit id, only when the system does not keep information about the created and updated entity. A method of synchronizing only the entities qualifying a criterion, a method for failure recovery from a correct point during integration process, a method for handling recovery for changes coming from multiple end points and a method for recovery during server shutdown are also provided.

Abstract: A method for reading a kernel log upon a kernel panic in an operation system is applicable to a computing device including a processing unit and a storage unit, coupled to the processing unit, for storing the kernel and including a log backup partition and a user data partition. The method includes the computing device performing the operating system by the kernel; the computing device generating a kernel log upon performing the operating system, and writing the kernel log into the log backup partition; and upon a kernel panic occurring and then the processing unit being reset, the computing device performing a kernel initialization procedure including reading and then writing the kernel log in the log backup partition into the user data partition, wherein the kernel log in the log backup partition includes information of a process of operating the kernel before the processing unit is reset.

Abstract: Embodiments of the invention address deficiencies of the art in respect to memory fault tolerance, and provide a novel and non-obvious method, system and apparatus for single channel memory mirroring. In one embodiment of the invention, a single channel memory mirroring system can be provided. The single channel memory mirroring system can include a memory controller, a single communications channel, and an operational data portion of memory, and a duplicate data portion of memory, both portions being communicatively coupled to the memory controller over the single communications channel. Finally, the system can include single channel memory mirror logic. The logic can include program code enabled to mirror data in the operational data portion of memory in the duplicate data portion of memory.

Abstract: A system and method for utilizing virtual ports associated with a physical port in a Fiber Channel adapter for use in a clustered storage system is disclosed. A plurality of virtual ports are created and associated with a physical port on a storage system. One of the virtual ports is utilized as a standby port to be used to assume the identity of a port associated with a failed storage system in the cluster. In the event of a failover operation, the standby port is activated and assumes the identity of the failed storage systems port. Data access requests previously directed to the failed storage system are received by the activated virtual port and processed by the surviving storage system.

Abstract: Failover in a data center that includes a multi-density server, where the multi-density server includes multiple independent servers, includes; detecting, by a management module, a failure of one of the independent servers of the multi-density server; identifying, by the management module, a failover target; determining, by the management module, whether the failover target is a non-failed independent server included in the multi-density server; and responsive to determining that the failover target is a non-failed independent server included in the multi-density server, migrating, by the management module, the failed independent server's workload to another server that is not included in the multi-density server.

Abstract: The method is performed as a client device and includes receiving a first message that includes a first data usage value. The first message is formatted according to a respective format. After receiving the first message, the method further includes acquiring a data usage template corresponding to the respective format. The method further includes receiving a second message that includes a second data usage value. The second message is formatted according to the respective format. The method further includes parsing the second message according to the data usage template so as to obtain a second data usage value.

Abstract: A method for execution by a storage unit in a directory-less distributed storage network (DSN) begins by receiving a read request regarding a data segment of data. The method continues by determining, based on the read request, whether an encoded data slice of a set of encoded data slices is locally stored, wherein the data segment was dispersed storage error encoded to produce the set of encoded data slices. When the encoded data slices are locally stored, the method continues by generating a read response. The method continues by determining whether to forward the read request to another storage unit of the directory-less DSN. When the read request is to be forwarded, the method continues by identifying one or more storage units to which the read request is to be forwarded and the read request is then forwarded to the one or more identified storage units.

Abstract: A storage apparatus is provided with a virtualization mechanism which manages first and second LPARs (logical partitions) assigned respectively with first and second logical resources acquired by logically partitioning physical resources in the storage apparatus. The virtualization mechanism provides a shared memory area which is an area based on a memory and can be accessed by the first and second LPARs. The first LPAR stores information required for taking over a data input/output process handled by the first LPAR to the second LPAR, in the shared memory area. When detecting that a fault occurs in the first LPAR, the second LPAR acquires the information required for taking over from the shared memory area and takes over and executes the data input/output process formerly handled by the first LPAR on the basis of the information required for taking over.

Abstract: In one embodiment, a system includes a processor and logic integrated with and/or executable by the processor, the logic being configured to cause the processor to define a disaster recovery (DR) family, the DR family having one or more DR clusters accessible to a DR host and one or more production clusters accessible to a production host, wherein the DR host is configured to replicate data from the one or more production clusters to the one or more DR clusters, create a backup copy of data stored to the one or more production clusters, store the backup copy to the one or more DR clusters, establish a time-zero in the DR family, and share a point-in-time data consistency at the time-zero among all clusters within the DR family. Other systems, methods, and computer program products are presented for DR testing, according to more embodiments.

Abstract: A test device includes a circuit modelling portion suitable for generating one or more model circuits by modelling a test-object circuit with a one-to-one or a one-to-multi relationship between the test-object circuit and the model circuits, and a test operation portion suitable for synthesizing the model circuits and performing a test operation on the model circuits.

Abstract: Exemplary system, method and computer-accessible medium for testing a multi-core chip can be provided which can have and/or utilize a plurality of identical cores. This can be performed by comparing each core with as many as at least the number of spare cores plus 1 using a comparator; the number of comparators can equal the total number of cores multiplied by one-half the number of spare cores plus 1. A mismatch between two cores can identify at least one of the two cores as defective and a perfect match between two cores can identify both cores as not defective. The multi-core chip can fail the test if the number of defective cores can be greater than the number of spare cores.

Abstract: Methods and apparatus are provided that facilitate debugging operations for components in dynamic power domains. In an embodiment, an integrated circuit includes hardware sectors associated with observability circuits served by a debug data bus of a debug circuit. A controlled sector residing in a dynamically-controlled power domain may be turned off while the power domain of another sector remains on. To continue to have debug observability all the way through and after these power events, a debug data register is configured to provide data, such as configuration and/or programming data, to the observability circuit of the controlled sector via the debug data bus. A shadow register is configured to capture the data provided to the controlled sector's observability circuit. The shadow register data is used upon restoring power to the controlled sector to restore the controlled sector's observability circuit to a state when the controlled sector was previously powered on.

Abstract: An exemplary embodiment of the present techniques may detect and correlate events from moving object sensor data by receiving data from a sensor. The data received from the sensor may be mapped, and events may be detected based on the mapped sensor data. Events from the mapped sensor data may be correlated online.

Abstract: Embodiments of the present invention provide a method, system and computer program product for configuration item (CI) status value analysis for multiple performance monitors. In one embodiment of the invention, a multi-CI analysis method can be provided. The method can include weighting different CI status values produced by different performance monitors for a single resource in a monitored computing system and displaying selected ones of the weighted different CI status values according to relevance determined by weight. In one aspect of the embodiment, weighting different CI status values produced by different performance monitors for a single resource in a monitored computing system can include locating the different CI status values for the single resource in a configuration management database (CMDB), identifying the different performance monitors producing the different CI status values in the CMDB and applying weights to the different CI status values according to CI status value characteristics.

Abstract: Data is received or accessed that includes a structured file encapsulating data required by an execution environment to manage executable code wrapped within the structured file. Thereafter, code and data regions are iteratively identified in the structured file. Such identification is analyzed so that at least one feature can be extracted from the structured file. Related apparatus, systems, techniques and articles are also described.

Abstract: The claimed subject matter provides for systems and/or methods for debugging a computer-executable file. The computer-executable file may be executing in a first runtime environment and located in a first process. The file may further comprise on object having a proxy in that first runtime environment. One method embodiment comprises the steps of debugging said computer-executable file; detecting a proxy for an object called by said file; decoding said proxy to obtain physical information regarding said object; returning said physical object information; and transforming said physical object information into logical object information.

Abstract: Aspects of the present invention provide a system and method for a user of an event-driven simulator to specify complex breakpoint conditions and actions which allow both hardware and software states to be accessed. In a virtual platform modeling hardware components, bare-metal software programs, and high-level software applications or processes, a global identifier may be used to unambiguously identify each element, object, and subcomponent of the modeled system. The unambiguous global identifier may include an instance name and a hierarchical path name. A state of a specific element, object, or modeled component may trigger a breakpoint or be utilized or set as part of a breakpoint condition.

Abstract: A method for capturing breakpoint information from a debuggee software process includes generating a breakpoint condition based upon a breakpoint request received from a user computing device corresponding to a user and transmitting the generated breakpoint condition to debuglets, each corresponding to a software process executed by a debuggee service. The debuggee service executes on a distributed system, and each debuglet translates the generated breakpoint condition to a physical breakpoint condition set to the respective software process. The method also includes receiving a request from one of the debuglets to update active breakpoint information captured by the debuglet upon the physical breakpoint condition being hit by one of the software processes and transmitting a notification from the processing device indicating the physical breakpoint condition being hit to the user computing device.

Abstract: Methods of managing observability code in an application program include generating an application program including an observability point, the observability point including a location in the application at which observability code, or a call to observability code, can be inserted, loading the application program into a memory of a target system, retrieving observability information from an observability point information file, and inserting the observability code, or the call to the observability code, at the observability point in the memory of the target system using the observability information retrieved from the observability point information file.

Abstract: In an embodiment, an address watch is established on a memory address while the execution of a first thread of a program is halted. In response to a second thread modifying memory contents at the memory address, encountering the address watch and halting, a determination is made whether a first variable in the program that represents the memory address is displayed on a user interface for the first thread. If the first variable in the program that represents the memory address is displayed on the user interface for the first thread, the value of the first variable is read and displayed on the user interface of the first thread.

Abstract: A simulation system enables comparison of a realized physical implementation against the simulation models that produce them, thereby detecting differences between an initial, logical design and the resulting physical embodiment. Errors introduced by an initial design, faulty Intellectual Property blocks, faulty programmable logic device silicon, faulty synthesis algorithms and software, and/or faulty place and route algorithms and software may be detected. As a result, the simulation system reflects both the accuracy of the actual implemented device with the capacity and performance of a purpose built hardware-assisted solution.

Abstract: A shared platform included in a device can be configured to execute instructions from a first application and a second application to operate the device. The shared platform can be configured to receive mode instructions from the first application indicative of operating in a test mode where the shared platform provides simulated responses to the first application. The shared platform can receive a request from the first application pertaining to an operation of the second application. The shared platform operating in the test mode can determine a response to the request from the first application based on a simulation of providing the request to the second application.

Abstract: Aspects of the present invention describe a system and method for a user of an event-driven simulation environment and/or embedded software debugger interface to step through the source code of components modeled by the environment/debugger, including the embedded software or hardware model source code. In a virtual platform modeling hardware components, bare-metal software programs, and high-level software applications or processes, the source code of each modeled component may be stepped through during simulation. Insertion points for breakpoints or watchpoints may be detected during a traversal of the source code of each component being modeled in the virtual platform and such breakpoints inserted automatically.

Abstract: An online marketplace for distributing software applications is established. From the online marketplace, devices are enabled to select respective ones of the software applications and initiate testing of the selected software applications in connection with testing tools operating in respective secure testing environments that shield the devices from potential adverse effects arising from testing the selected software applications. The testing tools generate testing data relating to one or more criteria for certifying the selected software applications. For each of one or more of the selected software applications, a determination is made whether or not to classify the software application as a certified software application based on an evaluation of the testing data generated during the testing of the software applications initiated by a plurality of the devices.

Abstract: A method executable on one or more processors for modeling a test space is provided. The method may include defining a coverage model including a set of variables. The method may also include selecting one or more variables within at least one subset of a plurality of subsets of the set of variables. The selection may be according to an interaction level requirement defined for at least one or more of the subsets, whereby the interaction level corresponds to a coverage of the test space that covers a plurality of possible combinations of the one or more variables at multiple levels. Furthermore, respective values for the one or more selected variables within the subset of the set of variables may be assigned. The method may also include one or more definitions for value combinations for said variables with assigned values.

Abstract: A system generates a test path set in a very efficient manner. The test path set may be tailored to test a target physical system, such as a complex set of source code, a manufacturing line of multiple process nodes, or other physical system. The system may generate the test path set to meet certain goals in testing the target physical system, for example comprehensive testing of system paths, system nodes, or particular subsets. As one example, the system may efficiently generate a test path set that uses the minimum number of test paths to test a coverage goal, for example traversing each of the prime paths in the target physical system.

Abstract: Testing computer software applications is implemented by probing a computer software application to determine the presence in the computer software application of any data-checking features, and applying a rule to the data-checking features that are determined to be present in the computer software application, thereby producing a testing set of inputs. The testing set includes any sets of inputs that were used to test sets of data-checking software, where each of the sets of data-checking software includes one or more data sanitizers and/or data validators, and where the rule is configured to produce the testing set to include one or more of the sets of inputs when the rule is applied to any of the data-checking features. The computer software application is tested using the testing set.

Abstract: An apparatus is provided for facilitating bulk assignment of test cases to a test cycle. The apparatus may include at least one memory and at least one processor configured to enable selection, via a user interface, of test cases to assign the test cases to a designated test cycle. The test cases are designated for testing or execution of functions of at least one application. The processor is also configured to automatically calculate an estimated duration of time in which to complete the testing or execution of the functions in response to receipt of indications of selections of the test cases via the user interface. The processor is also configured to provide visible indicia in the user interface indicating the estimated duration of time in which to complete the testing or the execution of the functions of the application. Corresponding computer program products and methods are also provided.

Abstract: Systems and methods for testing a network page without encapsulating the network page with a test environment are presented. A script such as a test injector script may be added to a network page in development. The test injector script may identify one or more tests to run on the network page based, at least in part, on metadata included in the network page. The domain object model (DOM) of the network page may be modified to include tests to be performed on the network page.

Abstract: The present disclosure describes systems and techniques relating to processing of network communications. According to an aspect of the described systems and techniques, a network device includes a content addressable memory (CAM); and processing circuitry configured to receive records to be stored in the CAM, compare the records to identify similar bit values at respective bit positions of at least a portion of the records, store in the CAM the similar bit values in a single sample record corresponding to the portion of the records, store in the CAM remaining non-similar bit values of the portion of the records, thereby compressing the portion of the records stored in the CAM, store in the CAM one or more remaining records of the received records not included in the portion of the records, and search the CAM including the compressed portion of the records and the one or more remaining records.