Abstract: An apparatus according to one embodiment includes a transducer structure having: a lower shield having recesses in an upper surface thereof; an upper shield formed above the lower shield; a current-perpendicular-to-plane sensor between the upper and lower shields, the recesses being positioned on opposite sides of the sensor; and a first insulating layer in the recesses in the upper surface of the lower shield. An apparatus according to another embodiment includes a transducer structure having: a lower shield; an upper shield formed above the lower shield, the upper shield having recesses in a lower surface thereof; a current-perpendicular-to-plane sensor between the upper and lower shields, the recesses being positioned on opposite sides of the sensor; and a first insulating layer in the recesses in the lower surface of the upper shield.

Abstract: In one embodiment, a magnetic sensor includes: a lower scissor free layer; an upper scissor free layer above the lower scissor free layer; a separation layer between the upper and lower scissor free layers; and upper stabilization layers on opposite sides of the upper scissor free layer in a cross-track direction, where lower surfaces of the upper stabilization layers are above a plane extending along a top surface of the separation layer. In another embodiment, a magnetic sensor includes: a lower scissor free layer; an upper scissor free layer above the lower scissor free layer; a separation layer between the upper and lower scissor free layers; and lower stabilization layers on opposite sides of the lower scissor free layer in a cross-track direction, where upper surfaces of the lower stabilization layers are below a plane extending along a bottom surface of the separation layer.

Abstract: A method, apparatus, and system for implementing enhanced asymmetric degauss control for a write head for hard disk drives. A degauss period is provided at the end of a write. The write head is driven asymmetrically with respect to the positive and negative driving currents during the degauss period. The average value of the write current during the degauss period is non-zero.

Abstract: One embodiment generally relates to a magnetic recording head. The magnetic recording head has a body having an upper surface and a media bearing surface, a spot size converter disposed in the body and extending from the upper surface to the media bearing surface. The spot size converter has a core, comprising a first portion having a rectangular wall extending below the upper surface; and a second portion having a trapezoidal wall extending below the first portion. The magnetic recording head additionally has a first cladding adjacent to the spot size converter in an in-surface direction of the spot size converter, wherein the first cladding has a first refractive index lower than a refractive index of the spot size converter.

Abstract: Described embodiments provide a magnetic mass storage device with a system clock phase-locked to servo address marks on the magnetic disk. A head sequentially reads multiple adjacent servo address marks in a spiral track of servo address marks. When a servo address mark detector detects a mark, the count value of a counter driven by the system clock is sampled and held by a latch. A system clock synthesizer calculates differences in value between successively sampled count values from the latch, averages the differences in value to create an average difference value, and normalizes a difference between the average difference value and a target value to create a phase error value. The phase of the system clock is updated using the phase error value.

Abstract: An “all optical switching” (AOS) magnetic recording system, i.e., one that does not require a magnetic field to reverse the magnetization in the magnetic recording media, uses a FeMnPt L10 alloy as the magnetic media. A FeMnPt alloy, with appropriate amounts of Mn, will have high magneto-crystalline anisotropy, but also ferrimagnetic spin alignment for triggering AOS. The combination of high magneto-crystalline anisotropy and ferrimagnetic spin configuration enables the FeMnPt media to function as magnetic media whose magnetization can be switched solely by polarized laser pulses. The FeMnPt media for may be a single layer with or without any segregants. Alternatively, the FeMnPt media may be a multilayered recording layer comprising alternating layers of FePt and MnPt L10 ordered alloys. The segregant-free embodiments of the FeMnPt material may be patterned to form bit-patterned-media (BPM).

Abstract: Provided is a tape recording medium including: a base layer having a first surface and a second surface; a first recording layer disposed over the first surface of the base layer and capable of optically recording first data; an imprinted layer disposed between the base layer and the first recording layer; and a second recording layer. The second recording layer is disposed over the second surface of the base layer, contains a magnetic material, and has recorded second data different from the first data.

Abstract: A recording medium having an outer surface relatively free of magnetic particulates is achievable by, after forming a magnetic recording layer with which magnetic contamination is associated, removing magnetic contamination from the medium by immersing the medium in an acidic water solution. For example, a post-sputter wash process utilizing a mildly acidic water solution having a pH less than around 5 may remove cobalt particle contaminants from the surface of the medium. The water solution may be acidized by introducing into deionized water a pre-diluted strong acid such as nitric acid or a weak acid such as carbonic acid.

Abstract: A recording apparatus includes a recording unit that performs a recording operation to each layer by performing laser light illumination to a recording medium which has (n+1) or more layers as a recording layer and in which a test writing area of each layer is formed between at least n consecutive layers and at a position in which the test writing areas are not overlapped with each other when seen from a laser light incident surface side, and a controller that sets the n consecutive layers to be a recording target layer in the recording operation including a test writing for laser power adjustment and causes the recording unit to execute the recording operation to the n recording target layers, wherein n?2.

Abstract: The present invention relates to a photopolymer formulation containing chemically crosslinked matrix polymers, writing monomers and a photoinitiator system, wherein the photoinitiator system contains a HABI, a dye attuned to the HABI and having an absorption maximum in the range of 400-800 nm and a hydrogen donor. The present invention further relates to a process for producing exposed holographic media with the above photopolymer formulation.

Abstract: System and methods are disclosed in connection with a reaction at or below the surface of a work object, in the context of a fluid flow fostering the reaction. In some example embodiments, the reaction is fostered by (1) creating fluid flow of an inerting fluid over a surface during exposure of the surface to a predetermined type of light, (2) creating fluid flow comprising a reactive species that reacts with another species at or below the work surface in a predetermined manner and/or (3) creating a fluid flow comprising a catalytic species that catalyzes a reaction in a predetermined manner, e.g., during exposure of the surface to a predetermined type of light. In some example embodiments, a light source is employed that comprises a solid-state light source, e.g., a dense array of solid-state light sources. In at least one of such example embodiments, the reaction is a photoreaction associated with the light source.

Abstract: Disclosed herein are near field transducers (NFTs) that include either silver, copper, or aluminum and one or more secondary elements.

Abstract: A device including a near field transducer (NFT); a write pole; at least one dielectric material positioned between the NFT and the write pole; and an adhesion layer positioned between the NFT and the at least one dielectric material.

Abstract: A content assessment apparatus, content assessment method, information reproducing apparatus, and information recording medium are provided that can determine whether digital content has been processed abnormally.

Abstract: A method is provided, for example, to implement multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of read data circuitry within the recording channel is switchably connected to a first analog line of the analog bus to receive read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation. In addition, a write data output of write data circuitry within the recording channel is switchably connected to the first analog line of the analog bus to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to data processing including adjacent track interference detection and/or characterization.

Abstract: A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a second quantized sample having a second precision, wherein the second precision is different from the first precision. The communication channel also includes an iterative decoder configured for utilizing the first quantized sample for a first global iteration of a decoding process and utilizing the second quantized sample for at least one subsequent global iteration of the decoding process.

Abstract: Systems and methods are disclosed for improving performance in data storage devices, particularly devices employing shingled magnetic recording. In one embodiment, an apparatus may comprise a data storage medium having multiple tracks with multiple track pitches. In another embodiment, a method may comprise formatting a data storage memory with a first track having a first track pitch, and formatting the data storage memory with a second track having a second track pitch. The method may further comprise formatting the computer readable data storage memory with a set of tracks including the first track arranged to store data in a shingled manner where one track at least partially overlaps an adjacent track, and the second track separating the set of tracks from a third track.

Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of data tracks. Data is encoded into a first number of codewords, and the first number of codewords are interleave written to a first segment of a first data track. Data is encoded into a second number of codewords, and the second number of codewords are interleave written to a second segment of the first data track. The first number of codewords is different than the second number of codewords, and a size of the first segment is different than a size of the second segment.

Abstract: A method and apparatus for controlling content based on a timeline in a timeline-based content control apparatus with a touch screen. The method includes generating and displaying a linear timeline bar on the touch screen regardless of the size of content; detecting contact on the timeline bar; nonlinearly distorting a predetermined section of the timeline bar being displayed around the touch-detected position on the timeline bar; and performing a fine search and shifting the distorted section depending on a direction of the user's touch.

Abstract: Systems and methods for encoding live multimedia content with audio data synchronized with other streams of data, including video data, in accordance with embodiments of the invention are disclosed. In one embodiment of the invention, an encoding system includes multimedia content storage configured to store live multimedia content including audio data and video data, a processor, and a multimedia encoder, wherein the multimedia encoder configures the processor to receive live multimedia content, generate a timeline using the video data, compute a first time window, align the audio data to the video data using the audio data samples and the timeline, measure a synchronization value of the aligned audio data to the video data using the timeline, realign the audio data to the video data when the synchronization value exceeds a threshold value using the timeline, and multiplex the audio data and video data into a container file.

Abstract: Systems and methods for automatic transformation the overall metadata associated with the multimedia content (MMC) at the global media hub (GMH) into unique role-and-client-based views via the network for review through the media access node (MAN) associated with the client, wherein those views of the metadata, general or temporal or subset, are unique and specific to each user in the context of that user's role within the client.

Abstract: A method provide a selection option to the at least one portable device, the selection option relating to selection of the first audio content and retrieving a selection from the at least one portable device based on the selection option. The method further retrieves a selection of the second audio content and synchronizing the first audio content, the second audio content, and the video content by embedding a synchronizing signal in the first audio content, the second audio content, and the video content. The method further outputs the second audio content and the video content to an output device according to the synchronizing signal. Responsive to the selection of the first audio content, the first audio content with the embedded synchronizing signal is transmitted to the least one portable device, wherein the at least one portable device outputs the first audio content according to the synchronizing signal.

Abstract: An image processing apparatus according to an embodiment includes: an interface configured to obtain management information that has been generated along with movie data generated; and a controller configured to generate, as a representative picture representing the movie data, image information including characters or an icon to be determined by reference to the management information. When selected by a user, the representative picture is presented on a display device in order to start playing back movie data represented by the representative picture.

Abstract: A storage media conversion device includes a mounting bracket (100) and a holder (200). The mounting bracket (100) includes a first baseplate (110) and two corresponding side plates (120) extending perpendicularly from the first baseplate (110). The first baseplate (110) and the two side plates (120) enclose a first loading space (130). Any of the side plates (120) includes a first resilient positioning portion (150) for positioning a first size hard disk (A). A holder (200) includes a pivot shaft (210) pivotally connected to one side of the first baseplate (110), a handle (220) rotatable with respect to the pivot shaft (210), and a contact portion (230) disposed close to the pivot shaft (210). The length from the handle (220) to the pivot shaft (210) is greater than the length from the contact portion (230) to the pivot shaft (210).

Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract: Semiconductor memories are provided. The Semiconductor memory includes a plurality of sense amplifiers, plurality sets of master data line segments and a plurality of memory segments. The plurality sets of master data line segments are arranged in a column direction. Each memory segment includes a plurality of memory cells, and is coupled to a set of corresponding master data line segments via a corresponding sense amplifier. Adjacent sets of corresponding master data line segments are coupled together. When accessing memory data, the memory data are transferred by the adjacent sets of corresponding master data line segments which are coupled together.

Abstract: A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.

Abstract: A storage medium communicating with a memory controller sent a read command is disclosed. The storage medium includes a plurality of memory units. Each memory unit includes at least sixteen memory cells coupled to a word line and a plurality of bit lines. A controlling unit receives first address information according to the read command and generates a row read signal and a column read signal according to the first address information. A row decoding unit activates the word line according to the row read signal. A column decoding unit activates the bit lines according to the column read signal to output a plurality of storing bits stored in the sixteen memory cells. A read-out unit processes the storing bits to generate a plurality of reading bits. The controlling unit outputs the reading bits to the memory controller in serial.

Abstract: An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.

Abstract: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

Abstract: Disclosed are single-ended sensing circuits. Each of the sensing circuits comprises at least a sense amplifier connected to a sense node, an isolation field effect transistor (FET) connected in series between the sense node and a signal line node, and a pre-charged device connected to the sense node. In order to achieve a relatively fast pre-charge of both the sense and signal line nodes and to also achieve a relatively fast and accurate sense of the sense node, the single-ended circuits further incorporate a variable reference voltage generator connected to the gate of the isolation FET for selectively applying different reference voltages to the gate during pre-charging and sensing operations, respectively, and/or a second pre-charge device connected to the signal line node for facilitating pre-charging of that signal line node.

Abstract: A write block read apparatus for a memory device includes a dynamic read address decoder that receives static read address bits as inputs thereto and having an output used to implement a read operation of a memory location corresponding to the read address bits; a dynamic write address decoder that receives static write address bits as inputs thereto and having an output used to implement a write operation of a memory location corresponding to the write address bits; and a static write address decoder, configured in parallel with the dynamic write address decoder, the static write address decoder configured to receive a portion of the static write address bits as inputs thereto, and wherein the static write address decoder is coupled to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation.

Abstract: A method of implementing a write block read function for a memory device includes configuring a dynamic read address decoder to receive static read address bits as inputs thereto and to generate an output used to implement a read operation of a memory location corresponding to the read address bits; configuring a dynamic write address decoder to receive static write address bits as inputs thereto and to generate an output used to implement a write operation of a memory location corresponding to the write address bits; and configuring a static write address decoder, in parallel with the dynamic write address decoder, to receive a portion of the static write address bits as inputs thereto, and coupling the static write address decoder to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation.

Abstract: A parallel processing computing system includes an ordered set of m memory banks and a processor core. The ordered set of m memory banks includes a first and a last memory bank, wherein m is an integer greater than 1. The processor core implements n virtual processors, a pipeline having p ordered stages, including a memory operation stage, and a virtual processor selector function.

Abstract: A memory device includes latching circuitry for receiving a latching value and for providing said latching value as an output. A path receives said latching value and passes said latching value to said latching circuitry. First storage circuitry provides a first stored value when said memory device is in a read mode of operation. A bit line is connected to said first storage circuitry. First control circuitry selectively connects said bit line to said path. Sensing circuitry, when an enable signal is active, detects a voltage change on said path as a result of connecting said bit line to said first storage circuitry and said path, and outputs a latching value, dependent on said voltage change, on said path. Second storage circuitry provides a second stored value in a test mode of operation and second control circuitry receives said second stored value and selectively outputs said second stored value as said latching value on said path.

Abstract: A method and circuit for reducing a glitch in a memory read latch is disclosed. A read latch circuit includes a first logic gate having a first input coupled to a read bit line and a second input. The read latch circuit further includes a second logic gate coupled to receive as inputs a first enable signal and a delayed version of the first enable signal. The second logic gate is configured to provide a second enable signal to the second input of the first logic gate. The second logic gate is configured to provide a rising edge of the second enable signal after a predetermined delay without a corresponding delay of a falling edge of the second enable signal. The first logic gate provides an output corresponding to a data value received on the read bit line responsive to receiving the rising edge of the second enable signal.

Abstract: In a 3D memory with vertical local bit lines, each local bit line is switchably connected to a node on a global bit line having first and second ends, the local bit line voltage is maintained at a predetermined reference level in spite of being driven by a bit line driver from a first end of the global bit line that constitutes variable circuit path length and circuit serial resistance. This is accomplished by a feedback voltage regulator comprising a voltage clamp at the first end of the global bit line controlled by a bit line voltage comparator at the second end of the global bit line. The comparator compares the bit line voltage sensed from the second end with the predetermined reference level and outputs a control voltage to control the voltage clamp In this way the voltage at the local bit line is regulated at the reference voltage.

Abstract: Embodiments relate to preventing or mitigating excessive drop in the negative voltage level of a bitline of memory bitcells by controlling the delay of a trigger signal for initiating injection of negative charge into the bitline. A write assist circuit causes negative charge to drop gradually in response to receiving a data input indicating a negative value of the bitline. When supply voltage is high, the timed delay of trigger signal is reduced, thereby causing negative charge to be injected into the bitline while bitline voltage remains at a higher voltage level and before the bitline voltage drops close to ground voltage. Since the negative charge is injected while the bitline voltage level is relatively high, the bitline is prevented from being pulled down to an excessively negative voltage level even when the supply voltage is relatively high.

Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

Abstract: A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit.

Abstract: The semiconductor device may include a first internal command generator suitable generating first internal command signals after decoding the external command signals in response to the external control signal, a column control signal generator suitable for generating a column control signal after decoding the external command signals in response to the external control signal, and a second internal command generator suitable for generating second internal command signals from the first internal command signals in response to the column control signal. Related systems are also provided.

Abstract: In an embodiment, a method of generating strobe signals includes generating a first strobe signal in a first mode by operating a multiplexer with a clock signal to select between a first input signal and a second input signal, the first input signal having a static first signal level and the second input signal corresponding to a control signal. In a second mode, the method includes generating a second strobe signal by operating the multiplexer with the clock signal to select between the first input signal and the second input signal, the first input signal corresponding to the control signal inverted and delayed and the second input signal having a static second signal level.

Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

Abstract: A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.

Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

Abstract: A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit. The low-pin-count non-volatile (NVM) memory can use only one external control signal and one internal clock signal to generate start, stop, device ID, read/program/erase pattern, starting address, and actual read/program/erase cycles. When programming or erasing begins, toggling of the control signal increments/decrements a program or erase address and a pulse width of the control signal determines the actual program or erase time. A data out of the low-pin-count non-volatile (NVM) memory can be multiplexed with the control signal. In some applications where only the integrated circuit can read the data, a second control signal internal to the integrated circuit generates start, stop, device ID, read pattern, starting address, and actual read cycles, while the first control signal external to the integrated circuit can do the same for the program or erase path.

Abstract: An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells.

Abstract: A spin transfer torque magnetic memory device is disclosed. In one aspect, the spin transfer torque magnetic memory device comprises a first layered structure stacked in a vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device additionally includes a second layered structure stacked in the vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device further includes a magnetic material interposing the first and second layered structures in a horizontal direction different from the vertical direction such that the magnetic material is in contact with a first side surface of the first layered structure and in contact with a first side surface of the second layered structure. Additionally, the magnetic material is configured to have a magnetization direction that can change in response to a current flowing through the magnetic material.