Patents Issued in March 8, 2016
  • Patent number: 9281041
    Abstract: In one example, the disclosure is directed to a memory system comprising a control module. The memory system further includes a first circuit and a second circuit that each receives a control signal from the control module. Each circuit includes a resistor (MRAM element or a fixed resistor) and a capacitor situated between the resistor and a reference voltage. The first circuit is configured to output a data signal after the first capacitor is charged. The second circuit is configured to output a reference signal after the second capacitor is charged. The memory system further includes an arbiter configured to receive the data signal from the first circuit and the reference signal from the second circuit, determine whether the data signal arrived before the reference signal, and determine whether the MRAM is in a high or low state based on whether the data signal or the reference signal arrived first.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: March 8, 2016
    Assignee: Honeywell International Inc.
    Inventor: Michael A. Smith
  • Patent number: 9281042
    Abstract: A memory cell includes a bi-directional resistive memory element, a first transistor, and a capacitive element. The bi-directional resistive memory element has a first terminal directly connected to a first power rail and a second terminal coupled to an internal node. The first transistor has a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to one of the first power rail, a second power rail, or a read wordline. The capacitive element includes a first terminal coupled to the internal node and a second terminal coupled to the read wordline.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: March 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Perry H. Pelley, Frank K. Baker, Jr., Ravindraraj Ramaraju
  • Patent number: 9281043
    Abstract: An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 8, 2016
    Assignee: Intel Corporation
    Inventors: Pulkit Jain, Fatih Hamzaoglu, Liqiong Wei
  • Patent number: 9281044
    Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to faun a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: March 8, 2016
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: D. V. Nirmal Ramaswamy, Adam D. Johnson
  • Patent number: 9281045
    Abstract: A first data access request to a first row of a first memory array of the DRAM is received while a refresh operation in the first memory array is executing. The refresh operation is paused. The first data access request is executed, and simultaneously, the bits of the first row of the first memory array, including any updates indicated in the first data access request, are latched to a transfer register. The bits latched to the transfer register are written to a corresponding first row in a second memory array of the DRAM. A bank select logic is updated to indicate that subsequent data access requests to the first row in the first memory array will be executed from the second memory array. The refresh operation is then resumed.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: March 8, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Darren L. Anand, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan
  • Patent number: 9281046
    Abstract: A data processor includes a memory accessing agent and a memory controller. The memory accessing agent generates a plurality of accesses to a memory. The memory controller is coupled to the memory accessing agent and schedules the plurality of memory accesses in an order based on characteristics of the memory. The characteristics of the memory include a row cycle page time (tRCPAGE) indicative of an acceptable number of activate commands to a row in the memory within a predetermined time window.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: March 8, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Kevin M. Brandl
  • Patent number: 9281047
    Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: March 8, 2016
    Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
    Inventors: Jin-Ki Kim, HakJune Oh
  • Patent number: 9281048
    Abstract: A semiconductor memory device that includes a command decoder, a refresh controller, an oscillator and a delay unit. The command decoder generates a self refresh command, and the oscillator generates an oscillation signal. The refresh controller generates a refresh control signal and a recovery signal in response to the self refresh command and the oscillation signal. The delay unit transitions internal nodes included in the delay unit that are not transitioned during a refresh period in response to the refresh control signal and the recovery signal.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: March 8, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-Chul Kim, Yang-Ki Kim, Seong-Hwan Jeon
  • Patent number: 9281049
    Abstract: Systems, devices, and circuits for source-synchronous memory interfaces are disclosed. For example, a device includes a first NAND gate with an input for receiving a serial mode enable signal. In addition, the device also includes a second NAND gate with an input for receiving a forwarded strobe signal and an input for receiving an output of the first NAND gate. The device also includes a third NAND gate with an input for receiving a data strobe signal, and an XNOR gate with an input for receiving an output of the second NAND gate and an input for receiving an output of the third NAND gate.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: March 8, 2016
    Assignee: XILINX, INC.
    Inventors: Terence J. Magee, Jayant Mittal
  • Patent number: 9281050
    Abstract: A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses. A clock signal is provided to the plurality of DRAM devices. A read command and address to the plurality of DRAM devices on the command and address busses in synchronization with the clock signal. A read clock signal is provided to the plurality of DRAM devices to initiate a read operation in one of the plurality of DRAM devices that is selected by the address. The one DRAM device delays the read clock signal by an amount based on a speed of the one of the plurality of DRAM devices to generate. First delayed read clock and second delayed read clock signals are provided. The read data is received on the data bus in synchronization with the second delayed read clock signal.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: March 8, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Chikara Kondo
  • Patent number: 9281051
    Abstract: A semiconductor package may include a first die and a second die disposed adjacent to the first die. The semiconductor package may include a plurality of pads configured for receiving and outputting data mask addresses. The semiconductor package may include mapping blocks configured to map data mask signals among the first die, the second die, and the plurality of pads in response to a received address.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: March 8, 2016
    Assignee: SK Hynix Inc.
    Inventors: Kyu Bong Kong, Kwang Jin Na
  • Patent number: 9281052
    Abstract: Disclosed herein is a semiconductor device that includes: a frequency dividing circuit dividing a frequency of a first clock signal to generate second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal; a data input/output terminal; data buses; and a data input/output circuit coupled between the data input/output terminal and the data buses. The data input/output circuit includes a data output circuit and a data input circuit. The data output circuit outputs read data supplied in parallel from the data buses to the data input/output terminal in serial in synchronism with the third clock signal. The data input circuit outputs write data supplied in serial from the data input/output terminal to the data buses in parallel in synchronism with a predetermined one of the second clock signals.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: March 8, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventor: Yoshinori Matsui
  • Patent number: 9281053
    Abstract: A memory system (1) comprising a control logic (2) adapted to receive a number n of write requests (WRs) from input ports and to receive a read request (RR) from an output port within a clock cycle of a clock signal (CLK) applied to said memory system (1), wherein n is a natural number; and n+1 memory banks (4) of a shared memory (3) adapted to store data, wherein the control logic (2) is adapted to control a memory bank occupancy level MBOL of each memory bank (4) such that the differences between memory bank occupancy levels MBOLs of the memory banks (4) are minimized.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: March 8, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Rami Zecharia, Yaron Shachar
  • Patent number: 9281054
    Abstract: A static read-only memory (SRAM) includes one or more bit cell rows that each includes a collection of bit cells. Each bit cell row is coupled to two or more different wordlines, where each wordline associated with a given bit cell row provides memory access to a different subset of bit cells within that bit cell row.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: March 8, 2016
    Assignee: NVIDIA Corporation
    Inventors: Yongchang Huang, Jiping Ma, Xiangning Shi
  • Patent number: 9281055
    Abstract: A memory includes a number of storage elements connected to a pair of bit-lines, a bit-line pre-charging circuit, a sense amplifier connected to the pair of bit-lines through a column-select switch, a transition detection circuit connected to an output of the sense amplifier, and a local pre-charge control circuit connected to the transition detection circuit and having a local pre-charge control signal output connected to the bit-line pre-charging circuit.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: March 8, 2016
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Rahul Sahu, Dharmendra Kumar Rai
  • Patent number: 9281056
    Abstract: A static random access memory (SRAM) including a bit cell, wherein the bit cell includes at least two p-type pass gates. The SRAM further includes a bit line connected to the bit cell, and a bit line bar connected to the bit cell. The SRAM further includes a pre-discharge circuit connected to the bit line and to the bit line bar, wherein the pre-discharge circuit includes at least two n-type transistors. The SRAM further includes cross-coupled transistors connected to the bit line and to the bit line bar, wherein each transistor of the cross-coupled transistors is an n-type transistor. The SRAM further includes a write multiplexer connected to the bit line and to the bit line bar, wherein the write multiplexer includes two p-type transistors.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: March 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Wu, Wei Min Chan, Yen-Huei Chen, Hung-Jen Liao, Ping-Wei Wang
  • Patent number: 9281057
    Abstract: One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current that is provided to the memory cell and to generate a superconducting phase based on the stored digital state. The memory cell also includes a superconducting read-select device that is configured to implement a read operation in response to a read current that is provided to the memory cell. The memory cell further includes at least one Josephson junction configured to provide an output based on the superconducting phase of the PHMJJ during the read operation, the output corresponding to the stored digital state.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 8, 2016
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Anna Y. Herr, Quentin P. Herr, Andrew Hostetler Miklich
  • Patent number: 9281058
    Abstract: A semiconductor memory device may include a common source line controller configured to provide a channel current to a cell string via a common source line during a read operation and a page buffer configured to detect data stored in a selected memory cell by detecting a current of the bit line when the channel current is provided. The page buffer may selectively bias the bit line to maintain a voltage of the bit line to be the same as or higher than a reference voltage.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: March 8, 2016
    Assignee: SK Hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 9281059
    Abstract: A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: March 8, 2016
    Assignees: Opel Solar, Inc., The University of Connecticut
    Inventor: Geoff W. Taylor
  • Patent number: 9281060
    Abstract: A device is disclosed, comprising: a first layer including a first molecular network having a first 2D lattice structure, a second layer including a second molecular network having a second 2D lattice structure, wherein the first layer and the second layer are arranged at a distance from each other such that the first and the second molecular network interact electronically via molecular orbital interactions, and a rotation device implemented to rotate the first layer relative to the second layer by a rotation angle, wherein an electrical resistance between the first molecular network and the second molecular network changes as a function of the rotation angle.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Urs T. Duerig, Armin W. Knoll, Elad Koren, Emanuel Loertscher
  • Patent number: 9281061
    Abstract: Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (PCM). Current passing through a circuit including the memory cell to be programmed is mirrored in a scaled or unscaled manner, and provided as an input to the replica circuit. The replica circuit represents voltage drops that should be encountered when programming the memory cell. An input voltage is also provided to the replica circuit, which affects the voltage drop within the replica circuit that represents the voltage drop of the cell. The voltage drop across the replica circuit can then be mirrored and provided to bias the circuit including the memory cell.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 8, 2016
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Umberto Di Vincenzo, Simone Lombardo
  • Patent number: 9281062
    Abstract: Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: March 8, 2016
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Xiaonan Chen
  • Patent number: 9281063
    Abstract: Embodiments of the present invention provide a flash memory which has high operating efficiency and a longer service life, and relate to the field of electronic technologies. The flash memory includes a control circuit and a plurality of memory cells, where the memory cell is a floating-gate MOS transistor which includes a source, a gate, a drain, and a substrate; the control circuit is separately connected to the source, the gate, the drain, and the substrate and configured to output a control signal to them, so as to implement a bitwise overwrite operation on the memory cell; and the control circuit is further configured to generate a control signal when data stored by any one of the memory cells is 0, so that the memory cell overwrites the data stored by the memory cell from 0 to 1 according to the control signal.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: March 8, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Guangheng Xiang
  • Patent number: 9281064
    Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: March 8, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Marco Maccarrone, Giuseppe Giannini, Demetrio Pellicone
  • Patent number: 9281065
    Abstract: Technologies are generally described for low-power nonvolatile memory cells configured with select gates. A nonvolatile memory cell may have a transistor body, a select gate and a floating gate both coupled to the body, and a control gate coupled to the floating gate. Charge stored on the floating gate may indicate the data stored on the memory cell, and the control gate may be configured to adjust the charge stored on the floating gate. The select gate may be used to adjust the state of the transistor body to facilitate the adjustment of charge on the floating gate, and may also be used to render the memory cell unresponsive to the control gate.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: March 8, 2016
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Leonard Forbes
  • Patent number: 9281066
    Abstract: Memory devices facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values is equal to or greater than a particular value or a comparison of current levels compared with a reference current level is equal to or exceeds some threshold condition.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: March 8, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Brandon Lee Fernandes
  • Patent number: 9281067
    Abstract: A semiconductor test system includes a nonvolatile memory and a test device. The nonvolatile memory is configured to include an information region. The test device is configured to include a pin memory and a pin memory controller. The pin memory controller is configured to separate information data into a plurality of information data groups, sequentially transmit the separated plurality of information data groups to the pin memory, sequentially transmit the transmitted plurality of information data group in the pin memory to the nonvolatile memory, and program the transmitted plurality of information data group in the nonvolatile memory into the information region.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong Gab Lee, Mansik Choi, Byoungwoo Ye
  • Patent number: 9281068
    Abstract: A method of reprogramming a nonvolatile memory device, comprising setting up bit lines of selected memory cells according to logic values of first and second latches of a page buffer connected to the bit lines, supplying a program pulse to the selected memory cells, performing a program verify operation on the selected memory cells using the first and second latches, and performing a predictive program operation on the selected memory cells according to a result of the program verify operation. In the predictive program operation, bit lines of the selected memory cells are setup according to a logic value of a third latch of the page buffer that corresponds to each of the selected memory cells.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-Young Kim
  • Patent number: 9281069
    Abstract: In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: March 8, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-Suc Jang, Dong-Hun Kwak
  • Patent number: 9281070
    Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Taeck Jung, Junghoon Park
  • Patent number: 9281071
    Abstract: In general, according to one embodiment, a semiconductor memory device includes a first transistor, a plurality of memory cells and a controller. One end of the first transistor is electrically connected to a first power supply. The plurality of memory cells are electrically connected between other end of the first transistor and a second power supply. The controller is configured to apply a first voltage to a gate of the first transistor when reading data from a selected memory cell. The controller is configured to make the first voltage progressively-increasing.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 8, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsumi Abe, Masahiro Yoshihara
  • Patent number: 9281072
    Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: March 8, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyeong-Han Lee, Seok-Cheon Kwon, Dong-Yang Lee
  • Patent number: 9281073
    Abstract: Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: March 8, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Akira Goda
  • Patent number: 9281074
    Abstract: The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: March 8, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Meng-Yi Wu, Chih-Hao Huang, Hsin-Ming Chen
  • Patent number: 9281075
    Abstract: The memory programming apparatus includes a memory reader configured to read a read data in a plurality of cells related with an address of a programmable memory; and a memory writer configured to record a write data on the plurality of cells to compare the write data with the read data, to generate a re-writing pattern, and to correct at least one mismatch cell among the plurality of cells. Accordingly, it may be possible to reduce a programming processing time and to increase a yield rate.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: March 8, 2016
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Beomseon Ryu, Taeil Yun, Daeyoung Yoo
  • Patent number: 9281076
    Abstract: A semiconductor device has an antifuse element and a measurement unit. The antifuse element stores information according to whether the antifuse element is in the broken or unbroken state. The measurement unit determines a resistance value related to the resistance value of the broken antifuse element.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: March 8, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Naohisa Nishioka
  • Patent number: 9281077
    Abstract: A shift register includes series-connection circuits to transmit a shift pulse. The series-connection circuits include a continuous stage group with continuous stages. Each stage of the continuous stage group includes a first output transistor, a first capacitor, an input gate, a first switching element, a second switching element, a third switching element, and a fourth switching element.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: March 8, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Nakamizo, Masashi Yonemaru, Kenichi Ishii, Yasuaki Iwase
  • Patent number: 9281078
    Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: March 8, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
  • Patent number: 9281079
    Abstract: An apparatus for detecting hard errors in a circuit includes a storage device and a processing circuit. The storage has stored therein test data and normal data. The processing circuit includes combinational logic in series with at least one set of input latches and at least one set of output latches. The apparatus includes a test control module configured to control the processing circuit to halt a flow of normal data through the processing circuit and run the test data through the processing circuit while subjecting the processing circuit to a stress condition.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alan Gara, Hans M. Jacobson
  • Patent number: 9281080
    Abstract: A system for testing a device under test (DUT) includes a test controller unit that includes a first memory operable to store a data pattern; a bridge circuit that includes a second memory that is smaller than the first memory, and a functional unit that includes a third memory that is smaller than the second memory. Portions of the data pattern are selectively transferred from the first memory to the second memory during and for DUT testing operations. The functional circuit interfaces with the DUT for testing. Portions of the data pattern are selectively transferred from the second memory to the third memory for application to the DUT.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: March 8, 2016
    Assignee: ADVANTEST CORPORATION
    Inventors: Michael Jones, Edmundo Delapuente, Alan S. Krech, Jr.
  • Patent number: 9281081
    Abstract: A semiconductor apparatus includes first and second address buffer groups. The first address buffer group receives first address signals from an external source and outputs the first address signals to a first internal circuit, in first and second operation modes. The second address buffer group receives second address signals from the external source and outputs the second address signals to the first internal circuit, in the first operation mode, and receives third address signals which are generated in a second internal circuit and outputs the third address signals to the first internal circuit, in the second operation mode.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: March 8, 2016
    Assignee: SK Hynix Inc.
    Inventor: Tae Jin Kang
  • Patent number: 9281082
    Abstract: Disclosed herein is a fuse circuit including a storage unit capable of storing defective address information corresponding to mat information when a boot-up operation is performed, a driving control unit coupled between the storage unit and a first power source terminal, and capable of forming a current path between the storage unit and the first power source terminal in response to the defective address information transferred through a first data line and the mat information transferred through a second data line while blocking the current path between the storage unit and the first power source terminal when a normal operation is performed, and an output unit capable of outputting the defective address information stored in the storage unit when the normal operation is performed.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: March 8, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Yub Lee, Sung-Soo Chi
  • Patent number: 9281083
    Abstract: A traveling wave nuclear fission reactor, fuel assembly, and a method of controlling burnup therein. In a traveling wave nuclear fission reactor, a nuclear fission reactor fuel assembly comprises a plurality of nuclear fission fuel rods that are exposed to a deflagration wave burnfront that, in turn, travels through the fuel rods. The excess reactivity is controlled by a plurality of movable neutron absorber structures that are selectively inserted into and withdrawn from the fuel assembly in order to control the excess reactivity and thus the location, speed and shape of the burnfront. Controlling location, speed and shape of the burnfront manages neutron fluence seen by fuel assembly structural materials in order to reduce risk of temperature and irradiation damage to the structural materials.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: March 8, 2016
    Assignee: TerraPower, LLC
    Inventors: Charles E. Ahlfeld, John Rogers Gilleland, Roderick A. Hyde, Muriel Y. Ishikawa, David G. McAlees, Nathan P. Myhrvold, Charles Whitmer, Lowell L. Wood, Jr., George B. Zimmerman
  • Patent number: 9281084
    Abstract: A motor stand of a primary motor-driven pump unit of a pressurized water nuclear reactor comprises an upper flange and fixing means suited to ensure the fixing of transverse holding means of the said primary motor-driven pump unit, the said primary motor-driven pump unit comprising an electric motor having a lower flange suited to be integrated with the said upper flange of the said motor stand. The motor stand is characterized in that the said fixing means comprise an annular element resting on the said upper flange of the said motor stand suited to be flanged between the said upper flange of the said motor stand and the said lower flange of the said motor, the said fixing means comprising at least one radial excrescence in which there is arranged a space suited to receive the said holding means.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: March 8, 2016
    Assignee: AREVA NP
    Inventor: Olivier Philippart
  • Patent number: 9281085
    Abstract: A method of repairing a connection between a first nozzle and a closed vessel includes cutting through an entire thickness of the first nozzle at a location adjacent to the mid-wall of the vessel. A portion of the first nozzle is removed. A replacement nozzle is disposed in a void formed by removal of the portion of the first nozzle. A weld is formed between the replacement nozzle and a surface of the mid-wall of the vessel.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: March 8, 2016
    Assignee: AZZ WSI LLC
    Inventors: Peter Charles Riccardella, Pedro Ernesto Amador
  • Patent number: 9281087
    Abstract: A mobile boration system (60) has a number of components that are mobile and include a water source (10), H2BO3 powder supply (14), a mixer to mix the solution (20) capable of providing a boric acid solution (30) with minimal air entrainment and optional heat exchanger(s) (12), and wherein the system (60) is capable of transport to a nuclear power plant facility by land, sea or air, rather than being in place in a large vulnerable footprint.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: March 8, 2016
    Assignee: Westinghouse Electric Company LLC
    Inventors: Stephen R. Swantner, Ryan T. Vanston, Robert S. Fournier
  • Patent number: 9281088
    Abstract: In a nuclear installation, an instrument includes a sensor module connected to a process flange. The sensor module includes a support conduit with support conduit threads. An electronic circuit is wired to a connector that includes a key that is aligned with field circuit contacts of the connector. A thermal and nuclear radiation shield encloses the electronic circuit and includes a shock protection annulus. The connector is secured inside the shock protection annulus. The thermal and nuclear radiation shield includes shield threads that rotatably engage the support conduit threads to rotate an alignment of the key relative to the process flange.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: March 8, 2016
    Assignee: Rosemount Inc.
    Inventors: Jeffery D. Chivers, Daniel A. Norberg
  • Patent number: 9281089
    Abstract: A method and apparatus for using a parent radionuclide. The apparatus includes a radiation impervious case, a vial disposed within the case, a stopper with a central bore, the central bore aligned at an oblique angle with respect to the case so that a straight line through the central bore does not pass through any part of the vial and a curved tube that connects the central bore of the stopper and a cap of the vial.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 8, 2016
    Assignee: NorthStar Medical Radioisotopes LLC
    Inventor: Glenn H. Isensee
  • Patent number: 9281090
    Abstract: Packaging for transporting radioactive material (1) comprising a radiation protection structure (4) comprising a shielding portion (5) defining a cavity (2) to house the radioactive material and a portion (7) having the effect of distancing the radioactive material from the outside of the packaging. The distancing-effect portion (7) directly encloses the shielding portion (5). The protection structure (4) has a thickness e associated with a segment (S) connecting a point (B) on the outer surface of the packaging to the center of gravity (G) of the cavity (2). It satisfies for any point (B): e=e1+e2 and 0.05<e1/e<0.25, where e1 is the thickness of the shielding portion (5), e2 is the thickness of the distancing-effect portion (7), with e1, e2 associated with the segment (S). The shielding portion (5) has a mean density of more than 8, the distancing-effect portion has a mean density of less than 0.5.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 8, 2016
    Assignee: TN INTERNATIONAL
    Inventors: Gilda Leleu, Kévin Massif
  • Patent number: 9281091
    Abstract: Methods and article for optically trapping nano-sized objects by illuminating a coaxial plasmonic aperture are disclosed.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: March 8, 2016
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Jennifer Anne Dionne, Amr Ahmed Essawi Saleh