Abstract: A trench structure which is capable of promoting extension of a depletion layer and hardly causes thermal stress is provided. A semiconductor device includes a semiconductor substrate. A plurality of loop trenches is formed on the surface of the semiconductor substrate. Each loop trench is configured to extend so as to surround a region smaller than the region where a plurality of gate trenches is formed. Each loop trench is separated from other loop trenches. A second insulating layer is located in each loop trench. P-type fourth regions are formed in the semiconductor substrate. Each fourth region is in contact with a bottom surface of corresponding one of the loop trenches and is configured to extend along the corresponding one of the loop trenches.

Abstract: A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

Abstract: A fin field effect transistor (FinFET) and a method of forming the same are introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. A part of the substrate is doped and a region of high dopant concentration and a region of low dopant concentration are formed. Gate stacks are formed, portions of the fins are removed and source/drain regions are epitaxially grown in the regions of high/low dopant concentration. Contacts are formed to provide electrical contacts to source/gate/drain regions.

Abstract: A method of fabricating a semiconductor device with fin-shaped structures includes respectively forming first fin-shaped structures in a first region and a second region of a semiconductor substrate, depositing a dielectric layer to completely cover the first fin-shaped structures, removing the first fin-shaped structures in the second region so as to form trenches in the dielectric layer, and performing an in-situ doping epitaxial growth process so as to respectively form second fin-shaped structures in the trenches.

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

Abstract: There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.

Abstract: There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield. Processing for partially reducing contact property between a first material layer (11) and a second material layer (12) (laser light irradiation, pressure application, or the like) is performed before peeling, and then peeling is conducted by physical means. Therefore, sufficient separation can be easily conducted in an inner portion of the second material layer (12) or an interface thereof.

Abstract: A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate.

Abstract: A bottom-gate transistor with a short channel length and a method for manufacturing the transistor are provided. A bottom-gate transistor with a short channel length in which portions of a source electrode and a drain electrode which are proximate to a channel formation region are thinner than other portions thereof was devised. In addition, the portions of the source electrode and the drain electrode which are proximate to the channel formation region are formed in a later step than the other portions thereof, whereby a bottom-gate transistor with a short channel length can be manufactured.

Abstract: A method of fabricating a thin-film transistor substrate includes disposing an oxide semiconductor layer on an insulating substrate, performing a thermal treatment process to the oxide semiconductor layer, providing an alignment mark, a source electrode, a drain electrode, and an oxide semiconductor pattern, after the thermal treatment process, providing a gate electrode, after the thermal treatment process, and providing a pixel electrode connected to the drain electrode.

Abstract: Reducing hydrogen concentration in a channel formation region of an oxide semiconductor is important in stabilizing threshold voltage of a transistor including an oxide semiconductor and improving reliability. Hence, hydrogen is attracted from the oxide semiconductor and trapped in a region of an insulating film which overlaps with a source region and a drain region of the oxide semiconductor. Impurities such as argon, nitrogen, carbon, phosphorus, or boron are added to the region of the insulating film which overlaps with the source region and the drain region of the oxide semiconductor, thereby generating a defect. Hydrogen in the oxide semiconductor is attracted to the defect in the insulating film. The defect in the insulating film is stabilized by the presence of hydrogen.

Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.

Abstract: A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm.

Abstract: A method for manufacturing a semiconductor device including an oxide semiconductor includes the steps of forming an oxide semiconductor film, forming a gate insulating film provided over the oxide semiconductor film, forming a gate electrode in contact with the gate insulating film, a sidewall insulating film in contact with the gate electrode, and forming a source electrode and a drain electrode in contact with the oxide semiconductor film. In the method, the gate insulating film and the sidewall insulating film are formed at a temperature at which oxygen contained in the oxide semiconductor film is inhibited from being eliminated, preferably at a temperature lower than a temperature at which oxygen contained in the oxide semiconductor film is eliminated.

Abstract: A thin film transistor is disclosed in the present invention, including a substrate, a gate, an insulating layer, a source, a drain and an active layer. The gate is arranged on the substrate. The insulating layer is arranged on the gate. The source and the drain are arranged on the insulating layer. The active layer is arranged between the source and the drain, and is formed by a bottom layer, an intermediate layer and a top layer stacked together on the insulating layer. The conductivity of the intermediate layer is higher than that of the bottom layer, and the conductivity of the bottom layer is higher than that of the top layer. As such, the disadvantage of low carrier mobility as commonly seen in the conventional thin film transistor is overcome.

Abstract: An insulating film is provided over one surface of a first semiconductor layer including a first oxide semiconductor including indium as a main component, and a second semiconductor layer including an i-type second oxide semiconductor is provided in contact with the other surface. The energy difference between a vacuum level and a Fermi level in the second oxide semiconductor is larger than that in the first oxide semiconductor. In the first semiconductor layer, a region in the vicinity of the junction surface with the second oxide semiconductor which satisfies the above condition is a region having an extremely low carrier concentration (a quasi-i-type region). By using the region as a channel, the off-state current can be reduced. Further, a drain current of the FET flows through the first oxide semiconductor having a high mobility; accordingly, a large amount of current can be extracted.

Abstract: An enhancement mode device includes a floating gate structure. The floating gate structure includes a first bottom dielectric layer, a second bottom dielectric layer on the first bottom dielectric layer and a conductive floating gate on the second bottom dielectric layer.

Abstract: According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.

Abstract: Sensors, sensing arrangements and devices, and related methods are provided. In accordance with an example embodiment, an impedance-based sensor includes a flexible dielectric material and generates an output based on pressure applied to the dielectric material and a resulting compression thereof. In certain embodiments, the dielectric material includes a plurality of regions separated by gaps and configured to elastically deform and recover in response to applied pressure.

Abstract: A Schottky diode includes first and second trenches formed in a semiconductor layer where the first and second trenches are lined with a thin dielectric layer and filled partially with a trench conductor layer with the remaining portion being filled with a first dielectric layer. Well regions are formed spaced-apart in a top portion of the semiconductor layer between the first and second trenches. A Schottky metal layer is formed on a top surface of the semiconductor layer between the first and second trenches. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.

Abstract: A semiconductor device includes a first active layer disposed over a substrate. The second active layer is disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. The first electrode establishes a Schottky junction with the second active layer. The first electrode includes a first electrode pad and a first series of fingers in electrical contact with the first electrode pad. The second electrode establishes an ohmic junction with the first active layer. The second electrode includes a second electrode pad and a second series of fingers in electrical contact with the second electrode pad. The first and second series of electrode fingers form an interdigitated pattern. The first electrode pad is located over the first and second series of electrode fingers.

Abstract: A capacitor includes an active layer, a gate insulation layer on the active layer, a gate electrode on the gate insulation layer, an interlayer insulating layer on the gate electrode, and a first electrode on the interlayer insulating layer and connected to the active layer through at least one contact hole.

Abstract: In one embodiment, a solar cell installation includes several groups of solar cells. Each group of solar cells has a local power point optimizer configured to control power generation of the group. The local power point optimizer may be configured to determine an optimum operating condition for a corresponding group of solar cells. The local power point optimizer may adjust the operating condition of the group to the optimum operating condition by modulating a transistor, such as by pulse width modulation, to electrically connect and disconnect the group from the installation. The local power point optimizer may be used in conjunction with a global maximum power point tracking module.

Abstract: A chemical vapor deposited film includes silicon atoms, oxygen atoms, carbon atoms, and hydrogen atoms. The chemical vapor deposited film is formed by a plasma CVD method such that the concentration of the oxygen atoms is 10-35% by element.

Abstract: A conductive reflective film has a silver nanoparticle-sintered film with a surface coating composition containing a hydrolysate of a metal alkoxide wet-coated thereto. The coated film is then fired. Also provided is a method of manufacturing the conductive reflective film comprising the steps of coating a surface coating composition containing a hydrolysate of a metal alkoxide on a silver nanoparticle-sintered film using a wet coating method, and firing the silver nanoparticle-sintered film having the coated film. The conductive reflective film provides improved adhesion properties with respect to a base material while maintaining a high reflectivity and a high conductivity of a silver nanoparticle-sintered film.

Abstract: A method includes obtaining a photosensor substrate (236) having two opposing major surfaces. One of the two opposing major surfaces includes at least one photosensor row (230) of at least one photosensor element (232, 234), and the obtained photosensor substrate has a thickness equal to or greater than one hundred microns. The method further includes optically coupling a scintillator array (310) to the photosensor substrate. The scintillator array includes at least one complementary scintillator row (224) of at least one complementary scintillator element (226, 228), and the at least one complementary scintillator row is optically coupled to the at least one photosensor row (230) and the at least one complementary scintillator element is optically coupled to the at least one photosensor element.

Abstract: An image pickup apparatus includes: a cover glass portion having a function of a right angle prism; an image pickup device substrate portion including an image pickup device on a first principal surface and a back-face electrode on a second principal surface, the back-face electrode being connected to the image pickup device via a through-wiring; and a bonding layer that bonds the cover glass portion and the image pickup device substrate portion that have a same outer dimension.

Abstract: An electromagnetic energy concentrator uses a prism and waveguide with a gap layer of uniform thickness disposed between the prism and a first surface of waveguide. Energy detectors, which may be photovoltaics or miniaturized antenna elements are disposed adjacent to and co-extensive with a second surface of the waveguide. The detectors operate in each of at least two bands; a distance between detectors operating in a given band depends on a wavelength in the given band.

Abstract: A method for producing a semiconductor component is disclosed. A carrier substrate includes a mounting region and an opening, which is formed in the mounting region of the carrier substrate. After mounting a semiconductor chip, an electrically insulating layer is applied to the carrier substrate in such a way that the electrically insulating layer completely fills the first opening in the carrier substrate. A second opening is formed in the electrically insulating layer. An electrically conductive layer is then applied to the electrically insulating layer in such a way that the second opening is filled with the electrically conductive layer in the form of a via. A semiconductor component produced in this way is also provided.

Abstract: Certain exemplary embodiments can provide a method, which can comprise fabricating a system. The system can comprise a light amplification element and a charge transport element. Each of the light amplification element and a charge transport element can comprise one or more of a graphene layer, graphene oxide, graphene nano platelets, functionalized graphene, graphene/superconductor composite, tubular shaped nano carbon, semiconductor powder, thin film, nano wire, and nano rod.

Abstract: An infrared photodiode that is a semiconductor device includes a substrate, a buffer layer formed of GaSb, and an absorption layer including a multiple quantum well structure. The multiple quantum well structure includes a stack of unit structures each including a plurality of component layers. Each unit structure includes a first component layer formed of InAs1-aSba where the ratio a is 0 or more and 0.05 or less, a second component layer formed of GaSb, and a third component layer formed of InSbxAs1-x where the ratio x is more than 0 and less than 1. The third component layer is disposed so as to be in contact with one main surface of the second component layer. The other main surface of the second component layer is in contact with the first component layer within the unit structure. The third component layer has a thickness of 0.1 nm or more and 0.9 nm or less.

Abstract: A mounting system for mounting photovoltaic panels on a support structure. The mounting system comprises photovoltaic panel frames in which the photovoltaic panels are mounted, panel support rails, and mounting brackets or cross beams for supporting the panel support rails. The panel frames have inwardly extending panel frame extensions on their back side. The panel support rails are mounted on the support structure with either pivoting brackets or cross beams. In either case, the support rails have pairs of stationary clamps and movable clamps with clamp lips that engage the panel frame extensions of the panel frames.

Abstract: A solar cell module includes interconnected solar cells, a transparent cover over the front sides of the solar cells, and a backsheet on the backsides of the solar cells. The solar cell module includes an electrical insulator between the transparent cover and the front sides of the solar cells. An encapsulant protectively packages the solar cells. To prevent polarization, the insulator has resistance suitable to prevent charge from leaking from the front sides of the solar cells to other portions of the solar cell module by way of the transparent cover. The insulator may be attached (e.g., by coating) directly on an underside of the transparent cover or be a separate layer formed between layers of the encapsulant. The solar cells may be back junction solar cells.

Abstract: A method for manufacturing a composite insulated panel (1) comprising the steps of: providing a first sheet (2); cutting a hole (7) in the first sheet (2) to accommodate a photovoltaic solar collector module (8); inserting the solar collector module (8) into the cut-out hole; sealing the solar collector module to the first sheet (2); providing a second sheet (3), the second sheet having an opening therein to receive a connector housing (22); leading electrical connections from the solar collector module through the connector housing; and providing a body (4) of insulating material between the inner face of the second sheet and the inner face of the first sheet and the inner face of the photovoltaic solar collector module.

Abstract: A power generating system is disclosed. The power generating system comprises a solar cell, a support structure coupled to the solar cell and adapted to adjust the position of the solar cell, a first thermal sensor coupled to the solar cell and adapted to detect a first temperature at a first location on the solar cell, a second thermal sensor coupled to the solar cell and adapted to detect a second temperature at a second location on the solar cell, the second location spaced apart from the first location, and a control system. The control system is adapted to receive a first signal from the first thermal sensor and a second signal from the second thermal sensor, compare information conveyed in the first and second signals, and adjust the position of the solar cell by operating the support structure in response to information conveyed in the first and second signals.

Abstract: A photoelectric conversion element includes a PN junction formed between an N-type oxide layer and a P-type oxide layer, in which the N-type oxide layer is formed of an oxide having a perovskite structure containing titanium and strontium, a part of strontium is substituted with a +3 valence metal element or a part of titanium is substituted with a +5 valence metal element, and the amount of the metal element substituted in the N-type oxide layer is 0.01 mass % to 0.75 mass %.

Abstract: A method of manufacturing photo-semiconductor device that has a photoconductive semiconductor film provided with electrodes and formed on a second substrate, the semiconductor film being formed by epitaxial growth on a first semiconductor substrate different from the second substrate, the second substrate being also provided with electrodes, the electrodes of the second substrate and the electrodes of the photoconductive semiconductor film being held in contact with each other.

Abstract: A method of forming infra red detector arrays is described, starting with the manufacture of a wafer. The wafer is formed from a GaAs or GaAs/Si substrate having CMT deposited thereon by MOVPE. The CMT deposited can include a number of layers of differing composition, the composition being controlled during the MOVPE process and being dependent on the thickness of the layer deposited. A CdTe buffer layer can aid deposition of the CMT on the substrate. Once the wafer is formed, the buffer layer, an etch stop layer and any intervening layers can be etched away leaving a wafer suitable for further processing into an infra red detector.

Abstract: Light to current converter devices, such as solar cells, are disclosed. The devices may include via holes extending through the cell substrate and may include through-hole electrodes within the via holes. The through-hole electrodes may be made from one or more materials and may be hollow, partially hollow, or fully filled. Front and rear electrodes may also be formed on the device and can be made of the same or different materials as the through-hole electrode. The devices may include emitters located only on the top surface of the cell, located on the top surface and symmetrically or asymmetrically along a portion of the inner surface of the via holes, or located on the top surface and full inner surface of the via holes. Processes for making light to current converter devices are also disclosed.

Abstract: One embodiment of the present invention provides a sputtering system for large-scale fabrication of solar cells. The sputtering system includes a reaction chamber, a rotary target situated inside the reaction chamber which is capable of rotating about a longitudinal axis, and an RF power source coupled to at least one end of the rotary target to enable RF sputtering. The length of the rotary target is between 0.5 and 5 meters.

Abstract: Disclosed are a light emitting device, a method of fabricating the light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, an electron blocking layer on the active layer, and a second conductive semiconductor layer on the electron blocking layer. The electron blocking layer includes a first electron blocking layer and an interrupted diffusion layer on the first electron blocking layer.

Abstract: A group III element nitride single crystal is grown on a template immersed in a raw material liquid retained in a crucible and containing a group III material and one of an alkali metal and an alkali earth metal. The raw material liquid remaining after the growth of the single crystal is cooled and solidified, and by feeding a hydroxyl group-containing solution into the crucible, the solidified raw material is removed from around the template, and thus the group III element nitride single crystal is taken out from inside the solidified raw material. The template is disposed at a position away from the bottom of the crucible.

Abstract: A nitride semiconductor element 1 includes a base structure part 5, and an element structure part 11 formed on the base structure part 5 and having at least an n-type AlGaN based semiconductor layer 6, and p-type AlGaN based semiconductor layers 8, 9, 10, and further includes an n-electrode contact part 13a formed on the n-type AlGaN based semiconductor layer 6, an n-electrode pad part 13b formed on the n-electrode contact part 13a, and a p-electrode 12 formed on the p-type AlGaN based semiconductor layers 8, 9, 10, in which an AlN mole fraction in the n-type AlGaN based semiconductor layer 6 is 20% or more, the n-electrode contact part 13a includes one or more metal layers, and the p-electrode 12 and the n-electrode pad part 13b have a common laminated structure of two or more layers having an Au layer as an uppermost layer, and an Au diffusion preventing layer composed of conductive metal oxide and formed under the uppermost layer to prevent Au diffusion.

Abstract: This invention provides an electroluminescence device comprising an indirect bandgap semiconductor layer, such as silicon or germanium, having a local conduction-band minimum at the ?-point in an E-k diagram for using as a light emitting layer, and a direct bandgap semiconductor layer formed by a heterojunction on the indirect bandgap semiconductor layer for using as an electron supply means transporting electrons from a ?-valley to a ?-valley when a forward-biased voltage is applied, wherein a light emission is occurred by recombining the electrons transported to the ?-valley of the indirect bandgap semiconductor layer with holes located at a valance band maximum of the indirect bandgap semiconductor layer.

Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.

Abstract: A light emitting diode (LED) device includes a semiconductor nanowire core, and an In(Al)GaN active region quantum well shell located radially around the semiconductor nanowire core. The active quantum well shell contains indium rich regions having at least 5 atomic percent higher indium content than indium poor regions in the same shell. The active region quantum well shell has a non-uniform surface profile having at least 3 peaks. Each of the at least 3 peaks is separated from an adjacent one of the at least 3 peaks by a valley, and each of the at least 3 peaks extends at least 2 nm in a radial direction away from an adjacent valley.

Abstract: The application provides a light-emitting diode array, including: a first light-emitting diode including a first area; a second area; a first isolation path between the first area and the second area, and the first isolation path including an electrode isolation layer; and an electrode contact layer covering the first area; a second light-emitting diode including a semiconductor stack layer; and a second electrical bonding pad on the semiconductor stack layer; and a second isolation path between the first light-emitting diode and the second light-emitting diode, wherein the second isolation path includes an electrical connecting structure electrically connected to the first light-emitting diode and the second light-emitting diode.

Abstract: A light emitting device includes a light emitting layer, a substrate that is transparent to an emission wavelength of the light emitting layer and positioned to receive an emission wavelength from the light emitting layer, a convex pattern including a collection of a plurality of convex portions discretely arranged on a front surface of the substrate with a first pitch, an n type nitride semiconductor layer located on the front surface of the substrate to cover the convex pattern and a p type nitride semiconductor layer located on the light emitting layer. The light emitting layer is located on the n type semiconductor layer. Each of the convex portions includes a sub convex pattern comprising a plurality of fine convex portions discretely formed at the top of the convex portion with a second pitch smaller than the first pitch, and a base supporting the sub convex pattern.

Abstract: An LED includes a mesa having a Group III Nitride mesa face and a mesa sidewall, on an underlying LED structure. The mesa face includes Group III Nitride surface features having tops that are defined by mask features, having bottoms, and having sides that extend along crystal planes of the Group III Nitride. The mask features may include a two-dimensional array of dots that are spaced apart from one another. Related fabrication methods are also disclosed.