Abstract: A method of controlling a resistive switching memory cell can include: receiving a first command to be executed on the resistive switching memory cell; performing, in response to the first command, an erase operation to erase the resistive switching memory cell to an erased state; verifying the erased state of the resistive switching memory cell; performing a weak program operation to program the resistive switching memory cell to a first programmed state; and verifying the first programmed state of the resistive switching memory cell.

Abstract: Device selection schemes in multi-chip package NAND flash memory systems are provided. A memory system is provided that has a memory controller, and a number of memory devices connected to the controller via a common bus with a multi-drop connection. The memory controller performs device selection by command. A corresponding memory controller is provided which performs device selection by command. Alternatively, device selection is performed by address. A memory device is provided use in memory system comprising a memory controller, and a number of memory devices inclusive of the memory device connected to the controller via a common bus with a multi-drop connection. The memory device has a register containing a device identifier, and a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match. The memory device is selected if the device identifier comparator determines there is a match.

Abstract: A monolithic three dimensional NAND string including a stack of alternating first material layers and second material layers different from the first material layers over a major surface of a substrate. The first material layers include a plurality of control gate electrodes and the second material layers include an insulating material and the plurality of control gate electrodes extend in a first direction. The NAND string also includes a semiconductor channel, a blocking dielectric, and a plurality of vertically spaced apart floating gates. Each of the plurality of vertically spaced apart floating gates or each of the second material layers includes a first portion having a first thickness in the second direction, and a second portion adjacent to the first portion in the first direction and having a second thickness in the second direction which is different than the first thickness.

Abstract: A memory cell including a drain, a channel, and a floating gate. The channel surrounds the drain and includes a first rounded closed curve structure around the drain. The floating gate is situated over the channel and includes a second rounded closed curve structure over the channel.

Abstract: A nonvolatile memory device includes a first memory cell group connected to a first word line and a first bit line group, a second memory cell group connected to the first word line and a second bit line groups (BLGs), a control logic that performs first and second program operations on the first and second memory cell groups, respectively, performs a verification operation on the first memory cell group by pre-charging bit lines in the first and second BLGs at a same time to verify the first program operation, and a verification operation on the second memory cell group by pre-charging the bit lines in the first and second BLGs at a same time to verify the second program operation, and performs a read operation on at least one of the first and second memory cell groups by simultaneously pre-charging the bit lines in the first and second BLGs.

Abstract: A nonvolatile memory device, including a first latch unit and a nonvolatile memory cell, and a method of writing data in a nonvolatile memory device are provided. The method includes receiving a first writing command or a second writing command from outside of the nonvolatile memory device, and writing first data stored in the first latch unit in the nonvolatile memory cell in response to the first or second writing command. The first data is retained in the first latch unit until the writing of the first data stored in the first latch unit in the nonvolatile memory cell is completed.

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract: The present invention provides methods and associated devices for controlling the voltage threshold distribution corresponding to performing a function on cells of non-volatile memory device. In one embodiment, a method is provided. The method may comprise providing the non-volatile memory device. The device comprises one or more strings, each string comprising a plurality of cells, the plurality of cells comprising a first cell and a second cell. The method further comprises performing a function of the non-volatile memory device by applying a first function voltage to the first cell and a second function voltage to the second cell. The first function voltage and the second function voltage are different.

Abstract: A memory cell includes a floating gate transistor, a word line transistor, a first capacitance element, and a second capacitance element. The floating gate transistor has a first terminal for receiving a bit line signal, a second terminal, and a floating gate. The word line transistor has a first terminal coupled to the second terminal of the floating gate transistor, a second terminal for receiving a third voltage, and a control terminal for receiving a word line signal. A voltage passing device is for outputting a second voltage during an inhibit operation and a first voltage during a program operation or an erase operation. The first capacitance element is coupled to the first voltage passing device and the floating gate, and for receiving a first control signal. The second capacitance element is for receiving at a second control signal.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.

Abstract: A semiconductor memory device includes memory cells, word lines that are electrically connected to gates of the memory cells, a source line that is electrically connected to one end of the memory cells, and a controller that executes a read operation over first, second, third, and fourth time periods. A first voltage is applied to a selected word line during the first and second time periods of the first operation, and a second voltage that is higher than the first voltage is applied to the selected word line during the third and fourth time periods of the second operation. A third voltage is applied to the source line during the first and third time periods, and fourth and fifth voltages that are lower than the third voltage are applied to the source line during the second and fourth time periods, respectively.

Abstract: A semiconductor memory device according to an embodiment includes a connecting portion having a first region between a memory cell array and a sense amplifier portion and including transistors in the first region, one of the transistors having a first terminal electrically connected to a certain memory cell and a second terminal electrically connected to the sense amplifier portion, the connecting portion including: a first transistor group configured from transistors aligned in a first direction, the first direction being as their channel width direction; and a second transistor group configured from transistors aligned in a second direction intersecting the first direction, the second direction being as their channel width direction, and one of the first terminals of the transistors of the second transistor group being disposed more inside of the first region than one of the second terminals of the transistors of the second transistor group.

Abstract: A semiconductor memory device includes a memory cell, a sense amplifier electrically connected to the memory cell, the sense amplifier including a node for sensing a voltage during a sense operation and a data latch electrically connected to the node and configured to hold a first voltage corresponding to a voltage of the node when a strobe signal is issued during a strobe operation, and a controller configured to raise the voltage of the node during the strobe operation before the strobe signal is issued.

Abstract: A method for wear reduction of a flash memory module, the method may include reading data stored in a group of flash memory cells to provide a read data; wherein the reading comprise supplying a bias voltage that is lower than a write bias voltage; wherein the write bias voltage was supplied to the group of flash memory cells during a writing of the data to the group of flash memory cells; and decoding the read data, by applying a decoding process of a given complexity, to provide decoded data.

Abstract: A method for operating a data storage device using, as a storage medium, a nonvolatile memory device including a memory cell array which is constructed by pages including data cells and flag cells for storing whether upper bit (MSB) data is stored in a data cell, includes searching a last programmed page in the case where recovery is made from a power failure to a normal state; determining whether the last programmed page is an upper bit (MSB) page to be accessed to store upper bit (MSB) data; and adjusting a flag cell read voltage for reading flag cells, in the case where the last programmed page is an upper bit (MSB) page.

Abstract: A semiconductor memory device includes a plurality of string units, each of which includes a plurality of strings of memory cells connected in series, a controller configured to perform an erase operation on the string units, the erase operation including an erase verify operation that is performed per string unit, and a control circuit including a register that stores erase characteristic for at least one of the string units. The control circuit is configured to output the erase characteristic in response to a command from a memory controller.

Abstract: There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a source select transistor and a drain select transistor, a peripheral circuit for performing a program operation on the memory cell array, and a control logic for controlling the peripheral circuit such that the potential level of a source control voltage applied to the source select transistor as a selected memory cell is closer to the drain select transistor in a program verify operation during the program operation.

Abstract: A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to determine a first shaping level corresponding to applying a first shaping operation to data to be stored to the non-volatile memory. The controller is further configured to, in response to the first shaping level exceeding a threshold, perform a second shaping operation to generate shaped data that corresponds to the data, the shaped data having a second shaping level that is less than the threshold.

Abstract: A one-time programmable (OTP) memory device includes a memory cell array including a plurality of OTP memory cells, the plurality of OTP memory cells being connected to a plurality of bitlines, a plurality of voltage wordlines and a plurality of read wordlines, respectively; and a switching circuit configured to, in a program mode, detect program states of the plurality of OTP memory cells to block currents from flowing through the plurality of OTP memory cells from the voltage wordlines to the bitlines based on the detected program states.

Abstract: Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor.

Abstract: Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Abstract: A circuit includes: a first circuit stage configured to sample a differential input signal at a first logic state of a sampling clock and regenerate the sampled differential input signal at a second logic state of the sampling clock to output a first regenerated differential signal; a second circuit stage configured to amplify the first regenerated differential signal at the second logic state of the sampling clock to output an amplified differential signal; and a third circuit stage configured to regenerate the amplified differential signal at the first logic state of the sampling clock to output a second regenerated differential signal.

Abstract: Methods and apparatuses for performing receive and transmit path tuning of a toggle mode interface between a primary controller and a secondary controller is disclosed. A first component having a variable setting and connected with a data bus of the interface is iteratively adjusted. For each setting of the first component, test data written to the secondary controller and a delay unit having a variable delay setting and connected with a strobe line of the interface is adjusted. Delay settings are identified where the read data is equal to the written data. Settings for the first component and corresponding delay setting that produce the largest range of delay settings where the read data is equal to the written data is selected. The first component may correspond to a driver unit in the primary controller or an ODT unit in the secondary controller.

Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.

Abstract: Embodiments relate to pre-silicon device testing using a persistent command table. An aspect includes receiving a value for a persistent command parameter from a user. Another aspect includes determining whether the value of the persistent command parameter is greater than zero. Another aspect includes based on determining whether the value of the persistent command parameter is greater than zero, selecting a number of commands equal to the value of the persistent command parameter from a regular command table of a driver of a device under test. Another aspect includes adding the selected commands to the persistent command table of the driver. Another aspect includes performing testing of the device under test via the driver using only commands that are in the persistent command table of the driver.

Abstract: Systems and methods establish a magnetically insulated fusion process. An exemplary embodiment establishes a Field Reversed Configuration (FRC) plasma, wherein the FRC plasma is a closed field, magnetically confined plasma; collapses a metal shell about the FRC plasma; and establishes a fusion reaction in response to collapsing the metal shell about the FRC plasma.

Abstract: A reactor vessel that performs work inside a nozzle stub of the reactor vessel, including a platform unit that is provided at an upper portion inside the reactor vessel and includes a substantially cylindrical side wall portion and a bottom portion blocking the lower end of the side wall portion; an access window that is provided at the side wall portion of the platform unit an access window moving device that opens and closes the access window; a working device; and a control device that is provided at the outside of the reactor vessel and controls the access window moving device and the working device, wherein the control device drives the access window moving device to open the access window, drives the working device to perform work inside the nozzle stub, and then drives the access window moving device to close the access window after the performance of the work.

Abstract: A control room for a nuclear power plant including two or more nuclear reactor units includes a central workstation providing monitoring capability for both nuclear reactor units, a first operator at the controls (OATC) workstation in front of and to one side of the central workstation providing monitoring and control capabilities for the first nuclear reactor unit, a second OATC workstation in front of and to the other side of the central workstation providing monitoring and control capabilities for the second nuclear reactor unit, and a common control workstation directly in front of the central workstation providing monitoring and control capabilities for systems serving both the first nuclear reactor unit and the second nuclear reactor unit. The central and common control workstations do not provide control capabilities for either nuclear reactor unit. The common control workstation does not include any control capabilities that must be performed by a licensed operator.

Abstract: A protection device for providing protection against ionizing radiation passing through an orifice defined by a wall bushing structure. The device includes a structure for attenuating ionizing radiation passing through the orifice, which structure can cover, or close off, the orifice, and includes a fastener configured to ensure that the structure for attenuating ionizing radiation can be fastened releasably to the wall bushing structure. The structure for attenuating ionizing radiation includes a sleeve that is open at both ends, that is deformable under its own weight, and that is configured to be fastened to the wall bushing structure by the fastener at a first open end of the sleeve.

Abstract: Illustrative embodiments of hybrid transparent conducting materials and applications thereof are disclosed. In one illustrative embodiment, a hybrid transparent conducting material may include a polycrystalline film and a plurality of conductive nanostructures randomly dispersed in the polycrystalline film. In another illustrative embodiment, a photovoltaic cell may include a transparent electrode comprising polycrystalline graphene that is percolation doped with metallic nanowires, where the metallic nanowires do not form a percolation network for charge carriers across the transparent electrode.

Abstract: A polyamide composition contains the following components: (a) at least 40 parts by weight PA12; (b) 0.1-15 parts by weight of at least one salt with a non-metallic cation; (c) 0.1-25% by weight of at least one dispersant based on esters or amides; (d) a quantity of carbon nanotubes that produces in the molding compound a specific surface resistance according to IEC standard 60167 of maximum 10?1-1010?; (e) 0-5 parts by weight of at least one metal salt; and optionally (f) conventional auxiliary substances and additives, the sum of the parts by weight of components (a) to (f) amounting to 100. The polyamide composition can be used for manufacturing moldings with improved electrical conductivity and improved surface quality.

Abstract: The invention relates to an insulation material having paint and a material additive, characterized in that the material additive comprises silicic acid and PE wax. The invention further relates to an insulating tape comprising an insulation core having a layer of insulating material according to the invention on at least one of the two flat sides.

Abstract: A dielectric composite material is provided for switch control by optical stimulus. The material includes a plurality of photo-conductive particulates; and a transparent binder for containing the plurality of particulates to form a photo-conductive pigment based matrix. The pigment based matrix is disposed on to overlap first and second separate electrodes to produce an electrical junction. Capacitance of the pigment based matrix changes from a first value absent the optical stimulus to a second value in response to illumination at a specific electromagnetic frequency and intensity by the optical stimulus.

Abstract: This is directed to a cable structure for use with an electronic device. The cable structure can include one or more conductors around which a sheath is provided. To prevent the cable structure from tangling, the cable structure can include a core placed between the conductors and the sheath, where a stiffness of the core can be varied along different segments of the cable structure to facilitate or hinder bending of the cable structure in different areas. The size and distribution of the stiffer portions can be selected to prevent the cable from forming loops. The resistance of the core to bending can be varied using different approaches including, for example, by varying the materials used in the core, varying a cross-section of portions of the core, or combinations of these.

Abstract: A wire harness which can absorb a position shift or a dimensional tolerance related to mounting or the like sufficiently is provided. A wire harness (21) includes a harness body (22), a motor side connector (23) provided at one end of the harness body (22), and an inverter side connector (24) provided at the other end of the harness body (22). The harness body (22) includes high voltage conduction paths (25), and an electromagnetic shielding member (26) which collectively covers the high voltage conduction paths (25). The high voltage conduction path (25) includes a conductor body (27), connecting parts (28, 29) and a mold part (30). The conductor body (27) is provided with a tolerance absorbing part (31).

Abstract: An object of the present invention is to provide a heat-recoverable article that thermally shrinks in a suitable temperature range and that does not easily split, and a wire splice and a wire harness that use the heat-recoverable article. The heat-recoverable article according to the present invention is a cylindrical, heat-recoverable article including a base layer. The base layer contains two or more polyolefin-based resins and a flame retardant, the base layer has a single melting-point peak temperature, the melting-point peak temperature is 112° C. or more and 128° C. or less, and a heat of fusion of the base layer is 60 J/g or more and 85 J/g or less. A heat of fusion of a total resin component of the base layer is preferably 80 J/g or more and 135 J/g or less.

Abstract: Discloses herein is a patterned transparent conductive electrode, comprises a substrate and a substantial single conductive layer on top of the substrate. The single conductive layer comprises a first region comprising a network of silver nanowires and means for protecting the nanowire from surface oxidation; and a second region, comprising a plurality of metal nanowires and means for protecting nanowire from surface oxidation, and metal oxide nanowires.

Abstract: A metal-oxide sintered body for a temperature sensor that can be installed in a combustion engine and components connected to the engine in order to sense temperature uses metal oxide. The metal-oxide sintered body has particles with large resistance values and particles with small resistance values mixed therein. The particles with the small resistance values may serve as a main resistance component in the temperature range of 0° C. to 500° C., and the particles with the large resistance values may contribute to the total resistance in proportion to the mixing ratio in the temperature range of 500° C. to 900° C. Thus, the metal-oxide sintered body enables a single sensor to measure all resistances, and can be used in an exhaust device or the like of a motor vehicle that requires temperature measurement over a wide range of temperatures.

Abstract: A high voltage surge arrester including insulating polymer housing with a protruding shed. The shed has an upper shed surface that forms a blunt angle with the longitudinal axis of the surge arrester and a lower shed surface. The lower shed surface includes an inner portion that forms an essentially right angle with said axis and an outer portion that forms an acute angle with said axis. Further the invention relates to an apparatus for molding an electrically insulating polymer housing.

Abstract: A process of fabricating a monolithic working component for magnetic heat exchange is disclosed. The process includes mixing two or more portions comprising amounts of La, Fe, Si and at least one of T and R suitable to produce a La1-aRa(Fe1-x-yTySix)13Hz phase, wherein T is at least one element from the group consisting of Mn, Co, Ni and Cr and R is at least one element from the group consisting of Ce, Nd, Y and Pr. The amount of T, R, and Si is selected for each of the two or more portions to provide the two or more portions with differing Curie temperatures and, preferably, a density, d, within a range of ±5% of an average density, dav, of a total number of portions. The process includes heat treating a single monolithic green body formed from two or more precursor powder mixtures to produce a single monolithic working component.

Abstract: Disclosed herein is a metal magnetic powder, and the metal magnetic powder according to the exemplary embodiment of the present invention includes a soft magnetic core particle and a multilayer coating film covering the core particle and having a multilayer structure, the multilayer coating film including an oxide film formed by heat treating the core particle and an insulation film formed by coating a coating particle with respect to the core particle.

Abstract: An electromagnetic lifting armature actuator, in particular for valves, comprises an armature rod which can be shifted in the direction of its longitudinal axis, and a magnetic yoke comprising a first yoke leg and a second yoke leg which is coaxial to the armature rod. A first magnet coil encloses the first yoke leg and a second magnet coil encloses both the second yoke leg and the armature rod. One of the magnet coils is a working and measuring coil which can be selectively used for enhancing the magnetic force or for determining a position of the movable armature rod.

Abstract: A transformer device includes: a transformer that includes a magnetic body core and a winding; a case that houses the transformer; an external terminal that is provided in the case; a relay section that is provided in the case and to which an end portion of the winding of the transformer is connected; and a conducting wire of which one end is wound around the external terminal and bonded thereto, and another end is connected to the relay section.

Abstract: An apparatus includes a coil assembly, a core, and at least one cooling channel. The coil assembly includes at least one winding configured to receive a varying electrical current. The core includes multiple segments, and the at least one winding is wound around portions of the segments and is configured to generate a magnetic flux. The at least one cooling channel is configured to transport coolant through the coil assembly or core in order to cool the coil assembly or core. Portions of the segments of the core can be separated from one another to form multiple cooling channels through the core, and the multiple cooling channels can be configured to transport coolant through the core. The coil assembly may include at least one insulative spacer having multiple cooling channels, and the multiple cooling channels may be configured to transport coolant through the coil assembly.

Abstract: A reactor that is small and capable of adjusting a coupling coefficient is provided. A reactor includes a plurality of coils obtained by winding a winding wire and a core that magnetically couples the plurality of coils to each other. The plurality of coils is arranged parallel to each other such that the adjacent outer circumferential surfaces are opposed to each other. The core may include: (1) a plurality of magnetic leg portions around which the plurality of coils are respectively disposed and (2) a pair of coupling portions that are disposed at both end portions of the magnetic leg portions and that couple the end portions of the magnetic leg portions adjacent to each other. The reactor may further include a coupling coefficient adjustment means that adjusts a coupling coefficient between adjacent coils.

Abstract: A system and method of controlling inductive power transfer in an inductive power transfer system and a method for designing an inductive power transfer system with power accounting. The method of controlling inductive power transfer including measuring a characteristic of input power, a characteristic of power in the tank circuit, and receiving information from a secondary device. Estimating power consumption based on the measured characteristic of tank circuit power and received information and comparing the measured characteristic of input power, the information from the secondary device, and the estimated power consumption to determine there is an unacceptable power loss. The method for designing an inductive power transfer system with power accounting including changing the distance between a primary side and a secondary side and changing a load of the secondary side.

Abstract: A coil unit configured to transmit or receive electric power by electromagnetic induction in a noncontact manner, including: a coil into or from both terminals of which a high-frequency voltage is input or output; a metal conductor placed near the coil; and a first capacitor and a second capacitor connected to the terminals of the coil, wherein the ratio of the capacitance between the first capacitor and the second capacitor is set to a value at which a current induced into the metal conductor due to capacitance coupling when a high-frequency voltage is input into or output from the coil is reduced.

Abstract: An auto-resonant driver for a transmitter inductor drives the inductor at an optimal frequency for maximum efficiency. The transmitter inductor is magnetically coupled, but not physically coupled, to a receiver inductor, and the current generated by the receiver inductor is used to power a load. The system may be used, for example, to remotely charge a battery (as part of the load) or provide power to motors or circuits. A feedback circuit is used to generate the resonant driving frequency. A detector in the transmit side wirelessly detects whether there is sufficient current being generated in the receiver side to achieve regulation by a voltage regulator powering the load. This point is achieved when the transmitter inductor peak voltage suddenly increases as the driving pulse width is ramped up. At that point, the pulse width is held constant for optimal efficiency.

Abstract: A multilayer ceramic capacitor may include a ceramic body and an active layer. The ceramic body includes three external electrodes disposed on amounting surface thereof so as to be spaced apart from each other, and first, second, and third lead parts extending from first and second internal electrodes of the ceramic body so as to be exposed to the mounting surface of the ceramic body. One side of at least one of the first, second, and third lead parts connected to the mounting surface of the ceramic body may be at least partially formed as an inclined extension portion that is inclined with respect to an outer periphery of the first or second internal electrode.

Abstract: A multilayer ceramic capacitor may include a capacitance forming layer including dielectric layers and internal electrodes disposed on the dielectric layers; a lower cover layer disposed below the capacitance forming layer; an upper cover layer disposed above the capacitance forming layer; and a plurality of crack inducing air gaps disposed in the lower cover layer.