Abstract: Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.

Abstract: A mask may be used in a process for manufacturing a semiconductor device. The semiconductor device may include a source line, a first drain contact terminal, and a second drain contact terminal. The mask may include the following elements: a source-line corresponding light-transmitting portion, which corresponds to the source line; a first-drain-contact-terminal corresponding light-transmitting portion, which corresponds to the first drain contact terminal; a second-drain-contact-terminal corresponding light-transmitting portion, which corresponds to the second drain contact terminal; and a first light-blocking portion, which abuts at least one of the source-line corresponding light-transmitting portion, the first-drain-contact-terminal corresponding light-transmitting portion, and the second-drain-contact-terminal corresponding light-transmitting portion.

Abstract: Method of forming a termination angle in a titanium tungsten layer include providing a titanium tungsten layer and applying a photo resist material to the titanium tungsten layer. The photo resist material is exposed under a defocus condition to generate a resist mask, wherein an edge of the exposed photo resist material corresponds to the sloped termination. The titanium tungsten layer is etched with an etching material, wherein the etching material at least partially etches the photo resist material exposed under the defocused condition, and wherein the etching results in the sloped termination in the titanium tungsten layer.

Abstract: FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

Abstract: A workpiece (120) has protruding conductive features (140) at least on a first side. The second side is processed while the workpiece is held from the first side by a holder (220H). To prevent damage to the protruding features and flatten the workpiece (which could be otherwise warped), a spacer (210) is inserted between the workpiece and the holder. The spacer has holes (250) receiving the protruding features. The workpiece can be held by forces generated by the holder such as vacuum or an electrostatic force, without an adhesive. Other features and advantages are provided.

Abstract: A method of fabricating a semiconductor package includes mounting a plurality of semiconductor devices on a substrate; forming a molding member that covers a top surface of the substrate, top surfaces of the semiconductor devices, and sidewall surfaces of the semiconductor devices; sawing the molding member and the substrate along pre-scribing lines of the substrate; and spraying a metallic epoxy material on the sawn molding members using a sprayer to form an antistatic layer on sidewall surfaces and a top surface of each of the sawn molding members.

Abstract: Mold pieces (105 and 110) for molding a layer of mold compound on the interconnect side of a bumped semiconductor wafer (118) include a primary cavity (117) and secondary cavities (120) into which excess mold compound from the primary cavity (117) flows. The secondary cavities (120) include a plunger (130) that asserts a predetermined backpressure that is equal to a desired mold compound pressure on the mold compound during molding. As most of the excess mold compound in the primary cavity (117) is forced to flow into the secondary cavities (120), this advantageously leaves a relatively thin layer of mold compound on the semiconductor wafer (118), which can then be removed, for example by grinding, in a relatively short time. Mold piece (105) further comprises a movable cavity bar (115) that can be moved away from mold piece (105) after molding and be cooled to detach the molded substrate that adheres to the cavity bar.

Abstract: A brush core for engaging and rotating a generally cylindrical brush having a hollow bore is provided. The brush core includes, but is not limited to, a body section forming an outer surface for engaging the hollow bore of the cylindrical brush. The outer surface of the body section includes three or more sides.

Abstract: An etching apparatus includes a receiving container which receives a substrate, and a first spraying unit which supplies etchant into the receiving container. The receiving container includes a bottom plate, a plurality of bottom through holes defined in the bottom plate and through which the etchant is drained from the receiving container; and a plurality of side walls extended from the bottom plate.

Abstract: A stage heater and a method of manufacturing a shaft capable of suppressing heat transfer from a heating substrate toward the shaft. The stage heater includes: a heating substrate made of aluminum or an alloy containing aluminum; and a shaft that is bonded to one surface of the heating substrate and supports the heating substrate. The shaft includes: a pipe made of a metal having a lower heat conductivity than a material of the heating substrate; and a bonding layer formed on a side of the pipe to be bonded to the heating substrate by accelerating a powder material of aluminum or a powder material of an alloy containing aluminum together with a gas and blowing the powder material while being maintained in a solid phase to the pipe so as to deposit thereon.

Abstract: A via pass-through apparatus is disclosed. The via pass-through apparatus includes a pass-through chamber adapted to couple between a first mainframe section and a second mainframe section of a substrate processing system, the pass-through chamber including an entry and an exit each having a slit valve, and a via process chamber located at a different level than the pass-through chamber wherein the via process chamber is adapted to carry out a process on a substrate at the via location. Systems and methods of operating the system are provided, as are numerous other aspects.

Abstract: The invention relates to computer visual recognition output image-aided LED die sorting system and sorting method. The computer visual recognition output image-aided LED die sorting system comprises an optical inspection device, a scanning device, a tablet computer device and a die sucking device. The scanning device scans an inspection result of the optical inspection device and transfers the scan data to the tablet computer device, and then the tablet computer device displays a recognition signal for a user to determine rapidly. Meanwhile, the sorting method can be performed to decrease the manpower cost and enhance the quality yield and production speed.

Abstract: An apparatus for fixing a metal mask includes a first substrate, a magnet array structure, a second substrate, and a metal mask. The magnet array structure includes a plurality of magnets. The magnet array structure is disposed on the first substrate. The plurality of magnets includes their respective magnetic axes. The magnetic axes cross each other. The second substrate is disposed on the magnet array structure. The metal mask is disposed on the second substrate.

Abstract: In an embodiment, the present invention discloses cleaned storage processes and systems for high level cleanliness articles, such as extreme ultraviolet (EUV) reticle carriers. A decontamination chamber can be used to clean the stored workpieces. A purge gas system can be used to prevent contamination of the articles stored within the workpieces. A robot can be used to detect the condition of the storage compartment before delivering the workpiece. A monitor device can be used to monitor the conditions of the stocker.

Abstract: An inactive gas introducing facility includes an introducing device disposed in a support portion supporting a container accommodating a substrate and configured for introducing inactive gas to the inside of the container through a gas feed opening of the container with discharging gas present inside the container to the outside through a gas discharge opening of the container and a controller for controlling operation of the introducing device. The introducing device is capable of varying the feed rate of the inactive gas. The controller is configured to control the operation of the introducing device such that in the feeding of the inactive gas to the container supported to the support portion, the feed rate is increased progressively to a target feed rate.

Abstract: There is provided a substrate transfer antechamber mechanism for a compact manufacturing apparatus that produces various types of devices in small volume using a small-diameter processing substrate at low cost. A container placement table, on which a wafer transfer container housing a semiconductor wafer is placed, is provided on an upper surface of an apparatus antechamber for a compact semiconductor manufacturing apparatus, and the apparatus antechamber includes therein a wafer elevating mechanism and a horizontal transfer mechanism. The wafer elevating mechanism moves down while holding from below a delivery bottom of the wafer transfer container, on which the semiconductor wafer remains placed, to transfer the semiconductor wafer into the apparatus antechamber. The horizontal transfer mechanism transfers the semiconductor wafer into a processing chamber using a transfer arm that receives the semiconductor wafer from the delivery bottom and extends.

Abstract: There is described apparatus and methods for transporting and processing substrates including wafers as to efficiently produce at reasonable costs improved throughput as compared to systems in use today. A linear transport chamber includes linear tracks and robot arms riding on the linear tracks to linearly transfer substrates along the sides of processing chambers for feeding substrates into a controlled atmosphere through a load lock and then along a transport chamber as a way of reaching processing chambers.

Abstract: An end handler and method for processing a device are presented. The end handler includes a mating portion for mating with a tool and a support portion for supporting a film frame on a support surface. The support portion includes a support base section, extension sections extending from the support base section, and vacuum ports on the support surface for facilitating mating of the film frame on the support surface. Each of the vacuum port includes at least one reservoir having at least one vacuum opening in fluid communication with at least one vacuum source. The vacuum ports being configured to principally maintain a slimmest profile with strongest suction force possible.

Abstract: Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

Abstract: There are included: forming element isolation regions in a semiconductor substrate; introducing a first impurity of a first conductivity type, to thereby form a first well and a second well of the first conductivity type; introducing a second impurity of a second conductivity type, to thereby form a third well of the second conductivity type and introducing the second impurity into a region between the first well and the second well, to thereby form a separation well of the second conductivity type; and further introducing a third impurity of the second conductivity type into the region between the first well and the second well.

Abstract: Novel methods to fabricate biological sensors and electronics are disclosed. A silicon-on-insulator wafer can be employed by etching a pattern of holes in the silicon layer, then a pattern of cavities in the insulating layer, and then sealing the top of the cavities. Further, n or p doped regions and metallic regions can be defined in the processed wafer, thereby enabling integration of biological sensing and electronic capabilities in the same wafer.

Abstract: A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of alternating sacrificial layers and insulating layers located over a major surface of a substrate. A contact mask having contact mask openings is provided over the stack, and a first over mask having first over mask openings is provided over the contact mask. A subset of the contact mask openings is substantially aligned with the first over mask openings. Contact openings are formed through the stack, wherein each of the contact openings extends substantially perpendicular to the major surface of the substrate to a respective one of the sacrificial layers. A plurality of electrically conductive via contacts is formed in the plurality of the contact openings.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A dielectric layer is deposited over a substrate and a hard mask (HM) layer is deposited over the dielectric layer. A line-like opening is formed in the HM layer and a line-end opening are then formed in the HM layer to connect to the line-like opening at the end of the line-like opening. The dielectric layer is etched through the line-like opening and the line-end opening to form a dielectric trench and a conductive line is formed in the dielectric trench.

Abstract: An interconnection structure may include insulating layers stacked stepwise and dielectric layers interposed between the insulating layers. The interconnection structure may include conductive layers interposed between the insulating layers and surrounding sidewalls of the dielectric layers, respectively. The interconnection structure may include contact plugs each coupled to one of the conductive layers. The contact plugs may at least partially pass through the dielectric layers.

Abstract: Dummy bit lines of are formed in a sacrificial layer at locations where bit lines are to be formed, with bit lines separated by trenches that extend through the sacrificial layer. Enclosed air gap structures are formed in the trenches between the dummy bit lines. Subsequently, the dummy bit lines are replaced with metal to form bit lines.

Abstract: A nitridation step applied to a tungsten via in a first silicon oxide layer forms a tungsten nitride layer on an exposed top surface of the tungsten via. Subsequently, a second silicon oxide layer is formed over the first silicon oxide layer and the tungsten via. Subsequently, an opening is formed through the second silicon oxide layer to expose at least part of the silicon nitride layer. Subsequently, a wet clean step is performed.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. A first insulation layer is formed on a semiconductor die, a redistribution layer electrically connected to a bond pad is formed on the first insulation layer, and a second insulation layer covers the redistribution layer. The second insulation layer is made of a cheap, non-photosensitive material. Accordingly, the manufacturing cost of the semiconductor device can be reduced.

Abstract: An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top source/drain region over the first semiconductor channel, and a first top source/drain pad overlapping the first top source/drain region. The second vertical transistor includes a second semiconductor channel, a second top source/drain region over the second semiconductor channel, and a second top source/drain pad overlapping the second top source/drain region. A local interconnector interconnects the first top source/drain pad and the second top source/drain pad. The first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region, with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector.

Abstract: One illustrative method disclosed herein includes, among other things, forming a region of a sacrificial material in a semiconductor substrate at a location where the portion of the fin to be removed will be located, after forming the region of sacrificial material, performing at least one first etching process to form a plurality of fin-formation trenches that define the fin, wherein at least a portion of the fin is comprised of the sacrificial material, and performing at least one second etching process to selectively remove substantially all of the sacrificial material portion of the fin relative to the substrate.

Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.

Abstract: A semiconductor device and a method for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second and first semiconductor layers to form an initial fin; forming an isolation layer on the substrate, wherein the isolation layer exposes partially the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer, wherein the first semiconductor layer comprises a compound semiconductor, with at least one component whose concentration has a graded distribution in a stack direction of the first and second semiconductor layers.

Abstract: Methods for creating self-aligned FINFET SDBs for minimum gate junction pitch and epitaxy formation. Embodiments include forming separated openings in a hard mask on upper surfaces of Si fins; forming cavities in the fins, each of the cavities having a concave shape and a width extending under the hard mask on each side of the cavity; forming trenches in the fins, the trenches having an upper width substantially equal to a width of the openings and less than the width of a cavity; removing the hard mask; filling the trenches and the cavities with oxide, forming STI regions; forming an oxide mask layer on the upper surfaces of the fins and the STI regions; removing upper portions of the oxide in sections between the STI regions; and removing remaining portions of the oxide mask revealing the fins and upper surfaces of the STI regions.

Abstract: A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.

Abstract: A polishing method and a polishing apparatus for performing a measurement of a film thickness of a substrate, such as a wafer, if an error has occurred during polishing of the substrate. The polishing method includes polishing a plurality of substrates, measuring a film thickness of at least one substrate, which has been designated in advance, of the plurality of substrates that have been polished, and if a polishing error has occurred during polishing of any one of the plurality of substrates, measuring a film thickness of that substrate.

Abstract: A method of manufacturing an organic EL display apparatus including an organic EL panel having light emitting pixels each of which has an organic EL element (OEL) includes: lighting up lighting target pixels set from among the light emitting pixels; causing an imaging device to photograph the organic EL panel and receiving a photographed image from the imaging device; detecting the lighting target pixels using the photographed image; determining whether an undetectable pixel that cannot be detected is included among the lighting target pixels, using a result obtained in the detecting; increasing an amount of luminescence of the undetectable pixel to a detectable amount of luminescence, when it is determined that the undetectable pixel is included; and aligning a relative position of the organic EL display apparatus and the imaging device, using the result obtained in the detecting.

Abstract: A mask includes a substrate, an effective pixel formation region and a reference pattern formation region. A pixel pattern for forming a pixel component that constitutes a pixel is arranged in the effective pixel formation region. A reference pattern for indicating a reference position where pixel pattern should be arranged in the effective pixel formation region is arranged in the reference pattern formation region. Pixel pattern is arranged to be displaced from the reference position toward a center side of the effective pixel formation region.

Abstract: A structure for TDDB measurement, a method determining TDDB at reduced spacings. The structure includes an upper dielectric layer on a top surface of a lower dielectric layer, a bottom surface of the upper dielectric layer and the top surface of the lower dielectric layer defining an interface; a first wire formed in the lower dielectric layer; a second wire formed in the upper dielectric layer; and wherein a distance between the first wire and the second wire measured in a direction parallel to the interface is below the lithographic resolution limit of the fabrication technology.

Abstract: A semiconductor device that includes a semiconductor chip having a first silicon substrate with opposing first and second surfaces, a semiconductor device formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the semiconductor device, a layer of thermal conductive material on the second surface, and a plurality of first vias formed partially through the layer of thermal conductive material.

Abstract: Disclosed is a heat dissipating component for a semiconductor element, having a tabular body 0.4-6 mm in thickness containing 40-70 volume % of diamond particles, with the balance comprising metal of which the principal component is aluminum, and coated on both surfaces by a coating layer comprising metal of which the principal component is aluminum, or an aluminum-ceramic based composite material, to form an aluminum-diamond based composite body. On at least the two major surfaces thereof are formed, in order from the major surface side, (1) an amorphous Ni alloy layer 0.1-1 ?m in film thickness, (2) an Ni layer 1-5 ?m in film thickness, and (3) an Au layer 0.05-4 ?m in film thickness, the ratio of the Ni alloy layer and the Ni layer (Ni alloy layer thickness/Ni layer thickness) being 0.3 or less.

Abstract: A semiconductor module includes a semiconductor element having a gate electrode and source electrode on the front surface, and a drain electrode on the rear surface, the drain electrode being electrically connected to the front surface of a drain plate; a laminated substrate having, on the front surface of an insulating plate, a first circuit plate to which the gate electrode is electrically connected, and a second circuit plate to which the source electrode is electrically connected, and which is disposed on the front surface of the drain plate; a gate terminal disposed on the first circuit plate; a source terminal disposed on the second circuit plate; and a cover disposed opposite to the front surface of the drain plate, and having an opening in which the gate terminal and the source terminal are positioned and a guide groove contacting the opening and extending to the outer peripheral portion.

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device comprising a substrate including a first surface and a second surface that face each other, a planarization layer formed on the first surface of the substrate, a passivation layer formed on the planarization layer, and a through via contact penetrating the substrate, the planarization layer, and the passivation layer, and being exposed from the passivation layer.

Abstract: The integrated circuit includes first and second vias, a first buffer configured to receive a signal transmitted from the first via, a second buffer configured to receive a signal transmitted from the second via, a first detour circuit configured to receive a signal transmitted through the second buffer, a second detour circuit configured to receive a signal transmitted through the first buffer, a first selector configured to selectively output one of the signal transmitted from the first via and a signal transmitted through the first detour circuit, and a second selector configured to selectively output one of the signal transmitted from the second via and a signal transmitted through the second detour circuit. Each of the first and second buffers and the first and second detour circuits transmits a signal in only one direction.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a through silicon via hole, an interlayer dielectric, a liner layer and a conductor. The through silicon via hole is formed in the substrate. The interlayer dielectric is formed on the substrate. The interlayer dielectric defines an opening corresponding to the through silicon via hole. The interlayer dielectric comprises a bird beak portion near the through silicon via hole. The liner layer is formed on a bottom and a sidewall of the through silicon via hole. The conductor is filled in the through silicon via hole and the opening.

Abstract: An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer.

Abstract: There is provided a method for manufacturing a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.

Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

Abstract: Structures, architectures, systems, an integrated circuit, methods and software for configuring an integrated circuit for multiple packaging types and/or selecting a packaging type for an integrated circuit. A structure generally includes a bump pad having a plurality of electrically disconnected bump pad sections, a plurality of bond pads each configured for electrical connection to one of the bump pad sections, and a plurality of conductive traces, each adapted to electrically connect one of the bond pads to the one bump pad section. A method generally includes the steps of forming the bump pad, the bond pads, and the conductive traces from an uppermost metal layer, and forming an insulation layer thereover. Another method generally includes forming the uppermost metal layer, and forming either a wire bond to at least one of the bond pads, or a ball bond or solder ball to electrically connect the bump pad section.

Abstract: According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a multi-phase power inverter, a control circuit, and a driver circuit. The driver circuit is configured to drive the multi-phase power inverter responsive to a control signal from the control circuit. The multi-phase power inverter, the control circuit, and the driver circuit are each situated on a PQFN leadframe of the PQFN package. The control circuit and the driver circuit can be in a common integrated circuit (IC). Furthermore, the control circuit can be configured to reconstruct at least two phase currents of the multi-phase power inverter from a combined phase current.

Abstract: There is provided a semiconductor module package including: a base substrate formed by mounting one or more first semiconductor devices thereon; a lead frame formed on a top surface of the first semiconductor device and having an inlet formed to inject a solder paste; and spaces inserted between the first semiconductor device and the lead frame to form a separation space, wherein the solder paste is filled in the separation space.