Abstract: A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films connected at the bottom of the trench between the stacks, and have outside surfaces and inside surfaces. The outside surfaces contact the data storage structures on the sidewalls of the corresponding even and odd stacks forming a 3D array of memory cells; the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films having a U-shaped current path.

Abstract: The metallic material content of a contact via structure for a three-dimensional memory device can be reduced by employing a vertical stack of a doped semiconductor material portion and a metallic fill material portion. A backside contact via can be filled with an outer metallic layer, a lower conductive material portion, an inner metallic layer, and an upper conductive material portion to form a contact via structure such that one of the lower and upper conductive material portions is a doped semiconductor material portion and the other is a metallic fill material portion. The doped semiconductor material generates less stress than the metallic fill material per volume, and thus, the contact via structure can reduce stress applied to surrounding regions in the three-dimensional memory device.

Abstract: According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.

Abstract: A vertical memory device includes a substrate, gate lines, channels, contacts and contact spacers. The gate lines are stacked on top of each other on the substrate. The gate lines are spaced apart from each other in a vertical direction with respect to a top surface of the substrate. The gate lines include step portions that extend in a parallel direction with respect to the top surface of the substrate. The channels extend through the gate lines in the vertical direction. The contacts are on the step portions of the gate lines. The contact spacers are selectively formed along sidewalls of a portion of the contacts.

Abstract: The present disclosure may provide a semiconductor device with a low manufacturing degree of difficulty and an enhanced performance. The device may include conductive layers and insulating layers, alternately stacked, each of the insulating layers being thinner than each of the conductive layers; a channel layer passing through the conductive layers and the insulating layers; a data storage layer surrounding a side-wall of the channel layer; and first charge blocking patterns, each of the first charge blocking patterns interposed between the conductive layers and the insulating layers and between the data storage layer and the conductive layers.

Abstract: The invention relates to a Radio Frequency System and method. A Radio Frequency (RF) system comprising a RF switch comprising a plurality of transistor switching elements implemented on Silicon on Insulator (SOI) for switching at least one or more RF signals and said SOI comprises a bulk substrate region and a buried oxide region. At least one filter is adapted to isolate the RF signal from the substrate and/or other high frequency signals or control signals present in the RF system. There is also provided a coupling capacitor adapted to cooperate with the filter to improve linearity of the transistor switch elements.

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation.

Abstract: A method of forming a fin-shaped structure includes the following steps. A substrate having at least a fin structure thereon is provided. A liner is formed on sidewalls of the fin structure. An oxide layer is formed between the fin structure and the substrate. The fin structure is removed until a bottom layer of the fin structure is reserved, to form a recess between the liner. A buffer epitaxial layer and an epitaxial layer are sequentially formed in the recess. A top part of the liner is removed until sidewalls of the epitaxial layer are exposed. Moreover, a fin-shaped structure formed by said method is also provided.

Abstract: An array substrate, a manufacturing method thereof, a liquid crystal panel and a liquid crystal display.

Abstract: Embodiments of the present invention disclose an array substrate and a method of manufacturing the same, and a liquid crystal display screen.

Abstract: A display device including: a substrate including first and second sides which face and are parallel to each other, and third and fourth sides which are orthogonal to the first and second sides, and face each other; a gate driver and a data driver disposed along the first side of the substrate; a first diagonal gate line, which is extended in a first direction crossing directions in which the first to fourth sides are extended, and has both ends heading the second and fourth sides of the substrate; a gate pad part extended from one end of the first diagonal gate line adjacent to the second side; an insulation layer including an opening for exposing at least a partial area of the gate pad part and formed on the substrate; a redundancy line extended in a second direction parallel to a direction in which the third and fourth sides are extended, and connected to the gate driver; and a redundancy pad part extended from the redundancy line to be in direct contact with the gate pad part exposed through the opening.

Abstract: An array substrate and a manufacturing method thereof, and a display apparatus comprising the array substrate are provided. The array substrate comprises a base substrate, and a thin film transistor and a storing capacitor provided on the base substrate, the thin film transistor comprises a gate, a source, a drain and a gate insulation layer provided between the source and drain and the gate, the storing capacitor comprises a first plate, a second plate and a dielectric layer provided between the first plate and the second plate, wherein, both of the first plate and the second plate are formed of metal material, and the dielectric layer is formed of the same material as the gate insulation layer. In the array substrate of the present invention, the charging speed of the storing capacitor can be improved and the display quality of the display apparatus comprising the array substrate is further improved.

Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.

Abstract: A transistor a gate of which, one of a source and a drain of which, and the other are electrically connected to a selection signal line, an output signal line, and a reference signal line, respectively and a photodiode one of an anode and a cathode of which and the other are electrically connected to a reset signal line and a back gate of the transistor, respectively are included. The photodiode is forward biased to initialize the back-gate potential of the transistor, the back-gate potential is changed by current of the inversely-biased photodiode flowing in an inverse direction in accordance with the light intensity, and the transistor is turned on to change the potential of the output signal line, so that a signal in accordance with the intensity is obtained.

Abstract: An image sensor with an array of pixels is provided. In order to achieve high image quality, it may be desirable to improve well capacity of individual pixels within the array. When forming each pixel, multiple n-type compartments having p-type isolation regions interposed between compartments may be formed. These compartments may have higher dopant concentrations due to lateral depletion that may occur within multiple PN-NP back to back junctions to assist full depletion at pinning-voltage. Compartments may allow distributing a moderately higher electric-field over a larger portion of the photodiode while lowering peak electric-fields that contribute to dark-current. Compartments will thereby improve the well capacity of the photodiode while preventing additional noise that may degrade the quality of the image signal. The quantity, doping, and depth of these compartments may be selected to maximize well capacity while minimizing effects on operating voltage, manufacturing cost, and power consumption.

Abstract: An image sensor includes a substrate having adjacent pixel regions and respective photodiode regions therein, and a pixel separation portion including a trench extending into the substrate between the adjacent pixel regions. The trench includes a conductive common bias line therein and an insulating device isolation layer between the common bias line and surfaces of the trench. A conductive interconnection is coupled to the common bias line and is configured to provide a negative voltage thereto. Related fabrication methods are also discussed.

Abstract: An image sensor includes: a lens configured to focus light after passing through or reflected by an object to be read and passing through a first transparent plate; a sensor arranged along the X direction and configured to receive the light focused by the lens; a first casing fixing the first transparent plate and containing or retaining the lens and the sensor; and a bracket arranged at the X direction end portion of the first casing and configured to seal the lens contained or retained by the first casing.

Abstract: A semiconductor device includes a thermal conductor formed on and thermally connected to the seal ring. The thermal conductor is spatially spaced from the electrically conductive pad. The thermal conductor is exposed of the substrate and can be regarded as an extension of the thermal path of the seal ring, such that the heat from the seal ring is dissipated efficiently.

Abstract: An image sensor includes a plurality of pixels arranged in two dimensions, wherein at least one pixel includes: a photoelectric conversion layer formed in a substrate; a first color filter layer formed over the photoelectric conversion layer; and a second color filter layer formed over the first color filter layer and defining an opening that is eccentrically formed with respect to an optical axis of the photoelectric conversion layer.

Abstract: A solid-state imaging device includes a plurality of pixels each of which includes a photoelectric conversion unit that generates charges by photoelectrically converting light, and a transistor that reads a pixel signal of a level corresponding to the charges generated in the photoelectric conversion unit. A phase difference pixel which is at least a part of the plurality of pixels is configured in such a manner that the photoelectric conversion unit is divided into a plurality of photoelectric conversion units and an insulated light shielding film is embedded in a region for separating the plurality of photoelectric conversion units, which are divided, from each other.

Abstract: A solid-state imaging device includes: multiple micro lenses, which are disposed in each of a first direction and a second direction orthogonal to the first direction, focus the incident light into the light-receiving surface; with the multiple micro lenses of which the planar shape is a shape including a portion divided by a side extending in the first direction and a side extending in the second direction being disposed arrayed mutually adjacent to each of the first direction and the second direction; and with the multiple micro lenses being formed so that the depth of a groove between micro lenses arrayed in a third direction is deeper than the depth of a groove between micro lenses arrayed in the first direction, and also the curvature of the lens surface in the third direction is higher than the curvature of the lens surface in the first direction.

Abstract: A semiconductor device includes a first substrate, a second substrate, a plurality of through vias (TVs), and a plurality of conductive caps. The first substrate has at least one electrical component disposed thereon. The second substrate is stacked on the first substrate. The TVs extend through the second substrate to be electrically connected to the at least one electrical component of the first substrate. The conductive caps respectively cover the TVs, and the conductive caps are electrically isolated from each other.

Abstract: An image sensor device may include an interconnect layer, an image sensor IC carried by the interconnect layer and having an image sensing surface, and encapsulation material laterally surrounding the image sensor IC and covering an upper surface of the image sensor IC up to the image sensing surface. The image sensor device may include an optical plate having a peripheral lower surface carried by an upper surface of the encapsulation material and aligned with the image sensing surface, the optical plate being spaced above the image sensing surface to define an internal cavity, and a lens assembly coupled to the encapsulation material and aligned with the image sensing surface.

Abstract: The present disclosure provides a device having a doped active region disposed in a substrate. The doped active region having an elongate shape and extends in a first direction. The device also includes a plurality of first metal gates disposed over the active region such that the first metal gates each extend in a second direction different from the first direction. The plurality of first metal gates includes an outer-most first metal gate having a greater dimension measured in the second direction than the rest of the first metal gates. The device further includes a plurality of second metal gates disposed over the substrate but not over the doped active region. The second metal gates contain different materials than the first metal gates. The second metal gates each extend in the second direction and form a plurality of respective N/P boundaries with the first metal gates.

Abstract: A solid-state imaging device has a sensor substrate having a pixel region on which photoelectric converters are arrayed; a driving circuit provided on a front face side that is opposite from a light receiving face as to the photoelectric converters on the sensor substrate; an insulation layer, provided on the light receiving face, and having a stepped construction wherein the film thickness of the pixel region is thinner than the film thickness in a periphery region provided on the outside of the pixel region; a wiring provided to the periphery region on the light receiving face side; and on-chip lenses provided to positions corresponding to the photoelectric converters on the insulation layer.

Abstract: A CIS structure is provided, including a translucent structure, a reflective structure surrounding the translucent structure, and a micro lens disposed on a side of the translucent structure. The reflective structure includes a first reflective layer surrounding the translucent structure, a second reflective layer surrounding the first reflective layer, and a third reflective layer surrounding the second reflective layer. The first, second, and third reflective layers respectively have refractive indexes N1, N2, and N3, wherein N1>N2>N3.

Abstract: A stacked type image sensor with improved optical characteristics, which may result from a color separation element, and an image pickup apparatus including this image sensor. The stacked type image sensor includes first and second light sensing layers arranged in a stacked manner, and color separation elements positioned between the first and second light sensing layers. Accordingly, the first light sensing layer absorbs and detects light of a first wavelength band, and the second light sensing layer detects light of second and third wavelength bands separated by the color separation elements.

Abstract: A phase change memory device with reduced programming disturbance and its operation are described. The phase change memory includes an array with word lines and bit lines and voltage controlling elements coupled to bit lines adjacent to an addressed bit line to maintain the voltage of the adjacent bit lines within an allowed range.

Abstract: Resistive random-access memory (RRAM) devices and methods of manufacturing thereof are disclosed. A device comprises a first transparent conducting oxide (TCO) layer and a second TCO layer over the first TCO layer. The device further comprises a first dielectric layer between the first TCO layer and the second TCO layer, a second dielectric layer between the second TCO layer and the first dielectric layer, and a metal layer between the first dielectric layer and the second dielectric layer.

Abstract: The objection of invention is to provide an organic electroluminescent element having an excellent current-voltage property. The organic electroluminescent element of the invention comprises an anode, a light emitting layer and a cathode, in this order, wherein a total number of kinds of an electron transport material and a light emitting material contained in the light emitting layer is five or more. Preferably, a total number of kinds of an electron transport material contained in the light emitting layer is four or more, and at least one of an ionization potential and an electron affinity of three kinds or more of the electron transport materials contained in the light emitting layer is different from each other.

Abstract: An organic light-emitting diode display unit, a driving method thereof and a display device are disclosed. At least part of pixel units are pixel units each with a stacked structure; each pixel unit with the stacked structure includes two adjacent subpixel unit stacked groups; and each subpixel unit stacked group includes at least two subpixel units which have different emitting colors and are stacked and insulated from each other. During display of different image frames, each subpixel unit stacked group in each pixel unit with the stacked structure can display gray-scale effect of at least two colors based on applied signals. Compared with an approach that each subpixel unit can only display gray-scale effect of only one color for different image frames, the display effect can be improved.

Abstract: A flexible input and output device in which defects due to a crack is reduced. The input and output device includes a first flexible substrate, a second flexible substrate, a first buffer layer, a first crack inhibiting layer, an input device, and a light-emitting element. A first surface of the first flexible substrate faces a second surface of the second flexible substrate. The first buffer layer, the first crack inhibiting layer, and the input device are provided on the first surface side of the first flexible substrate. The first buffer layer includes a region overlapping with the first crack inhibiting layer. The first buffer layer is between the first crack inhibiting layer and the first surface. The input device includes a transistor and a sensor element. The light-emitting element is provided on the second surface side of the second flexible substrate.

Abstract: A curved display device including a display area and a non-display area is provided. The curved display device includes a first direction area configured to maintain a flat state and a bending area connected to the first direction area. A thin film transistor (TFT) layer, a passivation layer, a sealing layer, and an upper film are provided on a base substrate in an area where the display area overlaps the bending area, and the sealing layer and the upper film extend to an area where the non-display area overlaps the bending area.

Abstract: The present disclosure provides an OLED display device and its manufacturing method. The OLED display device includes an anode layer, a cathode layer, and a pixel-defined layer and a light-emitting layer both arranged between the anode layer and the cathode layer. The pixel-defined layer is provided with an opening, and the light-emitting layer is arranged in the opening. An insulating layer having a refractive index greater than that of the pixel-defined layer is arranged between the light-emitting layer and the pixel-defined layer.

Abstract: An organic light emitting display device includes a first substrate having a plurality of organic light emitting structures thereon, a second substrate facing the first substrate to encapsulate the organic light emitting structures, an aperture under a lower surface of the first substrate, and an aperture controller under the lower surface of the first substrate. The organic light emitting structures define a pixel area. The second substrate has a light absorption area. The aperture corresponds to the light absorption area. The aperture controller is adjacent to the aperture.

Abstract: Disclosed are an organic light emitting diode device, and a method for fabricating the same. The organic light emitting diode device comprises a non-active area formed outside an active area of a substrate; a switching thin film transistor and a driving thin film transistor at each of the pixel regions; a planarization layer on the substrate; a first electrode on the planarization layer; a bank formed in the non-active area outside each pixel region; an organic light emitting layer on the first electrode; a second electrode on an entire surface of the substrate; a first passivation layer on the substrate; an organic layer on the first passivation layer; a second passivation layer on the organic layer and the first passivation layer; a barrier film disposed to face the substrate.

Abstract: An organic light emitting display device includes a substrate including a plurality of pixel regions and a plurality of transparent regions, thin film transistors disposed in the pixel regions, an insulation layer disposed on the thin film transistors, first electrodes electrically contacting the thin film transistors, a pixel defining layer including a black material disposed on the first electrodes, organic light emitting structures disposed on the pixel defining layer, and a second electrode disposed on the organic light emitting structures. The pixel defining layer may define an asymmetrical configuration of adjacent transparent regions disposed on opposing sides of corresponding pixel regions.

Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.

Abstract: An OLED display panel is provided which can control the problem of shedding even in high definition panels. Metal wiring 5 which conducts with an earth line of a flexible printed substrate 15 is provided on a substrate 1. A display area 2 comprised from a plurality of OLED elements is provided at the center of the substrate 1 and four low resistance metal films 3 are provided along each of four edges of the display area 2 on a surface of insulation films 8, 10 at the periphery of the display area 2. Among these, one low resistance metal film 3 conducts with the metal wiring 5 via a contact 3a.

Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.

Abstract: A semiconductor device including a substrate having an isolation structure therein is disclosed. A capacitor is disposed on the isolation structure and includes a polysilicon electrode, an insulating layer disposed on the polysilicon electrode, and a metal electrode disposed on the insulating layer. A method for forming the semiconductor device is also disclosed.

Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

Abstract: Various embodiments provide an MIM capacitor and fabrication method thereof. An exemplary MIM capacitor can include a dielectric layer disposed over a substrate containing a conductive layer. The dielectric layer can include a groove to expose the conductive layer in the substrate. A first metal layer can be disposed on a bottom surface and a bottom portion of a sidewall surface of the groove. A top surface of the first metal layer on the sidewall surface of the groove can be lower than a top surface of the dielectric layer. A dielectric material layer can be disposed on the first metal layer and on a top portion of the sidewall surface of the groove. A second metal layer can be disposed on the dielectric material layer; and a third metal layer can be disposed on the second metal layer to fill the groove.

Abstract: One embodiment of the present invention is a semiconductor device which includes a gate electrode; a gate insulating film formed to cover the gate electrode; a semiconductor layer formed over the gate insulating film and placed above the gate electrode; a second insulating film formed over the semiconductor layer; a first insulating film formed over a top surface and a side surface of the second insulating film, a side surface of the semiconductor layer, and the gate insulating film; silicon layers and which are formed over the first insulating film and electrically connected to the semiconductor layer; and a source electrode and a drain electrode which are formed over the silicon layers. The source electrode and the drain electrode are electrically separated from each other over the first insulating film. The semiconductor layer is not in contact with each of the source electrode and the drain electrode.

Abstract: An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.

Abstract: A semiconductor device including a substrate including an active region and a device isolation region that isolates the active region, and a buried bit line and a buried gate electrode formed in the substrate. The device isolation region includes a first device isolation region extending in a first direction and a second device isolation region extending in a second direction crossing with the first direction and having an formed air gap.

Abstract: A method of manufacturing a semiconductor device may include: etching a recess in a semiconductor substrate, where the etching produces a metal residue over a surface of the recess. The recess may thereafter be exposed to a cleaning process that causes the metal residue to etch at least one fissure in the semiconductor substrate. The at least one fissure may extend from the surface of the recess into the semiconductor substrate. The method may further include epitaxially forming a liner comprising a first semiconductor material having a first dopant concentration within the recess and over the at least one fissure. The method proceeds with epitaxially forming a semiconductor layer comprising a second semiconductor material having a second dopant concentration over the liner.

Abstract: A lateral bipolar junction transistor is fabricated using a semiconductor-on-insulator substrate. The transistor includes a germanium gradient within a doped silicon base region, there being an increasing germanium content in the direction of the collector region of the transistor. The use of a substrate including parallel silicon fins to fabricate lateral bipolar junction transistors facilitates the inclusion of both CMOS FinFET devices and lateral bipolar junction transistors having graded silicon germanium base regions on the same chip.

Abstract: A dual-well metal oxide semiconductor (MOS) device includes: a substrate, an epitaxial layer, a first conductive type well, a first conductive type body region, a second conductive type well, a gate, a first conductive type lightly doped diffusion (LDD) region, a second conductive type lightly doped diffusion (LDD) region, a second conductive type source, and a second conductive type drain. The second conductive type well is connected to the first conductive type well in a lateral direction, and an PN junction is formed between the second conductive type well and the first conductive type well. The MOS device includes LDD regions of opposite conductive types, each located in a corresponding well of a corresponding conductive type, to reduce the channel length.

Abstract: An insulated gate bipolar transistor device includes a semiconductor substrate having a drift region of an insulated gate bipolar transistor structure. Further, the insulated gate bipolar transistor device includes a first nanowire structure and a first gate structure. The first nanowire structure of the insulated gate bipolar transistor structure is connected to the drift region, and the first gate structure of the insulated gate bipolar transistor structure extends along at least a part of the first nanowire structure.