Abstract: Embodiments of method and apparatus for acoustic echo control are described. According to the method, an echo energy-based doubletalk detection is performed to determine whether there is a doubletalk in a microphone signal with reference to a loudspeaker signal. A spectral similarity between spectra of the microphone signal and the loudspeaker signal is calculated. It is determined that there is no doubletalk in the microphone signal if the spectral similarity is higher than a threshold level. Adaption of an adaptive filter for applying acoustic echo cancellation or acoustic echo suppression on the microphone signal is enabled if it is determined that there is no doubletalk in the microphone signal through the echo energy-based doubletalk detection, or there is no doubletalk through the spectral similarity-based doubletalk detection.

Abstract: A noise estimation apparatus of estimating a noise in an input signal includes a sub-band noise estimator estimating a noise in a sub-band input signal, obtained by dividing the input signal by sub-bands. The sub-band noise estimator includes a power calculator calculating a sub-band input power of the sub-band input signal; a probability model holder holding information on probability model; and an a posteriori probability maximizer calculating an instantaneous estimated value of a sub-band noise power based on the sub-band input power, an estimated value of the sub-band noise power and the information on the probability model, so as to maximize a posteriori probability of the sub-band noise power. The information on the probability model includes a likelihood function regarding a posteriori signal-to-noise ratio (SNR) in dependence upon predictive a posteriori SNR; and a priori probability of the a posteriori SNR under a condition establishing averaged a posteriori SNR.

Abstract: In one embodiment, a computing device can detect an utterance of a target phrase within an acoustic input signal. The computing device can further determine a first estimate of cumulative signal and noise energy for the detected utterance in the acoustic input signal with respect to a first time period spanning the duration of the detected utterance, and a second estimate of noise energy in the acoustic input signal with respect to a second time period preceding (or following) the first time period. The computing device can then calculate a signal-to-noise ratio (SNR) for the detected utterance based on the first and second estimates and can reject the detected utterance if the SNR is below an SNR threshold.

Abstract: A voice-based system may comprise a local speech interface device and a remote control service. A user may interact with the system using speech to obtain services and perform functions. The system may allow a user to install applications to provide enhanced or customized functionality. Such applications may be installed on either the speech interface device or the control service. The control service receives user speech and determines user intent based on the speech. If an application installed on the control service can respond to the intent, that application is called. Otherwise, the intent is provided to the speech interface device which responds by invoking one of its applications to respond to the intent.

Abstract: An estimate of a pitch of a signal may be computed by using correlations of frequency portions of a frequency representation of the signal. An initial pitch estimate may be obtained and frequency portions of the frequency representation may be identified using multiples of the initial pitch estimate. Correlations of the frequency portions may be computed, and a score for the initial pitch estimate may be determined using the correlations. A second pitch estimate may be determined using the first score, and the process may be repeated.

Abstract: A change in an optical energy profile of energy emitted from a read/write head is determined. The read/write head includes an optical transmission path that emits the energy to heat a heat-assisted recording medium during writing. A change in optical efficiency of the read/write head is also determined. Based on the change in the optical energy profile and the change in the optical efficiency, a change in the effectiveness of the read/write head is determined, and in response a mitigation is performed.

Abstract: The present invention generally relates to a method for forming a smooth gap of a damascene write pole. An opening having a side wall with a first angle with respect to vertical is formed in a fill layer, and a first non-magnetic layer is deposited into the opening by ion beam deposition. The ion beam is delivered to the side wall at a second angle with respect to vertical. The ratio of the first angle to the second angle ranges from about 250 to about 3.5.

Abstract: A method, apparatus, and system for implementing head degradation detection and prediction for hard disk drives (HDDs) are provided. Statistical parameter stability tests are used that are calculated as Confidence Intervals (CIs) from HDD parameter measurements. HDD parameters include, for example, change or delta in fly height (dFH), magnetic resistor resistance (MRR) head values, servo variable gain amplifier (SVGA) readback amplitude values, that are used in conjunction with two or more confidence level indicators and an Auto-Regressive Integrated Moving-Average (ARIMA) (p, d, q) predictor for head degradation detection and field failure prediction.

Abstract: A storage apparatus of an embodiment includes a magnetic disk, a head, and a controller. The head includes a writing unit that outputs a magnetic field to record write data into a recording region of the magnetic disk to which light is irradiated and a reading unit that reads read data from the recording region of the magnetic disk. Based on a first spectrum of first read data read by the reading unit at a first position of the magnetic disk and a second spectrum of second read data read by the reading unit at a second position which is a following position of the first position, the controller detects whether an offset of the writing unit occurs while writing into the recording region of the magnetic disk is performed by the writing unit.

Abstract: An apparatus comprises a heat-assisted magnetic recording (HAMR) head, a sensor, and a controller. The HAMR head is configured to interact with a magnetic storage medium. The sensor is configured to produce a signal indicating the occurrence of head-medium contact. The controller is configured to receive the signal and concurrently determine from the signal if the occurrence of head-medium contact is caused by a first contact detection parameter, a second contact detection parameter, or both the first and second contact detection parameters.

Abstract: Systems and methods for providing high performance soft magnetic underlayers for magnetic recording media are described. One such magnetic recording medium includes a substrate, an amorphous soft magnetic underlayer including CoFeMoNb on the substrate, where an atomic percent of the Mo is greater than about 8 and an atomic percent of the Nb is greater than about 9, and a magnetic recording layer on the soft magnetic underlayer.

Abstract: A perpendicular magnetic recording medium adapted for high recording density and high data recording rate comprises a non-magnetic substrate having at least one surface with a layer stack formed thereon, the layer stack including a perpendicular recording layer containing a plurality of columnar-shaped magnetic grains extending perpendicularly to the substrate surface for a length, with a first end distal the surface and a second end proximal the surface, wherein each of the magnetic grains has: (1) a gradient of perpendicular magnetic coercivity Hk extending along its length between the first end and second ends; and (2) predetermined local exchange coupling strengths along the length.

Abstract: According to one embodiment, a perpendicular magnetic recording medium has an arrangement obtained by sequentially stacking a nonmagnetic substrate, a soft magnetic underlayer, a nonmagnetic seed layer containing silver grains having an fcc structure and an amorphous germanium grain boundary formed between the silver grains, a reaction barrier layer containing 90 at % or more of silver or aluminum and having a thickness of 2 nm or less, a nonmagnetic interlayer formed on the reaction barrier layer and made of ruthenium or a ruthenium alloy, and a perpendicular magnetic recording layer.

Abstract: A magnetic device including a magnetic writer; and an overcoat positioned over at least the magnetic writer, the overcoat including oxides of yttrium, oxides of scandium, oxides of lanthanoids, oxides of actionoids, oxides of zinc, or combinations thereof.

Abstract: In one general embodiment, a computer-implemented method includes using, by the computer, a tape head and/or an actuator to detect the presence of external vibration. The method also includes selecting, by the computer, at least one frequency of interest, and using, by the computer, a discrete Fourier transform implemented as a Goertzel filter to determine a magnitude of the external vibration at the at least one frequency of interest. Compensation may optionally be applied to reduce an effect of the external vibration.

Abstract: The present invention relates to a method for controlling a bit rate and an apparatus therefor, and more specifically to an apparatus for storing a bit rate changed according to a significant level in a memory and a method for determining the bit rate, which meets the requirements for the distortion according to the memory space limitation and the significant level of the image information so as to minimize the energy consumption.

Abstract: According to one embodiment, a magnetic recording and reproducing device includes a magnetic recording medium, a recording unit and a reproducing unit. The magnetic recording medium includes a first track and a second track, the first track extending in a first direction, the second track extending in the first direction and being arranged with the first track in a second direction intersecting the first direction. The first track includes first and second sub-tracks extending in the first direction. The second track includes third and fourth sub-tracks extending in the first direction. The second sub-track is disposed between the first and fourth sub-tracks. The third sub-track is disposed between the second and fourth sub-tracks. The recording unit records information in the first and second tracks. The reproducing unit reproduces first information recorded in the first track. The reproducing unit reproduces second information recorded in the second track.

Abstract: Methods, systems, and computer program product embodiments for improving track-follow control in a tape storage system, by a processor device, are provided. In one embodiment, a method comprises, time-varying filtering an error feedback signal within a closed-loop tape controller to dampen varying motor and harmonic disturbances.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for data processing to identify a defect on a medium.

Abstract: Method and system for capturing and playing back ancillary data associated with a video stream. At capture, a first video stream and its associated non-audio ancillary data are received. The non-audio ancillary data associated with the first video stream is encoded into a first audio stream on a basis of a predefined encoding scheme. The captured non-audio ancillary data can then be transmitted and processed with the first video stream in the form of the first audio stream. At playback, a second video stream and a second audio stream containing encoded non-audio ancillary data associated with the second video stream are received. The second audio stream is decoded on a basis of a predefined decoding scheme in order to extract therefrom the non-audio ancillary data associated with the second video stream. The second video stream and its associated non-audio ancillary data are then both output for playback.

Abstract: A read head is tested by measuring the thermal magnetic fluctuation noise spectrum. A non-uniformity in the magnetic field of the free layer is produced and the thermal magnetic fluctuation noise spectrum is measured, with and/or without an external magnetic field applied. A peak in the thermal magnetic fluctuation noise spectrum can be used to derive the desired dimension of the free layer, such as track width and stripe height. The resulting measurement may then be fed back into the process control for the production of the read heads if desired. Additionally, the stiffness of the free layer and the strength of the reference layer may be determined using ferromagnetic resonance peaks in the thermal magnetic fluctuation noise spectrum.

Abstract: A terminal apparatus includes: by way of a gateway apparatus configured to perform communication with an in-vehicle apparatus capable of playing back a content through a CAN bus, a first communication section configured to transmit command information for changing a mode of the in-vehicle apparatus to the in-vehicle apparatus; and a second communication section configured to transmit content data to the in-vehicle apparatus.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array disposed on the semiconductor substrate, a capacitor and a control circuit. The memory cell array includes a plurality of memory cells. The control circuit supplies a voltage to the memory cell array. The memory cell array includes a first conductive body disposed in a first region on the semiconductor substrate. The first conductive body extends in a first direction intersecting with a surface of the substrate. The capacitor includes first and second electrodes disposed in a second region different from the first region on the semiconductor substrate. The electrodes each include a second conductive body extending in the first direction. The first conductive body and the second conductive body include an identical material.

Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Abstract: Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit requesting a read operation, the controller provides the clock signal to the memory array to read data, and controls the sense amplifier and the output latch to provide the functionality of a flip-flop master and slave so that the read operation delay through the output latch to the external circuit is removed from a first read cycle of two sequential read cycles.

Abstract: Characteristics of each transistor in a semiconductor device including a transistor of a memory cell are measured by an ASV monitoring circuit, a power supply voltage supplied to the semiconductor device is determined based on the measured characteristics of the transistor, a data read-out speed of the memory cell under the determined power supply voltage supplied is measured while changing a signal level of a word line by an SRAM word line monitoring circuit, the signal level of the word line is determined by comparing the measured data read-out speed of the memory cell and a specification range of the memory cell, and the signal level of the word line is appropriately set at the power supply voltage applied by the ASV.

Abstract: A memory module having an address mirroring function is provided. The memory module includes a register that allows mode registers of first memory chips of a first rank and mode registers of second memory chips of a second rank to be identically programmed in response to a mode register set (MRS) command during a rank-merged test mode. The register sets address signals, which are symmetrically connected to the first and second memory chips through through-via-holes (TVHs) or blind-via-holes (BVHs) of a printed circuit board, to be selectively mirrored.

Abstract: A spin transport channel includes a dielectric layer contacting a conductive layer. The dielectric layer includes at least one of a tantalum oxide, hafnium oxide, titanium oxide, and nickel oxide. An intermediate spin layer contacts the dielectric layer. The intermediate spin layer includes at least one of copper and silver. The conductive layer is more electrochemically inert than the intermediate spin layer. A polarizer layer contacts the intermediate spin layer. The polarizer layer includes one of a nickel-iron based material, iron, and cobalt based material. The conductive layer and intermediate layer are disposed on opposite sides of the dielectric layer. The dielectric layer and the polarizer layer are disposed on opposite sides of the intermediate spin layer. The intermediate spin layer is arranged to form a conducting path through the dielectric layer configured to transport a plurality of electrons. Each of the plurality of electrons maintains a polarized electron spin.

Abstract: A magnetic memory element includes a first magnetic unit, a second magnetic unit, a third magnetic unit, a read/write unit, a first electrode, a second electrode, a third electrode, a first current source, the second current source. The third magnetic unit is connected to one end in the first direction of the first magnetic unit and one end in the first direction of the second magnetic unit. The read/write unit includes a nonmagnetic layer and a pinned layer. The nonmagnetic layer is connected to the third magnetic unit. The pinned layer is connected to the nonmagnetic layer. The first current source causes a current to flow between the third electrode and at least one of the first electrode or the second electrode. The second current source causes a current to flow between the first electrode and the second electrode.

Abstract: A MRAM cell including a first tunnel barrier layer between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization. A second tunnel barrier layer is between the soft ferromagnetic layer and a second hard ferromagnetic layer and has a second storage magnetization. The first storage magnetization is freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold. The first high predetermined temperature threshold is higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.

Abstract: Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory cell even when one of the magnetic tunnel junctions within the memory cell is defective and is no longer functional. Self-referenced and referenced reads can be used in conjunction with the multiple magnetic tunnel junction memory cells. In some embodiments, writing to the memory cell forces all magnetic tunnel junctions into a known state, whereas in other embodiments, a subset of the magnetic tunnel junctions are forced to a known state.

Abstract: Reverse complement MTJ bit cells employing shared source lines are disclosed. In one aspect, a 2T2MTJ reverse complement bit cell employing shared source line is provided. Bit cell includes first MTJ and second MTJ. Value of first MTJ is complement of value of second MTJ. First bit line is coupled to top layer of first MTJ, and first electrode of first access transistor is coupled to bottom layer of first MTJ. Second bit line is coupled to bottom layer of second MTJ, and first electrode of second access transistor is coupled to top layer of second MTJ. Word line is coupled to second electrode of first access transistor and second access transistor. Shared source line is coupled to third electrode of first access transistor and second access transistor. Employing shared source line allows the bit cell to be designed with reduced parasitic resistance.

Abstract: According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements, and a read circuit to read the complementary data from the first and second magnetoresistive elements. The control circuit is configured to change the first and second bit lines to a floating state after setting the first and second bit lines to a first potential, and change a potential of the first bit line in the floating state to a first value in accordance with a resistance value of the first magnetoresistive element and a potential of the second bit line in the floating state to a second value in accordance with a resistance value of the second magnetoresistive element by setting the common source line to a second potential higher than the first potential.

Abstract: In some examples, a memory device is configured with non-volatile memory array(s) having one or more associated volatile memory arrays. The memory device may include a non-destructive write mode configured to prevent access to the non-volatile memory array(s) during an initiation or calibration sequence performed by the memory device or an electronic device associated with the memory device to calibrate read and write access timing associated with the memory device.

Abstract: A memory device includes a counter suitable for counting the number of times that a periodic wave is enabled and generating a code, one or more memory banks each including a plurality of word lines, and one or more measurement blocks corresponding to the memory banks, respectively, and suitable for measuring an active period of an activated word line in a corresponding memory bank among the memory banks, wherein each of the measurement blocks measures the active period of the activated word line based on a first value of the code at an activation starting point of the corresponding memory bank and a current value of the code.

Abstract: A semiconductor memory apparatus may include a refresh mode control circuit configured to enable a row address increase signal when all banks capable of being designated by a bank address in a refresh operation are all designated. The semiconductor memory apparatus may also include and a row address generation circuit configured to increase a value of a row address when the row address increase signal is enabled.

Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

Abstract: The various embodiments described herein include memory dies and methods for memory die communications. In one aspect, a method is performed at a first memory die with a plurality of memory banks and a plurality of contacts. The method includes: (1) coupling a first memory bank of the plurality of memory banks to a second memory die via the plurality of contacts; (2) transmitting data between the first memory bank and the second memory die via the plurality of contacts; and (3) receiving a control signal to couple a second memory bank of the plurality of memory banks to the second memory die. The method further includes, in response to receiving the control signal, coupling the second memory bank to the second memory die via the plurality of contacts; and transmitting data between the second memory bank and the second memory die via the plurality of contacts.

Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

Abstract: Approaches for providing write-assist boost for a Static Random Access Memory (SRAM) array are provided. A circuit includes a write driver of a Static Random Access Memory (SRAM) array. The circuit also includes a boost circuit that dynamically varies a write-assist boost voltage based on a stability assist setting applied to a wordline of the array.

Abstract: Apparatus and method for performing a post-write read in a memory device are disclosed. A memory device may include 3-dimensional memory, with the wordlines in a memory block each having multiple strings. Periodically, the memory device may analyze the wordlines for defects by performing a post-write read on a respective wordline and analyzing the read data to determine whether the respective wordline is defective. Rather than reading all of the strings for the respective wordline, less than all of the strings (such as only one of the strings) for the respective wordline are read. In this way, determining whether the respective wordline in 3-dimensional memory may be performed more quickly.

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Abstract: A semiconductor memory device includes a memory cell configured to hold 4-bit data according to a threshold. A first bit of the 4-bit data is established by reading operations using a first to a third read levels. A second bit different from the first bit is established by reading operations using a fourth to a seventh read levels. A third bit different from the first and second bits is established by reading operations using an eighth to an eleventh read levels. A fourth bit different from the first to third bits is established by reading operations using a twelfth to a fifteenth read levels.

Abstract: A Virtual-Memory Device (VMD) driver and application execute on a host to increase endurance of flash memory attached to a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD). Host accesses to flash are intercepted by the VMD driver using upper and lower-level filter drivers and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type before storage by the SSD. Ramdisks and caches for storing each data type in the host DRAM are managed and flushed to the SSD by the VMD driver. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.

Abstract: Junction diodes or MOS devices fabricated in standard FinFET technologies can be used as program selectors or One-Time Programmable (OTP) element in a programmable resistive device, such as interconnect fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCRAM, CBRAM, or RRAM. The MOS or diode can be built on at least one fin structure or at least one active region that has at least one first active region and a second active region. The first and the second active regions can be isolated by a dummy MOS gate or silicide block layer (SBL)to construct a diode.

Abstract: A memory device for thermoelectric heat confinement and method for producing same. The memory device includes a plurality of phase-change memory cells, wherein each of the phase-change memory cells has a first electrode, a second electrode and a phase-change material. The first electrode and the phase-change material are arranged such that a surface normal of a dominating interface for a current flow between the first electrode and the phase-change material points on one side to the phase-change material of the phase-change memory cell and on an opposite side to a phase-change material of a neighboring phase-change memory cell. A method for producing a memory device for thermoelectric heat confinement is also provided.

Abstract: According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.

Abstract: A semiconductor device including a memory device configured to take a plurality of resistance states that are distinguishable from one another; a bias application section configured to apply, in a bias application period, a bias signal to the memory device; and a determination section configured to determine a resistance state of the memory device on the basis of a detection signal, in which the detection signal is generated in the memory device to which the bias signal is applied. The bias application section sets a length of the bias application period in accordance with a resistance value of the memory device, when the resistance state determined by the determination section is predetermined one of the resistance states.