Abstract: A non-volatile memory device includes a memory cell array including memory cells, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells, an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, and a data adjustment circuit. In operation, the read circuit assigns, based on the binary reference value, 0 or 1 to each of the pieces of resistance value information. In operation, the data adjustment circuit determines whether to adjust the binary reference value, in accordance with a difference between the numbers of pieces of digital data “0” and digital data “1” in the pieces of digital data.

Abstract: Disclosed are a semiconductor memory apparatus, a program method, and a program system. The semiconductor memory apparatus includes a memory cell array including a plurality of resistive memory cells and a control block configured to variably control, based on digital code values reflecting resistance states of the resistive memory cells, at least one of a initial voltage magnitude and an initial voltage applying time in an incremental step pulse programming (ISPP) mode for the plurality of memory cells. Therefore, even in the case of the worst cell, the incremental step of the ISPP may be minimized, and the writing time may be reduced, limiting unnecessary current consumption.

Abstract: This variable resistance element is provided with a variable resistance film, a first electrode, which is disposed in contact with one surface of the variable resistance film, and a second electrode, which is disposed in contact with the other surface of the variable resistance film. The first and the second electrodes have corner portions, respectively, and the distance between the corner portions of the first and the second electrodes is set equal to the shortest distance between the first and the second electrodes. Furthermore, the variable resistance element has a third electrode, which is disposed on the one surface of the variable resistance film.

Abstract: A resistive non-volatile memory cell is programmed. A programming voltage is applied to a first terminal of the resistive non-volatile memory cell. Sensing, during the applying the programming voltage, determines if the resistive non-volatile memory cell has been programmed. Current is limited through the resistive non-volatile memory cell to a first magnitude. After a predetermined time, if the sensing has not detected that the resistive non-volatile memory cell has been programmed, the current through the resistive non-volatile memory cell is limited to a second magnitude greater than the first magnitude. The resistive non-volatile memory cell is also erased.

Abstract: Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. In some examples, the multi-storage state non-volatile random access memory device has two or more memory cells. Each memory cell may include a pair of programmable resistive devices that may be dynamically programmed to configure the memory cell in a particular logic state.

Abstract: Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in series may be placed in complementary memory states any one of multiple memory states in write cycles by controlling a current and a voltage applied to terminals of the non-volatile memory device.

Abstract: A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

Abstract: Content addressable memory (CAM) devices provide for high density, low cost CAM devices. CAM devices include a non-volatile memory array having a plurality of NAND memory cell strings, wherein a NAND memory cell string of the non-volatile memory array comprises a plurality of CAM memory cells, and wherein the CAM memory cells comprise non-volatile memory cells of a same NAND memory cell string. The CAM devices further include a control circuit, wherein the control circuit is adapted to search data words stored in the plurality of NAND memory cell strings for a match to at least a portion of an input data word.

Abstract: Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a substrate and 3D array of nonvolatile memory cells, the 3D array including a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers, the top layer further comprises n?1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer and not extending into the bottom layers and a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.

Abstract: A level shift driver circuit comprises a level shift circuit and a driver circuit. The driver circuit comprises a first and a second P-type transistors and a first and a second N-type transistors coupled in series. When a first input signal of the level shift circuit is at an operative voltage, the level shift circuit turns off the second N-type transistor. A control terminal of the first N-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the second N-type transistor. When the first input signal is at a system base voltage, the level shift circuit turns off the first P-type transistor. A control terminal of the second P-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the first P-type transistor.

Abstract: A nonvolatile memory device includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the cell strings; floating ground selection lines connected to ground selection transistors of the cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.

Abstract: A memory device includes memory cells arranged in word lines. Due to variations in the fabrication process, with width and spacing between word lines can vary, resulting in widened threshold voltage distributions. In one approach, a programming parameter is optimized for each word line based on a measurement of the threshold voltage distributions in an initial programming operation. An adjustment to the programming parameter of a word line can be based, e.g., on measurements from adjacent word lines, and a position of the word line in a set of word lines. The programming parameter can include a programming mode such as a number of programming passes. Moreover, the programming parameters from one set of word lines can be used for another set of word lines having a similar physical layout due to the variations in the fabrication process.

Abstract: A semiconductor device and a method of operating the same are provided. The method includes determining whether a read operation on a selected page is a beginning read operation on the selected page; performing a least significant bit (LSB) read operation on the selected page when the read operation is the beginning read operation on the selected page according to a determination result, and performing a first sub-read operation on the selected page according to a result of the LSB read operation; and performing a second sub-read operation including the LSB read operation or a most significant bit (MSB) read operation on the selected page according to stored program state data when the read operation is not the beginning read operation on the selected page according to the determination result.

Abstract: A method of healing a plurality of non-volatile semiconductor memory devices on a multi-chip package is disclosed. The multi-chip package can be heated to a temperature range having a temperature range upper limit value and a temperature range lower limit value. The temperature of the multi-chip package can be kept essentially within the temperature range for a predetermined time period by monitoring a thermal sensing element with a sensing circuit outside of the multi-chip package. The thermal sensing element may be located near the components with the lowest failure temperature to ensure the multi-chip package is not damaged during the healing process.

Abstract: According to one embodiment, a memory system includes: a semiconductor memory device and a controller. The semiconductor memory device reads data a plurality of times from a first area, performs a majority operation on the read results, and transmits data based on the majority operation result to the controller as read data.

Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.

Abstract: Techniques are provided for operating a memory device which detect word line short circuits, such as short circuits between adjacent word lines. In an example implementation, during a programming operation, the number of program loops used to complete programming or reach another programming milestone for WLn are counted. If the number of program loops exceeds a loop count limit, the memory cells of WLn+1 are evaluated to determine whether a short circuit is present. The evaluation involves a read operation which counts erased state memory cells in the upper tail of the Vth distribution of WLn+1. If the count exceeds a bit count limit, it is concluded that a short circuit exits between WLn and WLn+1, and a corrective action is taken. The loop count limit is adjusted lower as the number of program-erase cycles increases.

Abstract: A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The verifying programming of the plurality of memory cells includes verifying programming for a first data state using a verify operation for a second data state. In one embodiment, the one or more control circuits are also configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to the different memory cells.

Abstract: A low power consuming read circuit for a memory array is disclosed. The circuit is particularly useful in applications where oxide breakdown one-time programmable memory is integrated into a system having low power available from the power sources supplying the system.

Abstract: According to one embodiment, a shift register memory device includes a shift register, a program/read element, and a rotating force application unit. The shift register includes a plurality of rotors arranged along one direction and provided with a uniaxial anisotropy. Each of the plurality of rotors has a characteristic direction rotatable around a rotational axis extending in the one direction. The program/read element is configured to program data to the shift register by causing the characteristic direction of one of the rotors to match one selected from two directions conforming to the uniaxial anisotropy and configured to read the data by detecting the characteristic direction. The rotating force application unit is configured to apply a rotating force to the shift register to urge the characteristic direction to rotate. The plurality of rotors are organized into a plurality of pairs of every two mutually adjacent rotors.

Abstract: A shift register circuit including a logic circuit capable of controlling the threshold voltage of a transistor and outputting a signal corresponding to an input signal by changing only the potential of a back gate without changing the potential of a gate is provided. In a shift register circuit including a logic circuit with a first transistor and a second transistor having the same conductivity type, a first gate electrode of the first transistor is connected to a source electrode or a drain electrode of the first transistor, an input signal is supplied to a second gate electrode of the first transistor, a clock signal is supplied to a gate electrode of the second transistor, and the first gate electrode and the gate electrode are formed from the same layer.

Abstract: A semiconductor integrated circuit device includes a first circuit block configured to receive data from a plurality of data I/O (input/output) lines and output test data in a test mode, and a second circuit block configured to connect the plurality of data I/O lines and the first circuit block, output the data of the plurality of data I/O lines in a normal mode and output the test data provided from the first circuit block in the test mode.

Abstract: Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.

Abstract: A method and an apparatus for identifying non-intrinsic defect bits from a population of failing bits for failure analysis to characterize the extrinsic failure mechanisms is provided. Embodiments include performing a failure mode test on a bank of a memory array at different low VDD; determining optimal bank size to observe plateaus of fail counts; determining fail counts of the bank at each different low VDD; determining a plateau of the fail counts; determining whether the plateau represents extrinsic bits of the bank; and submitting the extrinsic bits for root cause analysis.

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.

Abstract: A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once.

Abstract: The invention relates to a multilayer tubular part (1) comprising a metal layer forming a metal tubular body (3) and two layers in ceramic matrix composite material covering the metal tubular body, wherein one of the two layers in ceramic matrix composite material covers the inner surface of the metal tubular body to form an inner tubular body (4), whilst the other of the two layers in ceramic matrix composite material covers the outer surface of the metal tubular body to form an outer tubular body (2), the metal tubular body therefore being sandwiched between the inner and outer tubular bodies. The metal tubular body is in metal or metal alloy. Finally, the metal tubular body has a mean thickness smaller than the mean thicknesses of the inner and outer tubular bodies. A said part is useful in particular for producing nuclear fuel claddings.

Abstract: A nuclear reactor vessel structure includes an inner peripheral tube-shaped steel plate, an outer peripheral tube-shaped steel plate, and an intermediate tube-shaped steel plate disposed between the inner and outer peripheral tube-shaped steel plates, and is configured to support a nuclear reactor vessel on the inner peripheral side of a tube-shaped structure with concrete placed between the steel plates. The nuclear reactor vessel structure includes a support having a tube-shaped plate disposed on the inner peripheral side of the intermediate tube-shaped steel plate, and an annular plate which protrudes to the inner peripheral side of the tube-shaped plate and to which a connection section is affixed. The support is affixed to the concrete, which is placed between the inner peripheral and the intermediate tube-shaped steel plates, by first bar members, and the support is also affixed to the inner peripheral tube-shaped steel plate by second bar members.

Abstract: A light-reflective anisotropic conductive adhesive used for anisotropic conductive connection of a light-emitting element to a wiring board includes a thermosetting resin composition, conductive particles, and light-reflective insulating particles. The light-reflective insulating particles are at least one of inorganic particles selected from the group consisting of titanium oxide, boron nitride, zinc oxide, and aluminum oxide, or resin-coated metal particles formed by coating the surface of scale-like or spherical metal particles with an insulating resin.

Abstract: The high-withstanding-voltage member includes an alumina sintered compact containing alumina as a main crystal. Furthermore, the alumina sintered compact exhibits a peak intensity of 5000 or less at a wavelength of about 330 nm when measured by a cathode luminescence method.

Abstract: A multipair cable includes an inner layer part including two differential signal transmission cables for an inner layer that are twisted together, a press winding tape wound around a periphery of the inner layer part, and an outer layer part including a plurality of differential signal transmission cables for an outer layer that are wound around an outer periphery of the press winding tape. The inner layer part further includes a buffer tape disposed between the two differential signal transmission cables.

Abstract: An isolation system is provided for an electronic device that is configured to be mounted to a structure. The isolation system includes a flexible conductor configured to be electrically connected to the electronic device. The isolation system also includes an isolator configured to be coupled between the electronic device and the structure such that the isolator is configured to attenuate at least one of shock or vibration exerted on the electronic device. At least a portion of the isolator is electrically conductive. The isolator is electrically connected to the flexible conductor and is configured to be electrically connected to the structure such that the isolator provides an electrical path between the flexible conductor and the structure.

Abstract: A method of forming a microelectronic assembly includes positioning a support structure adjacent to an active region of a device but not extending onto the active region. The support structure has planar sections. Each planar section has a substantially uniform composition. The composition of at least one of the planar sections differs from the composition of at least one of the other planar sections. A lid is positioned in contact with the support structure and extends over the active region. The support structure is bonded to the device and to the lid.

Abstract: A cover sheath includes a main body being adapted to define a channel for accommodating at least one conducting cable extending there through, and a hook and loop arrangement disposed on at least a portion of an outer surface of the main body. The main body is made of an electrically conducting material.

Abstract: An organically surface-bonded metal or metal oxide material including an inorganic metal or metal oxide and an organic material. The organic material is coated on the surface of the inorganic metal or metal oxide. The inorganic metal or metal oxide and the organic material are linked through a strong chemical bond. The strong chemical bond includes a covalent bond between a metal in the inorganic metal or metal oxide and a nitrogen in the organic material.

Abstract: An R-T-B based sintered magnet maintains high magnetic properties and decreases usage of heavy rare earth elements. The magnet includes main phase grains and grain boundary phases, the main phase grain containing a core portion and a shell portion. X in the main phase LR(2-x)HRxT14B of the core portion ranges from 0.00 to 0.07; x in the main phase LR(2-x)HRxT14B of the shell portion ranges from 0.02 to 0.40; and the maximum thickness of the shell portion ranges from 7 nm to 100 nm. LR contains Nd and one or more light rare earth elements consisting of Y, La, Ce, Pr and Sm; HR contains Dy or/and Tb and one or more heavy rare earth elements consisting of Gd, Ho, Er, Tm, Yb and Lu; T contains Fe or/and Co and one or two kinds of Mn and Ni; and B represents boron partly replaced by C (carbon).

Abstract: The present invention provides a rare earth based magnet having a microstructure in which in a section of the R2T14B main-phase crystal grains, the number density of the fine products in the interior of (inside) the crystal grains is larger than that in the periphery of (outside) the crystal grains. That is, the rare earth based magnet includes R2T14B main-phase crystal grains and grain boundary phases formed between the R2T14B main-phase crystal grains. The R2T14B main-phase crystal grains include a substance where fine products are formed in the crystal grains. In the section of the main-phase crystal grains, when the crystal grains are divided into the interior of the crystal grains and the periphery of the crystal grains with a specific ellipse, the fine products are formed such that the number density in the interior is larger than that in the periphery.

Abstract: New magnetic materials containing cerium, iron, and small additions of a third element are disclosed. These materials comprise compounds Ce(Fe12?xMx) where x=1-4, having the ThMn12 tetragonal crystal structure (space group I4/mmm, #139). Compounds with M=B, Al, Si, P, S, Sc, Co, Ni, Zn, Ga, Ge, Zr, Nb, Hf, Ta, and W are identified theoretically, and one class of compounds based on M=Si has been synthesized. The Si cognates are characterized by large magnetic moments (4?Ms greater than 1.27 Tesla) and high Curie temperatures (264?Tc?305° C.). The Ce(Fe12?xMx) compound may contain one or more of Ti, V, Cr, and Mo in combination with an M element. Further enhancement in Tc is obtained by nitriding the Ce compounds through heat treatment in N2 gas while retaining the ThMn12 tetragonal crystal structure; for example CeFe10Si2N1.29 has Tc=426° C.

Abstract: A magnetic field generator (G1) for a magnetocaloric thermal device which comprises first (SM11) and second (SM21) identical magnetizing structures mounted head-to-tail, on either side of a central plane (P) and defining two air gaps (E1, E2). Each magnetizing structure (SMM11, SM12) comprises first (AM1) and second (AM2) magnetizing assemblies, whose induction vectors are oriented in opposite directions, and mounted on a support (SUP1). Each magnetizing assembly (AM1, AM2) has a permanent magnet structure (API, APC) which comprises a passive side (FP1, FP2) and an active side (FA1, FA2), delimiting the air gaps (E1, E2). The induction vectors of the first (AM1, AM19) and the second (AM2, AM29) magnetizing assemblies, form inside the generator, a single circulation loop of a magnetic field through the supports (SUP1) and the air gaps (E1, E2, E3, E4).

Abstract: A system and methods for redundant current-sum feedback control of an actuator system is presented. An actuator comprises actuation coils configured to actuate the actuator, and an actuation coil current sensor senses a measured total coil current comprising a sum of coil currents of each of the actuation coils. Actuator coil controllers control the actuation coils based on a commanded total coil current and the measured total coil current.

Abstract: Apparatus and methods to magnetize and demagnetize the magnetic poles of a rotor assembly for an electrical machine, such as a generator. The apparatus and methods provide for individually magnetize magnetic domains in the permanent magnetic material of the magnetic poles of a rotor assembly of the electrical machine after the electrical machine is installed in a larger assembly. The magnetization system may be used to magnetize and demagnetize the magnetic poles while the rotor assembly is connected with a prime mover, such a rotor of a wind turbine.

Abstract: In some embodiments, an exemplary inventive device of the instant invention is a reactor which includes at least the following: a core, including: at least one leg, including: a first lamination, where the first lamination is made from a high permeability material, where the high permeability material has a magnetic permeability that is at least 1000 times greater than the permeability of air; a second lamination, where second lamination is made from the high permeability material; a bracket, where the bracket is configured to secure the first lamination and the second lamination in a spatial arrangement to have a space between each other; and a plurality of blocks made from a low permeability material, where the low permeability material has the magnetic permeability that is less than 100 times the permeability of air.

Abstract: A transformer filter arrangement (30) for passing signals at a fundamental frequency and suppressing signals at one or more interfering frequencies is disclosed. It comprises a transformer (100) having a first winding (110) and a second winding (120), wherein the first winding (110) has a first end (112a) and a second end (122b) and the second winding (120) has a first end (122a) and a second end (122b). It further comprises one or more capacitors (130a-e).

Abstract: An ignition coil for an internal combustion engine includes a wire-wound resistor. The wire-wound resistor includes a core material, a conductor winding, a pair of metal caps disposed at both ends of the core material, the pair of metal caps in contact with the conductor winding, and a resin coating material disposed so as to be in close contact with the core material and the conductor winding. The resin coating material is filled between the conductive winding and the resin coating material is formed to cover the conductor winding from an outer peripheral side of the conductor winding The metal cap includes a bottom portion and a cylindrical side portion. An inner peripheral side of the side portion is provide with ridges projecting internally formed along a direction crossing a winding direction of the conductor winding.

Abstract: The present invention provides a sintered magnet having superior residual magnetic flux density and coercive force. The sintered magnet of the present invention comprises a group of R-T-B based rare earth magnet crystal particles 2 having a core 4 and a shell 6 covering the core 4, the mass ratio of a heavy rare earth element in the shell 6 is higher than the mass ratio of a heavy rare earth element in the core 4, and the thickest part of the shell 6 in the crystal particles 2 faces a grain boundary triple junction 1. A lattice defect 3 is formed between the core 4 and the shell 6.

Abstract: A three-dimensional multipath inductor includes turns disposed about a center region on two layers, the turns on the two layers having corresponding geometry therebetween. Each of the turns is comprised of two or more segments that extend length-wise along the turns, and the segments have positions that vary from an innermost position relative to the center region and an outermost position relative to the center region. A lateral cross-over is configured to couple the segments of at least one turn on one layer with the segments on a turn on a same layer to form segment paths that have a substantially same length for all segment paths in a grouping of segment paths on that same layer. A vertical cross-over is configured to couple the segments on different vertically stacked metal layers to have the segment groups with a substantially same length for all segment paths based on vertical lengths.

Abstract: A multilayer ceramic capacitor includes flat-shaped inner electrodes that are laminated. An interposer includes an insulating substrate that is larger than contours of the multilayer ceramic capacitor. A first mounting electrode that mounts the multilayer ceramic capacitor is located on a first principal surface of the insulating substrate, and a first external connection electrode for connection to an external circuit board located on a second principal surface. The multilayer ceramic capacitor is mounted onto the interposer in such a way that the principal surfaces of the inner electrodes are parallel or substantially parallel to the principal surface of the interposer, that is, the first and second principal surfaces of the insulating substrate.

Abstract: A cast raw sheet for a capacitor film, prepared by heating and melting a polypropylene resin and extruding the resin from a T-die, wherein the polypropylene resin has: a weight average molecular weight, determined by gel permeation chromatography, of 100,000 or more and 500,000 or less; and a molecular weight distribution Mw/Mn of 7 or more, the resin contains 97% by mass or more of an isotactic component that is an extraction residue obtained by sequential extraction, and the cast raw sheet contains a ?-form in a proportion of 1% or more and less than 20%, the proportion being determined by X-ray diffraction intensity.

Abstract: A dielectric thin film element having a high humidity resistance is provided. A dielectric thin film element includes a capacitance section having a dielectric layer and a pair of electrode layers formed on the respective upper and lower surfaces of the dielectric layer. Furthermore, a protection layer is provided on the capacitance section, a pair of interconnect layers are drawn out to an upper surface of the protection layer, and external electrodes are formed to be electrically connected to the interconnect layers. Further, first surface metal layers cover a portion of the interconnect layers that extends along the inner surface of the openings and second surface metal layers are formed at end of the first surface metal layers.

Abstract: Disclosed is a capacitor. The capacitor includes a plurality of capacitor units connected to each other in parallel. The capacitor unit includes a first capacitor, a second capacitor connected to the first capacitor in parallel, and a switch selectively connected to the first capacitor or the second capacitor.