Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

Abstract: A plasma etching method includes a first process of applying, while applying a first high frequency power to a lower electrode, a second high frequency power to the lower electrode while switching the second high frequency power ON and OFF cyclically; and a second process of applying, while applying the first high frequency power to the lower electrode, the second high frequency power to the lower electrode while maintaining the second high frequency power ON continuously. The first process and the second process are alternately performed. If the deposits are formed on a bottom portion of an inner surface of the hole formed by the etching, the inner surface of the hole is protected by the deposits from the ions introduced into the hole. Therefore, the etching of the inner surface of the hole can be suppressed, and, thus, the twisting of the hole can also be suppressed.

Abstract: An endoprosthesis, a method for imaging an endoprosthesis, a method of making an endoprosthesis involve a polymeric substrate that has been modified to have voids embedded within the substrate. The voids are sized to scatter optical radiation from within the substrate so that an optical coherence tomography (OCT) image can be obtained in which an interior region of the substrate can be easily differentiated from empty space and other structures that surround the endoprosthesis. The voids allow for OCT visualization of the polymeric substrate which may be difficult to visualize by other methods such as fluoroscopy.

Abstract: A method of adjusting channel widths of semiconductive devices includes providing a substrate divided into a first region and a second region, wherein the substrate comprises numerous fins. A first implantation process is performed on the fins within the first region. Then, a second implantation process is performed on the fins within the second region, wherein the first implantation process and the second implantation process are different from each other in at least one of the conditions comprising dopant species, dopant dosage or implantation energy. After that, part of the fins within the first region and the second region are removed simultaneously to form a plurality of first recesses within the first region and a plurality of second recesses within the second region. Finally, a first epitaxial layer and a second epitaxial layer are formed to fill up each first recess and each second recess, respectively.

Abstract: An etching method containing, at the time of processing a substrate having a first layer containing titanium nitride (TiN) and a second layer containing a transition metal, selecting a substrate in which a surface oxygen content of the first layer is from 0.1 to 10% by mole, and applying an etching liquid containing a hydrofluoric acid compound and an oxidizing agent to the substrate and thereby removing the first layer.

Abstract: There is disclosed a method of preserving the integrity of a growth substrate in a epitaxial lift-off method, the method comprising providing a structure comprising a growth substrate, one or more protective layers, a sacrificial layer, and at least one epilayer, wherein the sacrificial layer and the one or more protective layers are positioned between the growth substrate and the at least one epilayer; releasing the at least one epilayer by etching the sacrificial layer with an etchant; and heat treating the growth substrate and/or at least one of the protective layers.

Abstract: A carrier structure is provided, which includes: a metal oxide plate having opposite first and second surfaces and a plurality of through holes penetrating the first and second surfaces; a plurality of conductive portions formed in the through holes, respectively; and a plurality of conductive pads formed on the first surface of the metal oxide plate, wherein each of the conductive pads is correspondingly positioned on and in contact with a plurality of the conductive portions so as to be electrically connected to the plurality of the conductive portions. By replacing a conventional silicon interposer with the metal oxide plate, the present invention eliminates the need to form through silicon vias as required in the prior art and therefore simplifies the fabrication process.

Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.

Abstract: The wet treatment of wafer-shaped articles is improved by utilizing a droplet generator designed to produce a spray of monodisperse droplets. The droplet generator is mounted above a spin chuck, and is moved across a major surface of the wafer-shaped article in a linear or arcuate path. The droplet generator includes a transducer acoustically coupled to its body such that sonic energy reaches a region of the body surrounding the discharge orifices. Each orifice has a width w of at least 1 ?m and at most 200 ?m and a height h such that a ratio of h to w is not greater than 1.

Abstract: A brush-cleaning apparatus is disclosed for use in cleaning a semiconductor wafer after polishing. Embodiments of the brush-cleaning apparatus implemented with a multi-branch chemical dispensing unit are applied beneficially to clean semiconductor wafers, post-polish, using a hybrid cleaning method. An exemplary hybrid cleaning method employs a two-chemical sequence in which first and second chemical treatment modules are separate from one another, and are followed by a pH-neutralizing-rinse that occurs in a treatment module separate from the first and second chemical treatment modules. Implementation of such hybrid methods is facilitated by the multi-branch chemical dispensing unit, which provides separate chemical lines to different chemical treatment modules, and dispenses chemical to at least four different areas of each wafer during single-wafer processing in an upright orientation.

Abstract: A device and method for processing wafer-shaped articles comprises a process chamber and a rotary chuck located within the process chamber. The rotary chuck is adapted to be driven without physical contact through a magnetic bearing. The rotary chuck comprises a series of gripping pins adapted to hold a wafer shaped article in a position depending downwardly from the rotary chuck. The rotary chuck further comprises a plate that rotates together with the rotary chuck. The plate is positioned above an area occupied by the wafer-shaped article, and shields upper surfaces of the process chamber from liquids flung off of a wafer-shaped article during use of the rotary chuck.

Abstract: A method and apparatus to modify the surface structure of a silicon substrate or deposited silicon layer in a controllable manner using gas only in an atmospheric environment, suitable for making photovoltaic (PV) wafer based devices. The method and apparatus comprising the steps of disposing the substrate or deposited layer on a moveable carrier; pre-heating the substrate or deposited layer; and moving the substrate or deposited layer for etching through an atmospheric reactor; under an etchant delivering module inside the reactor and applying at least one etchant in gas form at a controlled flow rate and angle to the substrate or deposited layer in the reactor, wherein the at least one etchant gas is selected from the group comprising fluoride-containing gases and chlorine-based compounds. The technical problem that has been solved is the provision of a high throughput dry etching method at atmospheric pressure.

Abstract: An edge bead removal apparatus is provided. The edge bead removal apparatus includes a clamping unit configured to clamp a cylindrical reticle and cause the cylindrical reticle to incline with a pre-determined angle and to rotate around a central axis. The edge bead removal apparatus also includes an edge bead removal solvent nozzle configured to spray an edge bead removal solvent to remove edge beads on both edges of the cylindrical reticle.

Abstract: A high-frequency power supply includes a shaft bonded to one surface of a plate serving as a gas distributor plate. The plate includes a radio-frequency electrode buried therein. The shaft has a through-hole through which a gas flows. The plate and the shaft are made of a ceramic material. The shaft has a double-tube structure including the inner tube and the outer tube . The interior space of the inner tube forms the through-hole. The plate is hermetically solid-state bonded to the inner tube and the outer tube. The shaft is bonded to the center of the plate.

Abstract: A microwave induced plasma decapsulation system and method for decapsulation a packaged semiconductor device applies a microwave induced plasma effluent along with etchant gases electrons, ions and free radicals that are chemically reactive to remove the epoxy molding compound encapsulating the semiconductor device. In one embodiment, the decapsulation system utilizes a microwave generator and a coaxial plasma source. In another embodiment, the decapsulation system utilizes a microwave generator, an electromagnetic surface wave plasma source, and a dielectric plasma discharge tube.

Abstract: Methods of depositing tungsten in different sized features on a substrate are provided herein. The methods involve depositing a first bulk layer of tungsten in the features, etching the deposited tungsten, depositing a second bulk tungsten, which is interrupted to treat the tungsten after the smaller features are completely filled, and resuming deposition of the second bulk layer after treatment to deposit smaller, smoother tungsten grains into the large features. The methods also involve depositing tungsten in multiple cycles of dep-etch-dep, where each cycle targets a group of similarly sized features using etch chemistry specific for that group, and depositing in groups from smallest sized features to the largest sized features. Deposition using methods described herein produce smaller, smoother grains with void-free fill for a wide range of sized features in a substrate.

Abstract: The present invention shortens the time needed to decrease the oxygen concentration in a chamber to be filled with an inert gas to a desired concentration. A substrate processing apparatus includes: a processing chamber configured to process a substrate; and a carrying chamber configured to carry the substrate to the processing chamber. The carrying chamber includes: a plurality of wall bodies configured to form a housing of the carrying chamber; a joint at which the plurality of wall bodies are joined; an isolated space creating member configured to cover the joint and thereby create an isolated space separated from the carrying chamber; and an exhaust section configured to purge gas in the isolated space.

Abstract: A temporary storage device transfers an article in different positions to and from an overhead travelling vehicle system and a second transport system, and transfers an article to and from an article transfer position outside the temporary storage device. The temporary storage device includes a local carrier including a hoist, travel rails of the local carrier below a travel rail of the overhead travelling vehicle system, passing directly above an article transfer position, and a slide rack below the travel rails of the local carrier, slidable between a portion directly above the transfer position and a second position in which an article can be transferred to and from the second transport system, the second position being different from the portion directly above the transfer position in a direction perpendicular or substantially perpendicular to the travel rails of the local carrier in a horizontal plane.

Abstract: An apparatus including a drive; a movable arm assembly; a plurality of sets of end effectors; and a controller. The end effectors are connected to the drive by the movable arm assembly. A first one of the sets of end effectors includes at least two of the end effectors, where the drive and the movable arm assembly are configured to move the at least two end effectors substantially in unison from a retracted position towards an extended position towards two different respective target locations. The at least two end effectors are at least partially independently movable relative to each other on the moveable arm assembly. The controller is configured to detect an offset of respective substrates on the at least two end effectors and adjust movement of the at least two end effectors relative to each other prior to placement of the substrates at the respective target locations.

Abstract: An attaching apparatus, a substrate and a support that can be uniformly attached through an adhesive layer. The attaching apparatus is equipped with a set plate and a press plate formed of ceramics. The set plate and the press plate have a flatness of 1.0 ?m or less when not pressed.

Abstract: A micro device transfer head array and method of forming a micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect. A dielectric layer covers a top surface of each mesa structure.

Abstract: This disclosure provides a package substrate, a flip-chip package circuit and their fabrication method. The package substrate includes: a first wiring layer having a first metal wire and a first dielectric material layer filling the remaining part of the first wiring layer except for the first metal wire; a conductive pillar layer formed on the first wiring layer and including a metal pillar connected to the first metal wire, a molding compound layer with a protrusion part surrounding the metal pillar, and a second dielectric material layer formed on the molding compound layer; a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the metal pillar; and a protection layer formed on the second wiring layer.

Abstract: A method comprises providing a handle substrate having a front surface and a back surface; providing a layer of flexible semiconductor material having a front surface and a back surface and an at least partially sacrificial backing layer stack on the back surface of the layer of flexible semiconductor material; bonding the front surface of the layer of flexible semiconductor material to the front surface of the handle substrate; removing at least a portion of the at least partially sacrificial backing layer stack from the back surface of the layer of flexible semiconductor material; opening outgassing paths through the layer of flexible semiconductor material; and processing the layer of flexible semiconductor material.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement region. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region.

Abstract: A method for manufacturing a semiconductor device, comprises forming an organic planarization layer on a plurality of gates on a substrate, wherein the plurality of gates each include a spacer layer thereon, forming an oxide layer on the organic planarization layer, removing a portion of the oxide layer to expose the organic planarization layer, stripping the organic planarization layer to form a cavity, patterning a direct lithographically-patternable gap dielectric on at least one of the gates in the cavity, and depositing a conductive contact in a remaining portion of the cavity.

Abstract: A gate structure is first formed on a substrate and an interlayer dielectric (ILD) layer is formed around the gate structure, a dielectric layer is formed on the ILD layer and the gate structure, an opening is formed in the dielectric layer and the ILD layer, and an organic dielectric layer (ODL) is formed on the dielectric layer and in the opening. After removing part of the ODL, part of the dielectric layer to extend the opening, and then the remaining ODL, a contact plug is formed in the opening.

Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metalization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 ?m larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.

Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

Abstract: The invention provides a fast, scalable, room temperature process for fabricating metallic nanorods from nanoparticles or fabricating metallic or semiconducting nanorods from carbon nanotubes suspended in an aqueous solution. The assembled nanorods are suitable for use as nanoscale interconnects in CMOS-based devices and sensors. Metallic nanoparticles or carbon nanotubes are assembled into lithographically patterned vias by applying an external electric field. Since the dimensions of nanorods are controlled by the dimensions of vias, the nanorod dimensions can be scaled down to the low nanometer range. The aqueous assembly process is environmentally friendly and can be used to make nanorods using different types of metallic particles as well as semiconducting and metallic nanotubes.

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

Abstract: Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first metal layer and a plurality of dielectric layers on top of the first metal layer; creating one or more openings through the plurality of dielectric layers to expose the first metal layer underneath the plurality of dielectric layers; causing the one or more openings to expand downward into the first metal layer and expand horizontally into areas underneath the plurality of dielectric layers; applying a layer of lining material in lining sidewalls of the one or more openings inside the plurality of dielectric layers; and filling the expanded one or more openings with a conductive material.

Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.

Abstract: A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.

Abstract: A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.

Abstract: According to various embodiments, a method of processing a substrate may include: forming a plurality of trenches into a substrate between two chip structures in the substrate, the trenches defining at least one pillar between the two chip structures and a sidewall on each of said two chip structures; disposing an auxiliary carrier on the substrate to hold the chip structures and the at least one pillar; at least partially filling the trenches with encapsulation material to cover the at least one pillar and the sidewalls, thereby at least partially encapsulating the chip structures; removing a portion of the encapsulation material to expose at least a portion of the at least one pillar; and at least partially removing the at least one pillar.

Abstract: A method includes forming a plurality of fins above a substrate. A first mask layer is formed above a first subset of the fins. First portions of the fins in the first subset exposed by a first opening in the first mask layer are removed to define, for each of the fins, a first fin segment and a second fin segment, each having a cut end surface. A first liner layer is formed on at least the cut end surface of the first fin segment for each of the fins in the first subset. A second mask layer having a second opening is formed above a second subset of the plurality of fins. An etching process removes second portions of the second subset of fins exposed by the second opening. The first liner layer protects the cut end surface of at least the first fin segment during the removing.

Abstract: A semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate, and at least one metal gate stack formed on the upper surface of the semiconductor substrate. One or more pairs of source/drain contact structures are formed on the upper surface of the semiconductor fin. Each source/drain contact structure includes a metal contact stack, a spacer, and a cap spacer. The metal contact stack is formed on the upper surface of the fin. The spacer is interposed between a contact sidewall of the metal contact stack and a gate sidewall of the at least one metal gate stack. The cap spacer is formed on an upper surface of the metal contact stack and has a cap portion disposed against the spacer such that the metal gate stack is interposed between the opposing source/drain contact structures.

Abstract: A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.

Abstract: A curable composition including: an epoxy resin; and an amine curing component including: an aromatic amine curing agent; and a solubilizer including an aliphatic amine, a cycloaliphatic amine, a non-volatile primary alcohol, non-volatile solvent or a mixture thereof. An electronic assembly including: a substrate; an underfill including a cured product of the curable composition on the substrate; and a ball grid array on the underfill is also disclosed.

Abstract: A method of manufacturing a semiconductor device and a semiconductor device that is manufactured by the method. In the method of manufacturing a semiconductor device, a releasing sheet is disposed in close contact with a hole of an aluminum plate having the recessed hole, and a skeleton structure of a semiconductor device is put into the recessed hole. Then, liquid epoxy resin is poured into the recessed hole. After hardening, the epoxy resin body 10 including the skeleton structure is taken out from the recessed hole to complete manufacturing the semiconductor device. Using a simple molding jig including the aluminum plate, and covering the skeleton structure with the epoxy resin body, a highly reliable semiconductor device with a case-less construction can be manufactured.

Abstract: A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Abstract: An integrated circuit (IC) package has a base, side walls mechanically connected to the base, IC dies respectively mounted on inner surfaces of the side walls or the base, and electrical connections connecting a corresponding IC die to another component of the IC package. In one embodiment, each die is electrically connected to only bond pads on its corresponding side wall or base. Each such side wall and the base have routing structures (e.g., copper traces) that connect each bond pad to another component of the IC package. The IC package is assembled using a flexible substrate that has side regions that rotate relative to the base such that the routing structures do not break. By connecting an IC die only to bond pads on its corresponding side wall or base with bond wires, the bond wires will not break during side-wall rotation.

Abstract: The present disclosure provides embodiments for a semiconductor structure including a heat spreader that includes a graphene grid having a first major surface and a second major surface opposite the first major surface. The graphene grid has a plurality of holes, each hole having a first opening in the first major surface and a second opening in the second major surface. The heat spreader also includes a first copper portion covering the first major surface of the graphene grid, a second copper portion covering the second major surface of the graphene grid, and a plurality of copper vias filling the plurality of holes.

Abstract: A semiconductor device structure includes a layer of III-V compound semiconductor material, a layer of polycrystalline CVD diamond material, and an interface region with a diamond nucleation layer. A Raman signal of the diamond nucleation layer exhibits an sp3 carbon peak at 1332 cm?1 having a full width half maximum of no more than 5.0 cm?1, and one or both of: (i) an sp2 carbon peak at 1550 cm?1 having a height which is no more than 20% of a height of the sp3 carbon peak at 1332 cm?1 after background subtraction when using a Raman excitation source at 633 nm; and (ii) the sp3 carbon peak at 1332 cm?1 is no less than 10% of local background intensity in a Raman spectrum using a Raman excitation source at 785 nm. An average nucleation density at a nucleation surface is no less than 1×108 cm?2 and no more than 1×1012 cm?2.

Abstract: A semiconductor device that does not produce nonlinearities attributed to a high resistivity silicon handle interfaced with a dielectric region of a buried oxide (BOX) layer is disclosed. The semiconductor device includes a semiconductor stack structure with a first surface and a second surface wherein the second surface is on an opposite side of the semiconductor stack structure from the first surface. At least one device terminal is included in the semiconductor stack structure and at least one electrical contact extends from the second surface and is electrically coupled to the at least one device terminal. The semiconductor stack is protected by a polymer disposed on the first surface of the semiconductor stack. The polymer has high thermal conductivity and high electrical resistivity.

Abstract: A method for manufacturing a semiconductor device comprises forming a first layer on an impurity diffusion region in a semiconductor substrate by a selective epitaxial growth method, forming a second layer on the first layer by the selective epitaxial growth method, forming a contact hole penetrating an interlayer insulating film in a thickness direction thereof and reaching the second layer, and filling a conductive material into the contact hole to form a contact plug including the first and second layers and the conductive material.

Abstract: Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug.

Abstract: A lead frame of high quality which can endure direct bonding to a semiconductor element, and a semiconductor device of high reliability which utilizing the lead frame. A lead frame includes a plurality of connected units, each unit including a pair of lead portions arranged spaced apart and opposite from each other, for mounting a semiconductor element and electrically connecting to a pair of electrodes of the semiconductor element respectively. The lead portions respectively include an element mounting region arranged on a surface thereof to mount the semiconductor element, and a groove extending from opposing end surfaces of each of the pair of lead portions, in a direction away from the end surfaces and bending in a surrounding manner along outer periphery of the element mounting region.

Abstract: In a semiconductor package, surfaces of a die pad, a semiconductor element, a connecting member, and a lead are subjected to a surface treatment with a silane coupling agent. A first surface of a plurality of surfaces of the semiconductor device includes a first region where an organic substance is exposed, and a second region where an inorganic substance is exposed, the first surface being bonded with the connecting member. A bonding strength between the first region and the sealing resin is weaker than a bonding strength between the second region and the sealing resin.