Abstract: A first normal bit and source lines are connected to a first memory cell. Second normal bit and source lines are connected to a second memory cell. A first column switch connects one of the first and second normal bit lines to a first global bit line. A second column switch connects one of the first and second normal source lines to a first global source line. A first reference bit and source lines are connected to a third memory cell. A third column switch connects the first reference bit line to a second global bit line. A fourth column switch connects the first reference source line to the first global source line. A sense amplifier is connected to the first and second global bit lines, and reads data stored in one of the first and second memory cells.

Abstract: A magnetic random access memory (MRAM) array including: a plurality of MRAM cells arranged in an array configuration, each comprising a first type nTron and a magnetic memory element; a wordline select circuit comprising of a second type nTron to drive a plurality of parallel wordlines; and a plurality of bitline select circuits, each comprising of said second type nTron for writing to and reading from a column of memory cells in the array and each capable of selecting a single MRAM cell for a memory read or write operation, wherein the second nTron has a higher current drive than the first nTron.

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various operating techniques or additional circuit components, or both. For example, a switching component connected to a digit line may also be connected to an offset capacitor selected to compensate for a threshold voltage offset. The offset capacitor may be discharged in conjunction with a read operation, resulting in a threshold voltage applied to the switching component. This may enable all or substantially all of the stored charge of the ferroelectric memory cell to be extracted and transferred to a sense capacitor through the transistor. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: The present invention is provided with: subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK1 or VKK2 to the subword drivers SWD, and memory cells MC that are selected in the case when the subword line SWL is set to an active potential VPP and are not selected in the case when the subword line SWL is either a negative potential VKK1 or VKK2.

Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.

Abstract: A memory device including first to fourth cell blocks, each including a plurality of normal columns and one or more redundancy columns and a control unit suitable for repairing the normal columns using the redundancy columns in the first and the second cell blocks using first repair information and repairing the normal columns using the redundancy columns in the third and the fourth cell blocks using second repair information when the memory device is set as a first mode, and suitable for repairing the normal columns using the redundancy columns in the first and the third cell blocks using the first repair information and repairing the normal columns using the redundancy columns in the second and the fourth cell blocks using the second repair information when the memory device is set as a second mode.

Abstract: Embodiments herein describe DRAM that includes storage circuitry coupled between complementary bit lines which are in turn coupled to the same sense amplifier. The storage circuitry includes a transistor and a storage capacitor coupled in series. The gate of the transistor is coupled to a word line which selectively couples the storage capacitor to one of the complementary bit lines. Because the capacitor is coupled to both of the bit lines, when reading the data stored on the capacitor, the charge on the capacitor causes current to flow from one of the bit lines into the other bit line which causes a voltage difference between the complementary bit lines. Put differently, both ends of the capacitor are electrically coupled to bit lines thereby generating a larger voltage difference between the bit lines when reading data from the storage capacitors.

Abstract: An apparatus includes a memory and a circuit. The memory may have a transmitter. The memory may be configured to (a) train transmit parameters of the transmitter that synchronize transmission of data with a clock signal while in a first mode, (b) save the transmit parameters in response to a command received while in the first mode, and (c) transmit additional data while in a second mode using the transmit parameters learned while in the first mode. The circuit may have a receiver in communication with the memory. The circuit may be configured to (a) train receive parameters of the receiver that synchronize reception of the data with the clock signal while the memory is in the first mode and (b) receive the additional data from the memory while the memory is in the second mode using the receive parameters learned while the memory was in the first mode.

Abstract: Hybrid Super Threshold (SupVt) circuits are CMOS circuits that can function in two different operation modes: a normal operation mode and a SupVt power saving mode. At normal operation mode, a hybrid SupVt circuit operates in the same ways as typical CMOS circuits. At SupVt mode, the standby leakage current of the circuit is reduced significantly, while the circuit still can function at high speed. Typically, most parts of a hybrid SupVt circuit stay in power saving mode. A circuit block is switched into normal operation mode when it needs to operate at full speed. The resulting circuits are capable of supporting ultra-low power operations without sacrificing performance.

Abstract: Disclosed is a memory device. The memory device includes a bit-cell comprising a cross-coupled inverter and pass gate transistor connected to data storage node of the cross-coupled inverter, a read buffer transistor having a drain terminal connected to a bit line for read operation and a gate terminal connected to the pass gate transistor, a write operation transistor connected between the pass gate transistor and a bit line for write operation, and a drive transistor unit which is connected to a local line between the pass gate transistors and the write operation transistor and which provide a voltage to a gate terminal of the read buffer transistor based on a data value stored at the bit-cell.

Abstract: A device includes memory cells, reference memory cells, and a sensing unit. The reference memory cells are configured to store first bit data, second bit data, third bit data, and fourth bit data, in which the first bit data and the fourth bit data are configured to be a high logic state, and the second bit data and the third bit data are configured to be a low logic state. The sensing unit is configured to read bit data stored in one of the memory cells according to the first bit data, the second bit data, the third bit data, and the fourth bit data.

Abstract: A combined memory block includes a first memory unit configured to store data and an additional memory unit that forms a stacked structure with the memory unit, wherein the memory unit and the storage unit together form multi-level cells having variable resistance in storing data.

Abstract: The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to provide a programming signal to a memory cell in the array, the programming signal associated with programming the memory cell to a particular data state; and determine, via an integration component, if a data state of the memory cell changes to a different data state responsive to the programming signal being provided.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.

Abstract: A nonvolatile memory device is writable to a high resistance state and a low resistance state. The nonvolatile memory device may be heated to at least a threshold temperature, based on application of an alternating current (AC) signal, and may be written based on application of a voltage bias.

Abstract: A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.

Abstract: A method of resetting a variable resistance memory cell in a nonvolatile memory device includes; programming the memory cell to a set state using a corresponding compliance current, and then programming the memory cell to a reset state by pre-reading the variable resistance memory cell to determine its resistance and resetting the memory cell using a variable reset voltage determined in response to the determined resistance.

Abstract: A reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays for stuck bits. The FRAM devices are subjected to a high temperature bake in wafer form. A “shmoo” of the reference voltage is performed, at an elevated temperature, for each device to identify a first reference voltage at which a first cell in the device fails a read of its low polarization capacitance data state, and a second reference voltage at which a selected number of cells in the device fail the read. The slope of the line between the first and second reference voltages, in the cumulative fail bit count versus reference voltage plane, is compared with a slope limit to determine whether any stuck bits are present in the device.

Abstract: A search system is obtained by combining a TCAM and a search engine not using the TCAM. The search engine not using the TCAM is constructed using a general-purpose memory cell structure, and includes a different-sized memory spaces each corresponding to an effective bit length of search target data.

Abstract: A non-volatile memory includes an data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.

Abstract: A semiconductor memory device includes a plurality of memory cells connected to a plurality of word lines; a peripheral circuit suitable for applying a program pulse to at least one of the word lines, performing a program verification operation to the plurality of memory cells by using a first program verification voltage; and a control logic suitable for controlling the peripheral circuit to repeat the applying of the program pulse and the performing the program verification operation until program verification passes by increasing a level of the program pulse by an amount of a step voltage at each repetition, wherein a size of the step voltage decreases at each repetition.

Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.

Abstract: A non-volatile memory system mitigates the effects of open block reading by analyzing the un-programmed region of a block before programming to determine a potential for read disturbance. The system may determine a read count value associated with open block reading of the memory block and/or perform partial block erase verification. To mitigate the effects of open block read disturbance, the system performs partial block erase for the un-programmed region of the memory block and/or limits programming in the un-programmed region.

Abstract: A method is provided for driving a nonvolatile memory device, including multiple strings, where each string is formed by penetrating plate-shaped word lines stacked on a substrate. The method includes configuring the word lines of a string in multiple zones based on zone configuration information, and applying zone voltages to the zones, respectively. The zone configuration information is varied according to a mode of operation.

Abstract: A memory system includes: a bit counter and a regression analyzer. The bit counter is configured to generate a plurality of count values based on data read from selected memory cells using a plurality of different read voltages, each of the plurality of count values being indicative of a number of memory cells of a memory device having threshold voltages between pairs of the plurality of different read voltages. The regression analyzer is configured to determine read voltage for the selected memory cells based on the plurality of count values using regression analysis.

Abstract: Methods and devices for data sensing are disclosed. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.

Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Abstract: The embodiments described herein provide antifuse devices and methods that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes an antifuse, a first diode coupled with the antifuse in a parallel combination, and a second diode coupled in series with the parallel combination. In such an embodiment the first diode effectively provides a bypass current path that can reduce the voltage across the antifuse when other antifuses are being programmed. As such, these embodiments can provide improved ability to tolerate programming voltages without damage or impairment of reliability.

Abstract: A display panel includes: gate and data lines; pixels connected to the gate and data lines; and a stage includes: a pull-up driver including an output terminal of the stage and which outputs a gate-on voltage, an output pull-down unit which pulls down an output terminal of the stage, a reset unit which changes a voltage of a second node into a low voltage based on a voltage of the output terminal of the stage, a first node pull-up unit which changes a first node into a high voltage based on a gate-on voltage from a previous stage, a first node pull-down unit which changes the first node into the low voltage based on the gate-on voltage from a subsequent stage, and a first node reset unit which changes the voltage of the first node into the low voltage based on the voltage of the second node.

Abstract: A sampling circuit uses an input stage to sample an input signal and a secondary evaluation stage to maintain the output state of the input stage. Once the input stage transitions at a clock transition, the secondary evaluation stage uses regenerative feedback devices to hold the state to help ensure the sampling circuit only switches once during an evaluation.

Abstract: A sample-and-hold circuit is provided. The sample-and-hold circuit includes an input one or more dedicated capacitive elements, one or more parasitic capacitive elements connected to said one or more dedicated capacitive elements, an output, a group of switches, and a control unit. The control unit controls said switches so as to interconnect said input, said one or more dedicated capacitive elements, and said output in a cyclic manner in accordance with a sample-and-hold cycle.

Abstract: An embodiment may include a first replica driver group configured for replicating an output driver of a physical area. A second replica driver group configured for replicating an output driver of a test electrode area for direct access of a memory, and an impedance calibration unit configured to independently perform an impedance matching operation of the first replica driver group and the second replica driver group.

Abstract: Memory devices storing particular data, systems containing such memory devices and methods of testing such memory devices. The memory devices include an array of memory cells containing particular data, and control circuitry configured to control operations of the array of memory cells.

Abstract: Provided are a nonvolatile memory and a data reading method of reading data from a nonvolatile memory by the memory controller. The data reading method includes reading data from memory cells of the nonvolatile memory, storing the read data in the internal memory, overwriting some of the read data stored in the internal memory with backup data, performing an error correction operation using the backup data stored in the internal memory, and overwriting the backup data stored in the internal memory with data corrected by the error correction operation.

Abstract: Systems and methods for capturing waste are disclosed. The systems and methods provide for a high level of confinement and long term stability. The systems and methods include adsorbing waste into a metal-organic framework (MOF), and applying pressure to the MOF material's framework to crystallize or make amorphous the MOF material thereby changing the MOF's pore structure and sorption characteristics without collapsing the MOF framework.

Abstract: Systems and methods for obtaining and displaying a collimated X-ray image are described. The methods can include providing an X-ray device having an X-ray source, a square or rectangular X-ray detector, and a collimator. The collimator can be sized and shaped to collimate an X-ray beam from the X-ray source that exposes a receptor region on the detector. The collimator can allow the X-ray image received by the X-ray detector to have any suitable shape that allows a relatively large view of the image to be displayed and rotated on the display device without changing the shape or size of the image as it rotated. In some instances, the collimator provides the image with superellipse shapes or cornerless shapes having four substantially straight edges with a 90 degree corner missing between at least two edges that run substantially perpendicular to each other. Other embodiments are described.

Abstract: An electrical bushing for use in a housing of an implantable medical device is proposed. The electrical bushing includes at least one electrically insulating base body and at least one electrical conducting element. The conducting element establishes, through the base body, at least one electrically conductive connection between an internal space of the housing and an external space. The conducting element is hermetically sealed with respect to the base body, at least in part. The at least one conducting element includes at least one cermet. The cermet of the conducting element and the base body include one or more of the same ceramic compound.

Abstract: A composite conductive material includes at least graphene-like exfoliated from a graphite-based graphite carbon material and a conductive material dispersed in a base material. The graphite-based carbon material has a rhombohedral graphite layer (3R) and a hexagonal graphite layer (2H), wherein a Rate (3R) of the rhombohedral graphite layer (3R) and the hexagonal graphite layer (2H), based on an X-ray diffraction method, which is defined by following Equation 1 is 31% or more: Rate(3R)=P3/(P3+P4)×100??(Equation 1) wherein P3 is a peak intensity of a (101) plane of the rhombohedral graphite layer (3R) based on the X-ray diffraction method, and P4 is a peak intensity of a (101) plane of the hexagonal graphite layer (2H) based on the X-ray diffraction method.

Abstract: Batteries with particularly high energy capacity and low internal impedance have been described herein. The batteries can exhibit extraordinary long cycling with acceptable low amounts of fade. Pouch batteries using high specific capacity lithium rich metal oxide as positive electrode material combined with graphitic carbon anode can reach an energy density of at least about 180 Wh/kg at a rate of C/3 from 4.35V to 2V at room temperature while having a room temperature areas specific DC resistance of no more than about 75 ohms-cm2 at 20% SOC based on a full charge to 4.35V. High specific capacity lithium rich metal oxide with specific stoichiometry ranges used in these batteries are disclosed.

Abstract: The invention provides a transparent conducting film which comprises a compound of formula (I): Zn1-x[M]xO1-y[X]y(I) wherein: x is greater than 0 and less than or equal to 0.25; y is from 0 to 0.1; [X] is at least one dopant element which is a halogen; and [M] is: (a) a dopant element which is selected from: a group 14 element other than carbon; a lanthanide element which has an oxidation state of +4; and a transition metal which has an oxidation state of +4 and which is other than Ti or Zr; or (b) a combination of two or more different dopant elements, at least one of which is selected from: a group 14 element other than carbon; a lanthanide element which has an oxidation state of +4; and a transition metal which has an oxidation state of +4 and which is other than Ti or Zr. The invention further provides coatings comprising the films of the invention, processes for producing such films and coatings, and various uses of the films and coatings.

Abstract: A polymer film, polymer gel, and polymer foam each contain an electrically conductive polymer and an ionic liquid and are each useful as a component of an electronic device.

Abstract: A composition in accordance with the present invention contains a nano-carbon material, such as a carbon nanotube, and a polyether-based polymer containing oxirane monomer units at least part of which are oxirane monomer units each having a cationic group.

Abstract: According to the invention there is provided a Structural integrated wiring loom comprising at least one conductor comprising at least one first conductive fiber ply, wherein said at least one first conductive fiber ply comprises at least two electrical connectors, a separator structure comprising at least one first non-conductive fiber ply, and at least one second non-conductive fiber ply, said separator structure encapsulating said at least one conductor, a screen structure which encapsulates said separator structure, said screen structure comprising at least one second conductive fiber ply and at least one third conductive fiber ply, wherein said device is encapsulated a binder matrix. The device may be used to replace structural panels on a vehicle vessel or craft, to transfer electrical power or RF signals, data transmission around a composite structure.

Abstract: In embodiments of the invention, a superconductor lead is configured to have less ohmic heating by its own current and less heat conduction from room temperature to cryogenic temperature, where a cryogenic apparatus is located. The superconducting lead with no ohmic resistance and low thermal conductivity disclosed herein maximizes current capacity by placing superconductors in parallel, each having equal current. Thus, the resistances are controlled to provide uniform current distribution through each superconductor of the high temperature superconducting (HTS) lead.

Abstract: A resin impregnated paper (RIP) condenser core configured for being positioned around an electrical conductor. The condenser core includes a winding tube forming a longitudinal through hole through the condenser core, configured for allowing an electrical conductor to be inserted there through; an electrically insulating RIP body wound onto and around the winding tube; and at least one electrically conducting foil coaxially encircling the winding tube and being surrounded by the RIP body insulating each of the at least one foil from any other of the at least one foil. The winding tube is of an electrically insulating material which has been chosen from a group consisting of materials having a volumetric thermal expansion coefficient within the range of 50% to 200% of the volumetric thermal expansion coefficient of the RIP body.

Abstract: A chip resistor having terminal electrodes is provided. In the chip resistor, a first protector layer has a size different from that of a first resistor layer. Thus, two ends of the first resistor layer are exposed to form new current conduction path. Original current conduction path having the same size of the protective layer and the resistor layer is thus replaced. Hence, resistance variation of the chip resistor is solved; yield of the chip resistor is increased; and, the material cost of the front terminal electrode is greatly reduced.

Abstract: Surface-mountable devices include a conductive polymer layer between first and second electrodes, on which are disposed first and second insulation layers, respectively, with first and second planar terminals on the second insulation layer. A first cross-conductor connects the second electrode to the first terminal, and is separated from the first electrode by a portion of the first insulation layer. A second cross-conductor connects the first electrode to the second terminal, and is separated from the second electrode by a portion of the second insulation layer. At least one cross-conductor may include a beveled portion through the first insulation layer. Alternatively, at least one cross-conductor may contact an anchor pad on the first insulation layer, the anchor pad having a small area relative to the areas of the terminals. Enhanced adhesion between the cross-conductor(s) and the first insulation layer is provided, while allowing thermal expansion without excessive stress.

Abstract: A ferrite magnet with salt includes 40 to 99.9 weight % of ferrite and 0.1 to 60 weight % of salt, wherein the salt has a melting point lower than a synthetic temperature of the ferrite, and the salt is melted to form a matrix between the ferrite particles, and a manufacturing thereof. The ferrite magnet with salt has advantages in terms of process conditions due to fast synthesis reaction at low temperatures compared to typical magnets, easily obtaining nano-sized particles having high crystallinity, preventing cohesion between particles and particle growth by molten salt, allowing sintering at temperatures lower than typical during the molding and sintering processes for producing a ferrite magnet with salt due to synthesized ferrite magnetic powder with salt thus preventing the deterioration of magnetic characteristics due to particle growth, and allowing alignment in the direction of magnetization easy axis to obtain higher magnetic characteristics.