Abstract: The semiconductor element has an electrode including: a Ni-inclusion metal layer containing nickel formed on a side of at least one surface of the semiconductor-element constituting part; a Ni-barrier metal layer formed outwardly on a side of the Ni-inclusion metal layer opposite to the side toward the semiconductor-element constituting part; and a surface metal layer outwardly formed on a side of the Ni-barrier metal layer opposite to the side toward the semiconductor-element constituting part, to be connected to the metal nanoparticles sintered layer; wherein the Ni-barrier metal layer contains a metal for suppressing diffusion of nickel toward the surface metal layer.

Abstract: An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings related to driving of the piezoelectric element formed thereon, and a sealing plate bonded thereto, the electrode wirings are made of wiring metal containing gold (Au) on the drive substrate through an adhesion layer which is a base layer, and has a removed portion in which a portion of the wiring metal in a region containing a part bonded to a bonding resin is removed and the adhesion layer is exposed.

Abstract: A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved.

Abstract: A device includes a metal pad, a passivation layer overlapping edge portions of the metal pad, and a first polymer layer over the passivation layer. A Post-Passivation-Interconnect (PPI) has a level portion overlying the first polymer layer, and a plug portion that has a top connected to the level portion. The plug portion extends into the first polymer layer. A bottom surface of the plug portion is in contact with a dielectric material. A second polymer layer is overlying the first polymer layer.

Abstract: A semiconductor device includes a semiconductor layer, an electrode layer arranged on the semiconductor layer, a crack starting point layer arranged above the semiconductor layer, and a solder layer being in contact with the electrode layer and the crack starting point layer. A joining force between the solder layer and the crack starting point layer is smaller than a joining force between the solder layer and the electrode layer.

Abstract: An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires.

Abstract: A bonding apparatus of substrate manufacturing equipment includes an upper stage, a lower stage facing the upper stage and which is configure and dedicated to support a processed substrate on which semiconductor chips are stacked (set), and an elevating mechanism for raising the lower stage relative to the upper stage to provide pressure for pressing the substrate and chips towards each other.

Abstract: Embodiments of the present disclosure include a semiconductor device, a package, and methods of forming a semiconductor device and a package. An embodiment is a method including placing a plurality of dies over a passivation layer, the plurality of dies comprising at least one active device, molding the plurality of dies with a first molding material, and forming a plurality of through-package vias (TPVs) in the first molding material, first surfaces of the plurality of TPVs being substantially coplanar with a backside surfaces of the plurality of dies. The method further includes patterning the passivation layer to expose a portion of the first surfaces of the plurality of TPVs, and bonding a plurality of top packages to the first surfaces of the plurality of TPVs.

Abstract: A microelectronic package includes a first microelectronic element comprising logic circuitry which is flip-chip mounted to a substrate, the substrate having terminals for connection with a circuit panel or other external component. A second microelectronic element overlies a rear surface of the first microelectronic element and has contacts electrically coupled with the substrate through electrically conductive interconnects extending through a region of the first microelectronic element. A heat spreader is thermally coupled with the rear surface of the substrate, either directly or through an additional element overlying the rear surface. Additional contacts of the second microelectronic element may be coupled with contacts of the substrate through electrically conductive structure disposed beyond an edge surface of the first microelectronic element.

Abstract: A semiconductor device package includes a substrate, electrical components disposed on the substrate, and a conductive frame disposed on the substrate. The conductive frame includes a top portion including at least one opening, a rim connected to the top portion and surrounding the electrical components, and a compartment extending from the top portion of the conductive frame and separating one or more of the electrical components from others of the electrical components. The semiconductor device package further includes an electromagnetic interference shield in contact with the top portion and the rim of the conductive frame.

Abstract: A chip stack structure using conductive film bridge adhesive technology comprises a substrate, a first chip, at least one bridge element, a conductive film, and a second chip. The first chip is electrically connected to a first electrode of the substrate. The at least one bridge element has a first bridge surface and a second bridge surface at two ends, and the first bridge surface and the second bridge surface are electrically connected to the first chip and a second electrode of the substrate, respectively. The conductive film is electrically connected to the first bridge surface of the at least one bridge element. The second chip is stacked and electrically connected to the conductive film. Thus, the structure of the present invention not only facilitates the ease of stacking the chips but also increases the effectiveness of the chips heat dissipation and ability of withstanding electrical current.

Abstract: A semiconductor package that includes a package substrate, a lower semiconductor chip mounted on the package substrate, and an upper semiconductor chip stacked on the lower semiconductor chip in a cascade shape is provided. An active surface of the lower semiconductor chip is facing an active surface of the upper semiconductor chip.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

Abstract: A microelectronic package having a substrate, a microelectronic element, e.g., a chip, and terminals can have conductive elements electrically connected with element contacts of the chip and contacts of the substrate. Conductive elements can be electrically insulated from one another for simultaneously carrying different electric potentials. An encapsulant can overlie the first surface of the substrate and at least a portion of a face of the microelectronic element remote from the substrate, and may have a major surface above the microelectronic element. A plurality of package contacts can overlie a face of the microelectronic element remote from the substrate. The package contacts, e.g., conductive masses, substantially rigid posts, can be electrically interconnected with terminals of the substrate, such as through the conductive elements. The package contacts can have top surfaces at least partially exposed at the major surface of the encapsulant.

Abstract: A compact LED module and a method of manufacturing such an LED module are provided. The LED module includes a first-pole first lead, a first-pole second lead, a first-pole third lead, a second-pole first lead, a second-pole second lead, a second-pole third lead, a first LED chip, a second LED chip, a third LED chip, and a housing. A distal end of the first-pole first lead is offset toward a second-pole side in a first direction with respect to both a distal end of the second-pole second lead and a distal end of the second-pole third lead.

Abstract: A light-emitting diode module includes a carrier and a plurality of optoelectronic semiconductor chips mounted on a carrier top and configured to generate primary radiation. The semiconductor chips are arranged in part at a first distance and in part at a second, greater distance from one another. Between the adjacent semiconductor chips arranged at the first distance from one another there is located a radiation-transmissive first filling for optical coupling. Between the adjacent semiconductor chips arranged at the second distance from one another there is located a radiation-opaque second filling for optical isolation.

Abstract: A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.

Abstract: Methods for integrating MOL TSVs in 3D SoC devices including face-to-face bonded IC chips. Embodiments include providing a device layer in each of IC chips on upper surfaces of top and bottom silicon wafers; forming, subsequent to the device layer, through-silicon vias (TSVs) extending through an upper surface of the device layer in each of the IC chips and into the bottom Si wafer; forming, subsequent to the TSVs, a dielectric layer on the upper surface of the device layer in each of the IC chips of the top and bottom Si wafers; forming a back-end-of-line metal layer in the dielectric layer of each of the IC chips of the top and bottom Si wafers; face-to-face bonding of opposing IC chips of the top and bottom Si wafers; and dicing adjacent bonded IC chips through vertically aligned dicing lanes in the top and bottom Si wafers.

Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.

Abstract: Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined.

Abstract: An apparatus configured to control a heat flow is provided. The apparatus may include a semiconductor device region formed in a matrix; a heat rectifier region formed adjacent to the semiconductor device region; and a heat flow blocker formed in at least one region contacting the semiconductor device region and the heat rectifier region.

Abstract: According to the present invention, a switching element includes a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, a first resistor portion formed on the substrate, the first resistor portion connecting the first gate pad and the second gate pad to each other, and a cell region formed on the substrate and connected to the first gate pad. Thus, measurement of the gate resistance value and selection from gate resistances of the switching element can be performed after the completion of the gate-resistor-incorporating-type switching element.

Abstract: A three terminal high voltage Darlington bipolar transistor power switching device includes two high voltage bipolar transistors, with collectors connected together serving as the collector terminal. The base of the first high voltage bipolar transistor serves as the base terminal. The emitter of the first high voltage bipolar transistor connects to the base of the second high voltage bipolar transistor (inner base), and the emitter of the second high voltage bipolar transistor serves as the emitter terminal. A diode has its anode connected to the inner base (emitter of the first high voltage bipolar transistor, or base of the second high voltage bipolar transistor), and its cathode connected to the base terminal. Similarly, a three terminal hybrid MOSFET/bipolar high voltage switching device can be formed by replacing the first high voltage bipolar transistor of the previous switching device by a high voltage MOSFET.

Abstract: A Reverse-conducting semiconductor device which comprises a freewheeling diode and an insulated gate bipolar transistor on a common wafer, part of which wafer forms a base layer of a first conductivity type with a first doping concentration and a base layer thickness. The insulated gate bipolar transistor comprises a collector side and an emitter side opposite the collector side of the wafer. A cathode layer of a first conductivity type with at least one first region and a anode layer of a second conductivity type with at least one second and pilot region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The Reverse-conducting-IGBT of the present application satisfies a number of specific geometrical rules.

Abstract: In some embodiments, a semiconductor device includes a first transistor and a second transistor. The first transistor includes a first source region in a first bulk region having a first concentration, and a first gate. The second transistor includes a second source region in a second bulk region having a second concentration higher than the first concentration. The second source region is connected with the first source region and the first gate.

Abstract: A method for fabricating a semiconductor device comprises forming active regions on a semiconductor substrate, forming a gate stack over the active regions and regions adjacent to the active regions, depositing a layer of conductive material over the active regions and the substrate, patterning a first mask over the conductive material, etching to remove exposed portions of the conductive material and form conductive contacts, patterning a second mask over portions of the gate stacks and conductive contacts, and etching to remove exposed portions of the gate stack.

Abstract: A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

Abstract: A semiconductor structure is provided, which includes a first high-voltage MOS device region having a first well and a first light-doping region in a part of the first well, wherein the conductive type of the first well and the conductive type of the first light-doping region are opposite. The first high-voltage MOS device region also includes a first gate stack on a part of the first well and a part of the first light-doping region, and first heavy-doping regions in the first well and the first light-doping region at two sides of the gate stack, wherein the conductive type of the first heavy-doping region and the conductive type of the first well are the same. The first light-doping region between the first well and the first heavy-doping regions is a channel region of the first high-voltage MOS device region.

Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.

Abstract: Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor. The method also includes etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process.

Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.

Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region. The semiconductor arrangement includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where an electrode unit of the first electrode has a first portion and a second portion, and where the second portion is above the first portion and is wider than the first portion.

Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor includes a first source terminal formed of a material and connected to a first source, a first drain terminal formed of the material and connected to a first drain, a first gate overlapping a portion of the substrate that is between the first source and the first drain, and a first dielectric layer between the first gate and the substrate. The second transistor includes a control gate formed of the material and overlapping a part of the substrate that is positioned between a second source and a second drain, a second dielectric layer between the control gate and the substrate, a floating gate extending through the second dielectric layer to contact a doped region in the substrate, and an insulating member positioned between the control gate and the floating gate.

Abstract: A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for providing a 3D memory array apparatus. In one embodiment, the apparatus may comprise a substantially hexagonal arrangement having seven pillars disposed in a die in a repeating pattern. The arrangement may include first and second pillars disposed at a pillar pitch from each other in a first row; third, fourth, and fifth pillars disposed at the pillar pitch from each other in a second row; and sixth and seventh pillar disposed at the pillar pitch from each other in a third row and shifted relative to the first and second pillars respectively by a quarter of the pillar pitch in a direction that is substantially orthogonal to bitlines disposed in the die. Each pillar in the arrangement may be electrically coupled with a different bitline. Other embodiments may be described and/or claimed.

Abstract: A method of forming a three-dimensional memory device includes forming a stack of alternating first and second material layers over a substrate, forming a memory opening through the stack, forming a memory film and a semiconductor channel in the memory opening, and forming backside recesses by removing the second material layers selective to the first material layers and the memory film, where an outer sidewall of the memory film is physically exposed within each backside recess. The method also includes forming at least one set of surfaces selected from silicon deposition inhibiting surfaces on the first material layers and silicon deposition promoting surfaces over the memory film in the back side recesses, selectively growing a silicon-containing semiconductor portion laterally within each backside recess, forming at least one blocking dielectric within the backside recesses, and forming conductive material layers by depositing a conductive material within the backside recesses.

Abstract: A semiconductor device may include gate structures spaced apart above a top surface of a substrate. The gate structures may include a horizontal electrode extending in a first direction parallel with the top surface of a substrate. An isolation insulating layer may be disposed between the gate structures. A plurality of cell pillars may penetrate the horizontal electrode and connect to the substrate. The plurality of cell pillars may include a minimum spacing defined by a shortest distance between any two of the plurality of cell pillars. The thickness of the horizontal electrode may be greater than the minimum spacing of the cell pillars.

Abstract: Methods of selectively etching tungsten from the surface of a patterned substrate are described. The etch electrically separates vertically arranged tungsten slabs from one another as needed, for example, in the manufacture of vertical flash memory devices. The tungsten etch may selectively remove tungsten relative to films such as silicon, polysilicon, silicon oxide, aluminum oxide, titanium nitride and silicon nitride. The methods include exposing electrically-shorted tungsten slabs to remotely-excited fluorine formed in a capacitively-excited chamber plasma region. The methods then include exposing the tungsten slabs to remotely-excited fluorine formed in an inductively-excited remote plasma system. A low electron temperature is maintained in the substrate processing region during each operation to achieve high etch selectivity.

Abstract: Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from a material, to define a profile for the memory cell. The method also includes partially filling the key-hole shaped column with a first number of materials. The method further includes filling the remaining portion of the key-hole shaped column with a second number of materials.

Abstract: Provided is a fabricating method of a semiconductor device, including the following. Fin structures are formed on a substrate, and the adjacent fin structures have an opening therebetween. A conductive material layer is formed to cover the fin structures and fill the opening. The conductive material layer and the fin structures are patterned to form a mesh structure. The mesh structure includes first strips extending in a first direction and second strips extending in a second direction. The first strips and the second strips intersect each other, and the mesh structure has holes. The first strips are located on the substrate at positions corresponding to the fin structures. The second strips are located on the substrate, and the conductive material layer in the second strips spans the fin structures. The hole is formed in the opening and surrounded by the first strips and the second strips.

Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

Abstract: A three-dimensional nonvolatile memory device includes a substrate defined with a slimming region, first and second pass regions on both sides of the slimming region, and a cell region adjacent to the slimming region with the first pass region interposed therebetween; a word line stack including a plurality of word lines stacked over the cell region, the first pass region, and the slimming region of the substrate; first wiring lines extending from the slimming region to the first pass region and electrically coupling some word lines with pass transistors formed in the first pass region of the substrate; and second wiring lines extending from the slimming region to the second pass region and electrically coupling remaining word lines, other than the some word lines, with pass transistors formed in the second pass region of the substrate.

Abstract: A method for fabricating a semiconductor device includes receiving a finned substrate comprising an isolation layer with a plurality of semiconductor fins formed thereon, forming a gate structure over a fin that comprises a gate and a seed layer disposed below the gate and immediately adjacent to the fin, and epitaxially growing a gate extender from the seed layer that laterally extends over a source or drain region of the fin. In one embodiment, a semiconductor device includes a finned substrate comprising an isolation layer with a plurality of semiconductor fins formed thereon, a gate structure formed over a fin of the plurality of fins, the gate structure comprising a gate and a seed layer disposed below the gate and immediately adjacent to the fin, and a gate extender epitaxially grown from the seed layer that laterally extends over a source or drain region of the fin.

Abstract: The present invention discloses an array substrate, a method of manufacturing the array substrate and a display device. Since the respective surfaces of the sources, the drains and the data lines are clad by the respective insulating films, in formation of the patterns of the pixel electrodes above the insulating films by using a patterning process, the insulating films can prevent the sources and the data lines provided under them from being corroded by an etching agent when an etching process is performed to form the patterns of the pixel electrodes, so as to avoid an influence on display quality of a display panel.

Abstract: A thin film transistor substrate includes a semiconductor channel layer made of an oxide semiconductor, protective insulating layers that cover the semiconductor channel layer, a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode. The second source electrode is located on the first source electrode and connected with the semiconductor channel layer through a first contact hole. The second drain electrode is located on the first drain electrode and connected with the semiconductor channel layer through a second contact hole.

Abstract: An array substrate, a display device comprising the array substrate and a method of manufacturing the array substrate are provided.

Abstract: A pixel electrode of an array substrate is connected with a drain electrode of a TFT via a first aperture formed on a second interlayer insulating film, a second aperture that includes a bottom portion of the first aperture and is formed on a common electrode, a third aperture that includes at least a part of the bottom portion of the first aperture, is included in a second aperture and is formed on a third interlayer insulating film, and a fourth aperture that is formed on the first interlayer insulating film in a region where the third aperture overlaps with the bottom portion of the first aperture.

Abstract: The invention discloses an array substrate, a display panel and methods of manufacturing the same, and a display device. The array substrate comprises: a pixel region and a wiring region located outside the wiring region; a gate line and a data line each arranged within both the pixel and wiring regions; a passivation layer arranged to cover the gate and data lines and provided therein with trenches respectively exposing and being wider than the gate and data lines within the wiring region; first and second signal line partially arranged within the trenches respectively and contacting exposed portions of the gate and data lines to transmit signals to the gate and gate lines respectively, the first and second signal line each having widths equal to those of the trenches respectively. With the invention, good electrical connections between the signal line and the gate and data lines are enabled.