Abstract: The present invention relates to a method of controlling an ion implanter having a plasma power supply AP and a substrate power supply, the substrate power supply comprising: an electricity generator; a first switch SW1 connected between the generator and the output terminal of the substrate power supply; and a second switch SW2 connected between the output terminal and a neutralization terminal; the method including an implantation stage A-D and a neutralization stage E-H. The method also includes a relaxation stage C-F overlapping the implantation stage and the neutralization stage, during which relaxation stage the plasma power supply is inactivated. Furthermore, the neutralization stage includes a preliminary step E-F for closing the second switch, this preliminary step being followed by a cancellation step F-G for activating the plasma power supply AP.

Abstract: A charged particle beam writing apparatus includes a reading unit to read an identifier from a substrate where an absorber film which absorbs extreme ultraviolet light is formed and the identifier which can be optically read is formed, a storage unit to store defect position information indicating a position of a defect on the substrate based on reference marks, defect size information indicating a size of the defect, which are corresponding to the identifier, and pattern data for writing, an examination unit to input partial pattern data corresponding to a region including at least the defect in the pattern data, the defect position information based on reference marks, and the defect size information, and to examine whether a pattern layout is formed such that the defect is located in a region where the absorber film remains after patterning, and a writing unit to write a pattern on the substrate.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: The present invention discloses an inductively coupled coil and an inductively coupled plasma device using the same. The inductively coupled coil comprises an internal coil and an exterior coil which are respective from each other and coaxially arranged, internal coil comprising a plurality of internal respective branches having the same configurations which are nested together, the plurality of internal respective branches being arranged symmetrically with respect to an axis of the inductively coupled coil; the external coil comprising a plurality of external respective branches having the same configurations which are nested together, the plurality of external respective branches being arranged symmetrically with respect to the axis of the inductively coupled coil. The inductively coupled coil is located on the reaction chamber of the inductively coupled plasma device and is connected to a RF source.

Abstract: An antenna for plasma generation radiates a microwave transmitted through a coaxial waveguide into a processing chamber and propagates the microwave on a metal surface of the processing chamber to convert gas into surface wave plasma. The antenna includes a gas flow path for passing the gas through the antenna, a plurality of gas holes that communicate with the gas flow path and introduce the gas into the processing chamber, and a plurality of slots that are separated from the gas flow path and penetrate through the gas flow path. The slots pass the microwave transmitted through the coaxial waveguide and a slow-wave plate to the processing chamber. A first space between portions of adjacent slots penetrating through the gas flow path is arranged to be wider than a second space between portions of the adjacent slots opening out to a plasma generation space of the processing chamber.

Abstract: Embodiments disclosed herein include an abatement system for abating compounds produced in semiconductor processes. The abatement system includes a plasma source that has a first plate and a second plate parallel to the first plate. An electrode is disposed between the first and second plates and an outer wall is disposed between the first and second plates surrounding the electrode. The plasma source has a first plurality of magnets disposed on the first plate and a second plurality of magnets disposed on the second plate. The magnetic field created by the first and second plurality of magnets is substantially perpendicular to the electric field created between the electrode and the outer wall. In this configuration, a dense plasma is created.

Abstract: Embodiments of the present invention generally include an apparatus for plasma cleaning and a method for plasma cleaning. The apparatus can include a lid body having a first surface for facing a pedestal during cleaning and a second surface opposite the first surface and substantially parallel to the first surface, the second surface having a first indentation sized to receive a magnet assembly, one or more handles coupled to the second surface of the lid body, and the magnet assembly resting in the first indentation. The method can include removing a sputtering target from the processing chamber, sealing the processing chamber, introducing a gas into the processing chamber, applying an RF bias to a pedestal within the processing chamber, maintaining the pedestal at a substantially constant temperature, and removing material from the pedestal to clean the pedestal.

Abstract: An ion mobility separator 4 and a method of separating ions according to their ion mobility are disclosed. An RF ion guide is provided having a plurality of electrodes that are arranged to form an ion guiding path that extends in a closed loop. RF voltages are supplied to at least some of the electrodes in order to confine ions within said ion guiding path. A DC voltage gradient is maintained along at least a portion of a longitudinal axis of the ion guide, wherein the voltage gradient urges ions to undergo one or more cycles around the ion guide and thus causes the ions to separate according to their ion mobility as the ions pass along the ion guide. The closed loop ion guide enables the resolution of the ion mobility separator to be increased without necessitating a large device, since the drift length through the device can be increased by causing the ions to undergo multiple cycles around the device.

Abstract: A method of analyzing ions is disclosed comprising: (i) separating ions according to a physico-chemical property in a separator; (ii) transmitting ions which emerge from the separator through a transfer device with a first transit time t1, energizing a pusher electrode or orthogonal acceleration electrode and obtaining first data; (iii) transmitting ions which subsequently emerge from the separator through the transfer device with a second greater transit time t2, energizing the pusher electrode or orthogonal acceleration electrode and obtaining second data; and (iv) repeating steps (ii) and (iii) one or more times. The pusher electrode or orthogonal acceleration electrode is energized with a period t3, wherein t2-t1 is arranged to equal t3/2. The first and second data are combined to form a composite data set.

Abstract: Methods and systems for delivering a liquid sample to an ion source are provided herein. In various aspects, the methods and systems can improve the stability of a flow of liquid sample delivered to an ion source. In accordance with various aspects, the methods and systems can remove bubbles (e.g., cavitation bubbles or otherwise) present in the liquid sample prior to its injection into an ionization chamber.

Abstract: A method for producing multiply charged ions is provided. In the method, a laser is used to ablate a sample comprising a matrix and an analyte. The sample is in the liquid form when it is ablated and the ions produced are passed through a heated conduit. The multiply charged ions produced may be used in mass spectrometry to measure the mass of the analyte.

Abstract: An ionizing system includes a channel having an inlet disposed in a first pressure region and an outlet disposed in a second pressure region, a pressure of the first pressure region being greater than a pressure of the second pressure region. A heater is coupled to the channel and configured to heat the channel. A device is configured to introduce an analyte into the channel where the analyte is ionized.

Abstract: An ion mobility separator or spectrometer is disclosed comprising an inner cylinder and an outer cylinder defining an annular volume through which ions are transmitted. Spiral electrodes a-f are arranged on a surface of the inner cylinder and/or on a surface of the outer cylinder. A first device is arranged and adapted to maintain a DC electric field and/or a pseudo-potential force which acts to urge ions from a first end of the ion mobility separator or spectrometer to a second end of the ion mobility separator or spectrometer. A second device is arranged and adapted to apply transient DC voltages to the one or more spiral electrodes in order to urge ions towards the first end of the ion mobility separator or spectrometer. The net effect is to extend the effective path length of the ion mobility separator.

Abstract: A method of mass spectrometry is disclosed comprising providing a flight region for ions to travel through and a detector or fragmentation device. A potential profile is maintained along the flight region such that ions travel towards the detector or fragmentation device. The potential at which a first length of the flight region is maintained is then changed from a first potential to a second potential while at least some ions are travelling within the first length of flight region. The changed potential provides a first potential difference at an exit of the length of flight region, through which the ions are accelerated as they leave the length of flight region. This increases the kinetic energy of the ions prior to them reaching the detector or fragmentation cell.

Abstract: The geometry of a High Intensity Discharge (HID) arc tube is controlled to improve lamp color control and temperature distribution. In some embodiments, conical sections located at the transition zones near the electrodes are included to provide funnel-like body-leg interface portions. The body-leg interface portions are shaped so as to advantageously control the temperature distribution along the internal surface of the discharge chamber wall so that it monotonically decreases resulting in a stable local cold spot location at the body-leg interface.

Abstract: Embodiments of systems, devices, and methods to minimize warping of ultrathin IC packaged products are generally described herein. In some embodiments, an apparatus includes an IC mounted on a package substrate, and a capacitive stiffener subassembly mounted on the package substrate. The capacitive stiffener subassembly includes a plurality of capacitive elements electrically connected to contacts of the IC.

Abstract: A method of decreasing fin bending, includes providing a substrate including a plurality of fins, wherein a plurality of trenches are defined by the fins, the trenches include a first trench and a second trench, and the second trench is wider than the first trench. Later, a flowable chemical vapor deposition process is performed to form a silicon oxide layer covering the fins, filling up the first trench and partially filling in the second trench. After that, the silicon oxide layer is solidified by a UV curing process. Finally, after the UV curing process, the silicon oxide layer is densified by a steam anneal process.

Abstract: A process for depositing aluminum nitride is disclosed. The process comprises providing a plurality of semiconductor substrates in a batch process chamber and depositing an aluminum nitride layer on the substrates by performing a plurality of deposition cycles without exposing the substrates to plasma during the deposition cycles. Each deposition cycle comprises flowing an aluminum precursor pulse into the batch process chamber, removing the aluminum precursor from the batch process chamber, and removing the nitrogen precursor from the batch process chamber after flowing the nitrogen precursor and before flowing another pulse of the aluminum precursor. The process chamber may be a hot wall process chamber and the deposition may occur at a deposition pressure of less than 1 Torr.

Abstract: A method of manufacturing a semiconductor device includes: pre-treating a surface of a substrate by supplying an oxygen-containing gas and a hydrogen-containing gas to the substrate heated in a process chamber under a pressure less than atmospheric pressure; and forming a film on the pre-treated substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor gas to the substrate in the process chamber; and supplying a reaction gas to the substrate in the process chamber.

Abstract: A metal oxide film forming method includes: repeating a cycle a first predetermined number of times, the cycle including supplying a gas containing an organic metal precursor into a processing chamber where an object to be processed is accommodated, and supplying oxygen gas into the processing chamber after the gas containing the organic metal precursor is supplied into the processing chamber; and supplying ozone gas into the processing chamber, wherein repeating the cycle and supplying the ozone gas are repeated a second predetermined number of times, so that a metal oxide film is formed on a surface of the object to be processed.

Abstract: Disclosed herein are methods of forming SiC/SiCN film layers on surfaces of semiconductor substrates. The methods may include introducing a silicon-containing film-precursor and an organometallic ligand transfer reagent into a processing chamber, adsorbing the silicon-containing film-precursor, the organometallic ligand transfer reagent, or both onto a surface of a semiconductor substrate under conditions whereby either or both form an adsorption-limited layer, and reacting the silicon-containing film-precursor with the organometallic ligand transfer reagent, after either or both have formed the adsorption-limited layer. The reaction results in the forming of the film layer. In some embodiments, a byproduct is also formed which contains substantially all of the metal of the organometallic ligand transfer reagent, and the methods may further include removing the byproduct from the processing chamber. Also disclosed herein are semiconductor processing apparatuses for forming SiC/SiCN film layers.

Abstract: A manufacturing method for a semiconductor device, including: loading a wafer into a reaction chamber; placing the wafer on a push-up shaft moved up; preheating the wafer under controlling an in-plane temperature distribution of the wafer to be a recess state under a state of placing the wafer on the push-up shaft moved up; lowering the push-up shaft with the wafer kept in the recess state to hold the wafer on a wafer holding member; heating the wafer to a predetermined temperature; rotating the wafer; and supplying a process gas onto the wafer.

Abstract: There are provided a processing method of a substrate in which in forming a trench on the substrate by etching, a side wall surrounding the trench is surely protected, and a manufacturing method of a liquid ejection head. The methods include: repeating sequentially a plurality of cycles of a trench forming step of forming the trench on a printing element substrate, a first protection layer forming step of forming a passivation layer, and a first protection layer removing step of removing a portion at which the trench is excavated in the passivation layer. A second protection layer forming step and a second protection layer removing step are performed between the trench forming step through the first protection layer removing step repeated in a plurality of cycles and the trench forming step through the first protection layer removing step repeated next.

Abstract: The invention provides an oxide semiconductor layer that has less cracks and is excellent in electrical property and stability, as well as a semiconductor element and an electronic device each including the oxide semiconductor layer. The invention provides an exemplary method of producing an oxide semiconductor layer, and the method includes the precursor layer forming step of forming, on or above a substrate, a layered oxide semiconductor precursor including a compound of metal to be oxidized into an oxide semiconductor dispersed in a solution including a binder made of aliphatic polycarbonate, and the annealing step of heating the precursor layer at a first temperature achieving decomposition of 90 wt % or more of the binder, and then annealing the precursor layer at a temperature equal to or higher than a second temperature (denoted by X) that is higher than the first temperature, achieves bonding between the metal and oxygen, and has an exothermic peak value in differential thermal analysis (DTA).

Abstract: A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The method includes depositing silver-selenide using a sputter deposition process at a pressure of about 0.3 mTorr to about 10 mTorr. In accordance with one aspect of the invention, an RF sputter deposition process may be used preferably at pressures of about 2 mTorr to about 3 mTorr. In accordance with another aspect of the invention, a pulse DC sputter deposition process may be used preferably at pressures of about 4 mTorr to about 5 mTorr.

Abstract: A substrate processing method is performed to improve surface roughness of a pattern mask formed on a substrate by being exposed and developed. The method includes supplying a first solvent in a gaseous state to a surface of the substrate to dissolve the pattern mask, and supplying a second solvent to the surface of the substrate, which is supplied with the first solvent, to dissolve the pattern mask, wherein a permeability of the second solvent is lower than a permeability of the first solvent.

Abstract: A method for DSA fin patterning includes forming a BCP layer over a lithographic stack, the BCP layer having first and second blocks, the lithographic stack disposed over a hard mask and substrate, and the hard mask including first and second dielectric layers; removing the first block to define a fin pattern in the BCP layer with the second block; etching the fin pattern into the first dielectric layer; filling the fin pattern with a tone inversion material; etching back the tone inversion material that overfills the fin pattern; removing the first dielectric layer selectively to define an inverted fin pattern from the tone inversion material; etching the inverted fin pattern into the second dielectric layer of the hard mask; removing the tone inversion material; and transferring the inverted fin pattern of the second dielectric layer into the substrate to define fins.

Abstract: Methods and apparatus for processing substrates and controlling the heating and cooling of substrates are described. A radiation source providing radiation in a first range of wavelengths heats the substrate within a predetermined temperature range, the substrate being absorptive of radiation in a second range of wavelengths within the first range of wavelengths and within the predetermined temperature rang. A filter prevents at least a portion of radiation within the second wavelength range from reaching the substrate.

Abstract: A supply source for delivery of a CO-containing dopant gas composition is provided. The composition includes a controlled amount of a diluent gas mixture such as xenon and hydrogen, which are each provided at controlled volumetric ratios to ensure optimal carbon ion implantation performance. The composition can be packaged as a dopant gas kit consisting of a CO-containing supply source and a diluent mixture supply source. Alternatively, the composition can be pre-mixed and introduced from a single source that can be actuated in response to a sub-atmospheric condition achieved along the discharge flow path to allow a controlled flow of the dopant mixture from the interior volume of the device into an ion source apparatus.

Abstract: A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench.

Abstract: Co-fabricating non-planar (i.e., three-dimensional) semiconductor devices with different threshold voltages includes providing a starting semiconductor structure, the structure including a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, at least two gate structures encompassing a portion of the raised structures, each gate structure including a gate opening lined with dielectric material and partially filled with work function material, a portion of the work function material being recessed. The co-fabrication further includes creating at least one conformal barrier layer in one or more and less than all of the gate openings, filling the gate openings with conductive material, and modifying the work function of at least one and less than all of the filled gate structures.

Abstract: A number of variations may include a method that may include depositing a first layer on a first semiconductor epi layer (epitaxial layer) in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer. The first layer may include a first metal and a second metal. A second layer may comprise a material constructed and arranged to scavenge silicon migrating from the first semiconductor epi layer during annealing may be deposited over the first layer. The first semiconductor epi layer may be subjected to at least a first annealing act to provide a first structure. At least a portion of the first structure may be stripped to remove any of the first layer not reacted with silicon to form a silicide during the first annealing act.

Abstract: A plating apparatus 20 includes a substrate holding device 110 configured to hold and rotate the substrate 2; a first discharge device 30 configured to discharge a plating liquid toward the substrate 2 held on the substrate holding device 110; and a top plate 21 that is provided above the substrate 2 and has an opening 22. The first discharge device 30 includes a first discharge unit 33 configured to discharge the plating liquid toward the substrate 2, and the first discharge unit 33 is configured to be moved between a discharge position where the plating liquid is discharged and a standby position where the plating liquid is not discharged. Further, the first discharge unit 33 is configured to be overlapped with the opening 22 of the top plate 21 at the discharge position.

Abstract: Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a trench formed into one surface of the dielectric layer and a signal conductor that fills the trench and extends above the one surface of dielectric layer. The electrical interconnect further includes a conductive reference layer mounted on an opposing side of the dielectric layer. The conductive reference layer is electromagnetically coupled to the signal conductor when current passes through the signal conductor.

Abstract: There is provided a conductive pattern forming method that can suppress shape abnormalities caused by the reattachment of a neodymium component. A conductive pattern forming method according to an aspect of the invention includes forming an aluminum-neodymium alloy film on a base material; forming, on the aluminum-neodymium alloy film, a conductive film having a thickness greater than or equal to ¼ times the thickness of the aluminum-neodymium alloy film; and patterning the aluminum-neodymium alloy film and the conductive film by using dry etching.

Abstract: Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region.

Abstract: A thin film transistor (TFT), method of manufacturing the TFT and a flat panel display having the TFT are disclosed. In one aspect, the TFT comprises a substrate and an active layer formed over the substrate, wherein the active layer is formed of oxide semiconductor, and wherein the active layer includes two opposing sides. The TFT also comprises source and drain regions formed at the opposing sides of the active layer, a first insulating layer formed over the active layer, a gate electrode formed over the active layer, a second insulating layer formed covering the first insulation layer and the gate electrode, and a first conductive layer formed on the source and drain regions and contacting the second insulating layer.

Abstract: In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip including an electronic component is connected to the die pad. The die pad is configured with a recessed well extending from a top surface of the die pad towards a bottom surface of the die pad. The electronic component is position at least proximate to and overlapping the recessed well to increase the distance between the die pad and the electronic component. In one embodiment, the electronic component includes a passive component, such as an inductor. A package body encapsulates the electronic chip and top surfaces of the substrate, and is further disposed within the recessed well. The die pad bottom surface is continuous below the recessed well.

Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.

Abstract: A method of forming a molding layer includes the following operations: forming a substrate having at least one column structure thereon; flipping over the substrate having the column structure such that the column structure is beneath the substrate; dipping the column structure of the flipped substrate into a molding material fluid contained in a container; and separating the column structure of the flipped substrate from the container to form a molding layer covering and in contact with the column structure.

Abstract: Embodiments of the present disclosure provide a liner assembly including a plurality of individually separated gas passages. The liner assembly enables tenability of flow parameters, such as velocity, density, direction and spatial location, across a substrate being processed. The processing gas across the substrate being processed may be specially tailored for individual processes with a liner assembly according to embodiment of the present disclosure.

Abstract: In a substrate processing device 10 having a heating and drying unit 103 for drying a surface of a substrate W, the heating and drying unit 103 heats upward a vertically downward surface of the substrate W to dry the surface of the substrate by dropping and removing, by gravity, the droplets of the volatile solvent formed on the surface of the substrate W by the heating operation.

Abstract: To provide a cleaning method which makes it possible to reduce alkaline component mixing in an ozone cleaning solution, thereby preventing impairment of cleaning ability of ozone. In the cleaning method, before chuck members retain another workpiece having previously been dipped in an ozone cleaning solution in an ozone cleaning tank, alkaline component attached to part of transfer arms and the chuck members is removed by cleaning, thereby preventing the alkaline component from mixing into the ozone cleaning solution.

Abstract: In certain embodiments the metal liftoff tool comprises an immersion tank for receiving a wafer cassette with wafers therein, the immersion tank including an inner weir, a lifting and lowering mechanism capable of raising and lowering the wafer cassette while submerged in fluid in the immersion tank, low pressure high velocity primary spray jets for stripping the metal, the primary spray jets positioned at opposing sides of the immersion tank parallel to the wafer surfaces planes, and secondary spray jets for pressure equalization force, positioned at the bottom of the immersion tank. A wafer lift insert is positioned at the bottom of the immersion tank to receive and periodically lift the wafers within the cassette.

Abstract: An apparatus, such as a heater, is provided that includes a base member having at least one fluid passageway. A two-phase fluid is disposed within the fluid passageway, a pressure of the two-phase fluid being controlled such that the two-phase fluid provides at least one of heating and cooling to the base member. A tuning layer is secured to the base member, and the tuning layer includes a plurality of zones. Furthermore, a component, such as a chuck by way of example, is secured to the tuning layer.

Abstract: A coating method includes a step of forming a film of a coating solution having a larger thickness in a central region of a substrate than in an edge region of the substrate by discharging droplets of the coating solution from a plurality of nozzles formed on an inkjet head to the substrate, and a step of moving the coating solution in the film from the central region toward the edge region of the substrate by rotating the substrate. This reduces a difference in thickness of the film between the central region and the edge region of the substrate, thereby to make the film thickness substantially uniform. At the same time, the movement of the coating solution in the film can make the surface of the film smoother.

Abstract: A method comprises providing a handle substrate having a front surface and a back surface; providing a layer of flexible semiconductor material having a front surface and a back surface and an at least partially sacrificial backing layer stack on the back surface of the layer of flexible semiconductor material; bonding the front surface of the layer of flexible semiconductor material to the front surface of the handle substrate; removing at least a portion of the at least partially sacrificial backing layer stack from the back surface of the layer of flexible semiconductor material; opening outgassing paths through the layer of flexible semiconductor material; and processing the layer of flexible semiconductor material.

Abstract: There is provided a substrate separation device and method for separating a growth substrate from a laminate structure which includes a support substrate, a semiconductor layer, and the growth substrate. The device includes: a first base which is configured to hold the laminate structure thereon, and includes a first holding unit configured to hold the support substrate defining a bottom surface of the laminate structure and a heating unit configured to heat the laminate structure; and a second base including a second holding unit disposed above the first holding unit and configured to hold the growth substrate defining an upper surface of the laminate structure.

Abstract: A wafer transport system includes a substantially horizontal non-contact support platform for supporting a wafer substantially horizontally at a substantially fixed vertical distance from the platform. A wafer gripping device includes wafer grippers to grip a surface of the wafer that is opposite the non-contact support platform. Each of the wafer grippers is mounted on a vertically flexible holder to enable the wafer gripper to adapt to a height of the wafer above the wafer gripping device while maintaining a substantial horizontal rigidity of the vertically flexible holder so as to prevent horizontal motion of the wafer relative to the wafer gripping device.

Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.