Patents Issued in January 24, 2017
  • Patent number: 9553012
    Abstract: The present disclosure provides a FinFET. The FinFET includes a silicon-on-insulator (SOI) with an insulator; a plurality of fin structures on the insulator; an isolation on the insulator, and between two adjacent fin structures in the plurality of fin structures; and an oxide layer between each of the plurality of fin structures and the insulator, wherein the insulator comprises silicon germanium oxide. A method for manufacturing the FinFET includes forming a plurality of fin structures on a layer having a larger lattice constant than that of the fin structure by a patterning operation; oxidizing the fin structure and the layer to transform the layer into a first oxide layer; filling insulating material between adjacent fin structures; and etching the insulating material to expose a top surface and at least a portion of a sidewall of the fin structure.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: January 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9553013
    Abstract: A method is disclosed. The method comprises fabricating a device layer on a top portion of a semiconductor wafer that comprises a substrate. The device layer comprises an active device. The method also comprises forming a trap rich layer at a top portion of a handle wafer. The forming comprises etching the top portion of the handle wafer to form a structure in the top portion of the handle wafer that configures the trap rich layer. The method also comprises bonding a top surface of the handle wafer to a top surface of the semiconductor wafer. The method also comprises removing a bottom substrate portion of the semiconductor wafer.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: January 24, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Michael A. Stuber, George Imthurn
  • Patent number: 9553014
    Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: January 24, 2017
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 9553015
    Abstract: Embodiments of the present invention provide III-V-on-insulator (IIIVOI) platforms for semiconductor devices and methods for fabricating the same. According to one embodiment, compositionally-graded buffer layers of III-V alloy are grown on a silicon substrate, and a smart cut technique is used to cut and transfer one or more layers of III-V alloy to a silicon wafer having an insulator layer such as an oxide. One or more transferred layers of III-V alloy can be etched away to expose a desired transferred layer of III-V alloy, upon which a semi-insulating buffer layer and channel layer can be grown to yield IIIVOI platform on which semiconductor devices (e.g., planar and/or 3-dimensional FETs) can be fabricated.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Ali Khakifirooz, Davood Shahrjerdi
  • Patent number: 9553016
    Abstract: A method for a method of forming a semiconductor device includes providing a semiconductor substrate having a bottom surface opposite a top surface with circuitry disposed at the top surface. The method further includes forming a first metal layer having a first metal over the bottom surface of the semiconductor substrate. The first metal layer is formed by depositing an adhesion promoter followed by depositing the first metal.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: January 24, 2017
    Assignee: Infineon Technologies AG
    Inventors: Mark James Harrison, Martin Sporn
  • Patent number: 9553017
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal layer overlying a metal line of a metallization layer that is disposed in an ILD layer of dielectric material while an upper surface of the ILD layer that is laterally adjacent to the metal line is exposed. A hard mask layer is formed overlying the upper surface of the ILD layer laterally adjacent to the metal layer. The metal layer is removed to expose the metal line while leaving the hard mask layer intact. An interconnect is formed with the metal line adjacent to the hard mask layer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventor: Xunyuan Zhang
  • Patent number: 9553018
    Abstract: Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: January 24, 2017
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Kevin Lin, Kanwal Jit Singh, Alan M. Myers, Richard E. Schenker
  • Patent number: 9553019
    Abstract: A method for via alignment includes forming first airgaps between interconnect structures and depositing a pinch off layer to close off openings to the first airgaps. A protection layer is formed in divots in the pinch off layer. The protection layer and the pinch off layer are planarized to form a surface where the protection layer remains in the divots. An interlevel dielectric layer (ILD) is deposited on the surface. The ILD and the pinch off layer are etched using the protection layer as an etch stop to align a via and expose the interconnect structure through the via.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: January 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
  • Patent number: 9553020
    Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
  • Patent number: 9553021
    Abstract: In various embodiments, a method for processing a wafer may include: providing a wafer having at least one die region and at least one metallization disposed over the at least one die region; covering the at least one metallization with a protecting layer; plasma etching the wafer to form at least one die.
    Type: Grant
    Filed: September 3, 2012
    Date of Patent: January 24, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Markus Menath
  • Patent number: 9553022
    Abstract: In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are disposed on a first face of the wafer and wherein adjacent die areas are distanced from one another. A first trench and a second trench are formed on the first face between adjacent die areas. The first trench and the second trench are spaced apart from one another by a ridge. A third trench is disposed above the ridge on a second face of the wafer.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: January 24, 2017
    Assignee: Infineon Technologies AG
    Inventors: Michaela Braun, Markus Menath
  • Patent number: 9553023
    Abstract: A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: January 24, 2017
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Yoshimaro Fujii, Fumitsugu Fukuyo, Kenshi Fukumitsu, Naoki Uchiyama
  • Patent number: 9553024
    Abstract: Object is to provide a semiconductor device having improved reliability or performance. A high-breakdown-voltage n type transistor has source and drain regions having first, second, and third semiconductor regions, which are formed by ion implantation of a first impurity from the outside of a high-breakdown-voltage gate electrode, a second impurity from the outside of the high-breakdown-voltage gate electrode and a first sidewall insulating film, and a third impurity from the outside of the high-breakdown-voltage gate electrode and the first and second sidewall insulating films, respectively. The first and second impurities are implanted from a direction tilted by 45° relative to the main surface of the semiconductor substrate and the third impurity from a direction perpendicular thereto. The impurity concentration of the first semiconductor region is lower than that of the second one and the ion implantation energy of the first impurity is greater than that of the second impurity.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 24, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hirofumi Tokita
  • Patent number: 9553025
    Abstract: A method of forming a fin field-effect transistor (FinFET) includes forming a plurality of fins on a substrate. The method further includes forming an oxide layer on the substrate, wherein a bottom portion of each fin of the plurality of fins is embedded in the oxide layer, and the bottom portion of each fin of the plurality of fins has substantially a same shape. The method further includes shaping at least one fin of the plurality of fins, wherein a top portion of the at least one fin has a different shape from a top portion of another fin of the plurality of fins.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: January 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yi-Tang Lin, Chih-Sheng Chang, Chi-Wen Liu
  • Patent number: 9553026
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first mandrel, a second mandrel, a third mandrel, and a fourth mandrel are formed on the substrate. Preferably, the first mandrel and the second mandrel include a first gap therebetween, the second mandrel and the third mandrel include a second gap therebetween, and the third mandrel and the fourth mandrel include a third gap therebetween, in which the first gap is equivalent to the third gap but different from the second gap. Next, spacers are formed adjacent to the first mandrel, the second mandrel, the third mandrel, and the fourth mandrel, and the spacers in the first gap and the third gap are removed.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: January 24, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Chien-Ting Lin, Li-Chiang Chen, Jyh-Shyang Jenq
  • Patent number: 9553027
    Abstract: A fine-patterning method includes forming a mask layer with lower and upper mask layers on an underlying layer, forming a pair of sacrificial patterns on the mask layer, forming a connection spacer between the sacrificial patterns and first spacers that are spaced apart from each other with the pair of sacrificial patterns interposed therebetween and covering side surfaces of the sacrificial patterns, etching the upper mask layer using the first spacers and the connection spacer as an etch mask to form upper mask patterns, forming second spacers to cover side surfaces of the upper mask patterns, etching the lower mask layer using the second spacers as an etch mask to form lower mask patterns, and etching the underlying layer using the lower mask patterns as an etch mask.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: January 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyeong-seop Kim, Sungbong Kim, Myeongcheol Kim
  • Patent number: 9553028
    Abstract: A method includes forming a layer of insulating material above first and second transistors, within the layer of insulating material, forming a set of initial device-level contacts for each of the first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact, forming an initial local interconnect structure that is conductively coupled to one of the initial device-level contacts in each of the first and second transistors, and removing the initial local interconnect structure and portions, but not all, of the initial device-level contacts for each the first and second transistors. The method also includes forming a copper local interconnect structure and copper caps above the recessed device-level contacts.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Ryan Ryoung-Han Kim
  • Patent number: 9553029
    Abstract: A method includes forming a buried layer in a substrate, growing an epitaxial layer over the substrate, etching the epitaxial layer and the buried layer to form a first trench and a second trench, wherein the first trench and the second trench are of a same depth and a width of the second trench is greater than a width of the first trench, forming a dielectric layer in a bottom portion of the first trench, forming a first gate electrode in an upper portion of the first trench and filling the second trench with a gate electrode material, forming gate electrodes for a plurality of lateral transistors formed in the substrate, forming a body region, forming a first drain/source region over the body region and forming a second drain/source region over the epitaxial layer.
    Type: Grant
    Filed: September 5, 2015
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 9553030
    Abstract: A method of forming a semiconductor device is provided including providing a semiconductor-on-insulator (SOI) wafer comprising a first semiconductor layer comprising a first material component and formed on a buried oxide (BOX) layer, and forming a channel region of a P-channel transistor device, including forming a second semiconductor layer only over a first portion of the first semiconductor layer, wherein the second semiconductor layer comprises the first material component and a second material component different from the first material component, forming an opening in the first semiconductor layer outside the first portion and subsequently performing a thermal anneal to push the second material component from the second semiconductor layer into the first semiconductor layer.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hans-Peter Moll, Peter Baars
  • Patent number: 9553031
    Abstract: A method for making an integrated circuit includes a) providing a substrate including n-type metal oxide semiconductor field effect transistors (NMOSFETs) and p-type metal oxide semiconductor field effect transistors (PMOSFETs), wherein channel regions of the NMOSFETs and the PMOSFETs include germanium; b) depositing and patterning a mask layer to mask the channel regions of the PMOSFETs and to not mask the channel regions of the NMOSFETs; c) passivating an exposed surface of the substrate; d) removing the mask layer; and e) depositing a metal contact layer on both the NMOSFETs and the PMOSFETs.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 24, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Paul Raymond Besser, Thorsten Lill
  • Patent number: 9553032
    Abstract: Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer. In another embodiment, a growth-rate-enhancing dopant can be implanted by ion implantation onto sidewall surfaces of second semiconductor fins, while first semiconductor fins are masked by a masking layer. The differential growth rates of the deposited semiconductor material can cause raised active regions on the first semiconductor fins to remain unmerged, and raised active regions on the second semiconductor fins to become merged.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9553033
    Abstract: Methods and tools for generating measurement models of complex device structures based on re-useable, parametric models are presented. Metrology systems employing these models are configured to measure structural and material characteristics associated with different semiconductor fabrication processes. The re-useable, parametric sub-structure model is fully defined by a set of independent parameters entered by a user of the model building tool. All other variables associated with the model shape and internal constraints among constituent geometric elements are pre-defined within the model. In some embodiments, one or more re-useable, parametric models are integrated into a measurement model of a complex semiconductor device. In another aspect, a model building tool generates a re-useable, parametric sub-structure model based on input from a user.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: January 24, 2017
    Assignee: KLA-Tencor Corporation
    Inventors: Jonathan Iloreta, Matthew A. Laffin, Leonid Poslavsky, Torsten Kaack, Qiang Zhao, Lie-Quan Lee
  • Patent number: 9553034
    Abstract: A semiconductor wafer inspection system includes a camera and two or more illuminators. The illuminators illuminate a line of the semiconductor wafer in sequence and the camera captures an interleaved image of illuminated lines such that the individual images can be recovered from the interleaved image. The semiconductor wafer can be moved by a conveyor so that adjacent lines can be sequentially illuminated by the illuminators. The camera may include two or more line sensors.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: January 24, 2017
    Assignee: KLA-Tencor Corporation
    Inventors: Scott A. Young, Guoheng Zhao, NanChang Zhu, Neeraj Khanna
  • Patent number: 9553036
    Abstract: A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer covers the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: January 24, 2017
    Assignee: Powertech Technology Inc.
    Inventors: Shou-Chian Hsu, Hiroyuki Fujishima
  • Patent number: 9553037
    Abstract: A semiconductor device includes a semiconductor element having a front surface and a rear surface, a pair of heat sinks disposed facing each other so as to sandwich the semiconductor element, and attached respectively to the front surface and the rear surface, and a fastening screw fastening the pair of the heat sinks in the facing direction, the fastening screw having insulation property. Threads are arranged on at least a part of the fastening screw in an axis direction of the fastening screw between the pair of the heat sinks.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: January 24, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Rintaro Asai
  • Patent number: 9553038
    Abstract: An apparatus for cooling semiconductor elements uses heat exchangers to transfer heat from the semiconductor elements to a coolant flowing through the heat exchangers. A central body, made from a flexible material, is positioned between the heat exchangers and a manifold from which the coolant is provided. The central body includes a plurality of flexible runners fluidly coupled to each heat exchanger and the manifold to provide the coolant to the heat exchanger. Heat is transferred away from the semiconductor elements by the coolant and heated coolant is returned from the heat exchanger to the manifold. Each flexible runner is configured to flex to conform to a height of a respective semiconductor element and thereby apply a force to the heat exchanger to maintain contact with the semiconductor element.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: January 24, 2017
    Assignee: Raytheon Company
    Inventors: Christopher R. Koontz, Charles Chu, Rosalio S. Vidaurri
  • Patent number: 9553039
    Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three dimensional integration is offered by this scheme.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: January 24, 2017
    Assignee: AMS AG
    Inventors: Cathal Cassidy, Martin Schrems, Franz Schrank
  • Patent number: 9553040
    Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor package includes a substrate having a die attach surface. A die is mounted on die attach surface of the substrate via a conductive pillar bump. The die comprises a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, wherein the length of the first edge is different from that of the second edge from a plan view.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 24, 2017
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Tzu-Hung Lin, Ta-Jen Yu
  • Patent number: 9553041
    Abstract: Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. Methods and systems for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: January 24, 2017
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Michael G. Kelly, Ronald Patrick Huemoeller, Won Chul Do, David Jon Hiner
  • Patent number: 9553042
    Abstract: A wiring structure thereof includes a first interlayer insulating film, a first wiring and a first electrode for the capacitive element embedded in the first interlayer insulating film, a barrier insulating film formed over the first interlayer insulating film to cover the wiring and the electrode, a second interlayer insulating film formed over the barrier insulating film, and a second wiring and a second electrode for the capacitive element embedded in the second interlayer insulating film. The lower surface of the second wiring is positioned in the middle of the thickness of the second interlayer layer film, and the lower surface of the second electrode is in contact with the barrier insulating film. The barrier insulating film of a portion interposed between both electrodes functions as a capacitance insulating film of the capacitive element and is thicker than the barrier insulating film of a portion covering the first wiring.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 24, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Teruhiro Kuwajima
  • Patent number: 9553043
    Abstract: An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: January 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chung Lu, Wen-Hao Chen, Yuan-Te Hou, Fang-Yu Fan, Yu-Hsiang Kao, Dian-Hau Chen, Shyue-Shyh Lin, Chii-Ping Chen
  • Patent number: 9553044
    Abstract: An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis opposite the first axis to define a length. A capping layer is interposed between the first dielectric layer and the second dielectric layer. At least one electrically conductive feature is embedded in at least one of the first dielectric layer and the second dielectric layer. At least one electrically conductive via extends through the second dielectric layer and the capping layer. The via has an end that contacts the conductive feature. The end includes a flange having at least one portion extending laterally along the first axis to define a contact area between the via and the at least one conductive feature.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, James J. Demarest, Sean Teehan, Chih-Chao Yang
  • Patent number: 9553045
    Abstract: An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Jie Chen, Ying-Ju Chen, Tsung-Yuan Yu
  • Patent number: 9553046
    Abstract: A method of forming a semiconductor device comprising a fuse is provided including providing a semiconductor-on-insulator (SOI) structure comprising an insulating layer and a semiconductor layer formed on the insulating layer, forming raised semiconductor regions on the semiconductor layer adjacent to a central portion of the semiconductor layer and performing a silicidation process of the central portion of the semiconductor layer and the raised semiconductor regions to form a silicided semiconductor layer and silicided raised semiconductor regions.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Peter Baars, Hans-Peter Moll
  • Patent number: 9553047
    Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the patterning of the array and periphery regions in self-aligned quadruple patterning and provide semiconductor devices resulting from the combined patterning.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: January 24, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Min Hung, Tzung-Ting Han, Miao-Chih Hsu
  • Patent number: 9553048
    Abstract: According to one embodiment, in a semiconductor device, a second contact is disposed at a position that is shifted from a first contact by a distance approximately of P in a first direction and by a distance approximately of ?8×P in a second direction. A third contact is disposed at a position that is shifted from the first contact by a distance approximately of 2P in the first direction and by a distance approximately of ?8×P/2 in the second direction. A fourth contact is disposed at a position that is shifted from the first contact by a distance approximately of 3P in the first direction. A fifth contact is disposed at a position that is shifted from the fourth contact by a distance approximately of P in the first direction and by a distance approximately of ?8×P in the second direction.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 24, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satomi Higashibata
  • Patent number: 9553049
    Abstract: Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a compound semiconductor, a first barrier layer disposed over the first Ti layer, a second Ti layer disposed over the first barrier layer, and a copper (Cu) layer disposed over the second Ti layer. The second Ti layer can be configured to inhibit or reduce alloying of the Cu layer and the first barrier layer. The first Ti layer, the first barrier layer, and the second Ti layer can be configured to yield a barrier between the Cu layer and an ohmic metal layer formed on the compound semiconductor. The metalized structure can further include a third Ti layer disposed over the Cu layer and a second barrier layer disposed over the third Ti layer. The first and second barrier layers can include platinum (Pt) and/or palladium (Pd).
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: January 24, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: Kezia Cheng
  • Patent number: 9553050
    Abstract: A semiconductor device includes a semiconductor substrate, an interlayer insulating film on the semiconductor substrate and having a first hole extending therethrough, and a contact portion in the first hole of the interlayer insulating film. The contact portion includes a first silicon film along an inner surface of the first hole of the interlayer insulating film.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: January 24, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ming Hu, Akira Yotsumoto
  • Patent number: 9553051
    Abstract: In an embodiment, an electronic component includes a dielectric layer having a first surface and a second surface, one or more semiconductor dies embedded in the dielectric layer and at least one electrically conductive member. The electrically conductive member includes a first portion and a second portion. The first portion includes a foil including a first metal and the second portion includes an electrodeposited layer including a second metal. The first portion and the second portion are embedded in the dielectric layer.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: January 24, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Petteri Palm, Holger Torwesten, Manfred Schindler, Boris Plikat
  • Patent number: 9553052
    Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall at a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 24, 2017
    Assignee: J-DEVICES CORPORATION
    Inventors: Hiroaki Matsubara, Toshihiro Iwasaki, Tomoshige Chikai, Kiminori Ishido, Shinji Watanabe, Michiaki Tamakawa
  • Patent number: 9553053
    Abstract: A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Wei Chiu, Tzu-Yu Wang, Shang-Yun Hou, Shin-Puu Jeng, Hsien-Wei Chen, Hung-An Teng, Wei-Cheng Wu
  • Patent number: 9553054
    Abstract: Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring structures associated with a lower wafer structure. The method further includes bonding the lower wafer structure to an upper wafer structure and thinning the upper wafer, and forming upper metal wiring structures. The method further includes electrically linking the lower metal wiring structures to the upper metal wiring structures by formation of through silicon via structures to form an electrically connected chain extending between multiple wafer structures. The method further includes forming contacts to an outside environment which electrically contact two of the lower metal wiring structures.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Erdem Kaltalioglu, Wei Lin, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9553055
    Abstract: The present disclosure provides a method for fabricating semiconductor devices having reinforcing elements. The method includes steps of providing a first wafer having a lower electrode layer and an insulation layer; forming a device layer; etching the device layer and the insulation layer to form recesses; etching the device layer to form separation trenches and upper electrodes; forming reinforcing elements; and depositing metal pads. The reinforcing elements strengthen the integration of the upper electrodes and the insulation layer.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: January 24, 2017
    Assignee: ASIA PACIFIC MICROSYSTEMS, INC.
    Inventor: Hung-Lin Yin
  • Patent number: 9553056
    Abstract: Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Joel P. de Souza, Bahman Hekmatshoartabari, Daniel M. Kuchta, Devendra K. Sadana
  • Patent number: 9553057
    Abstract: A method of forming an E-plane probe includes forming a plurality of monolithically integrated circuits (MICs) on a wafer, each MIC including a monolithic microwave integrated circuit (MMIC), and an E-plane probe coupled to the MMIC, mounting the wafer on an ultra-violet (UV) tape, cutting the wafer with a laser at a first power and a first linear cutting speed along vertical streets and then along horizontal streets to form separate substrates, cutting with the laser at a second power and a second linear cutting speed a rectangle or a portion of a rectangle from the separate substrates to form narrow substrate extensions on the substrates, and repeating this step for each rectangle or portion of a rectangle to be cut to form substrate extensions, and curing the UV tape, wherein the E-plane probes are on the narrow substrate extensions.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 24, 2017
    Assignee: HRL Laboratories, LLC
    Inventors: Eric M. Prophet, Alexandros D. Margomenos, Miroslav Micovic
  • Patent number: 9553058
    Abstract: A method of forming a network of RDL lines on the backside of a thinned TSV die to control warpage and the resulting device are provided. Embodiments include providing a thinned TSV die of a 3D IC stack, the thinned TSV die having a front side and a back side; forming a plurality of RDL lines across the backside of the die; and forming a plurality of UBM structures across the backside of the die.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luke England, Rahul Agarwal
  • Patent number: 9553059
    Abstract: An embodiment package on package (PoP) device includes a molding compound having a metal via embedded therein, a passivation layer disposed over the molding compound, the passivation layer including a passivation layer recess vertically aligned with the metal via, and a redistribution layer bond pad capping the metal via, a portion of the redistribution layer bond pad within the passivation layer recess projecting above a top surface of the molding compound.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 9553060
    Abstract: Provided are a semiconductor device and a manufacturing method therefor that can prevent electric short-circuiting between redistribution lines. A barrier film is formed over each side surface of a copper redistribution line. The barrier film includes, for example, a manganese oxide film. The barrier film is also in contact with each end surface of a barrier metal film that is located in the position receding inward from the side surface of the copper redistribution line. A redistribution portion is formed by the copper redistribution line, the barrier film, and the barrier metal film.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: January 24, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuyuki Omori
  • Patent number: 9553061
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to wire bond pad structures and methods of manufacture. The structure includes: bond pads in an active region of a chip; test pad structures in a kerf region of the chip; and hardmask material in the kerf region between the test pad structures and the bond pads. The surfaces of the test pad structures and the bond pads are devoid of the hardmask material.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Donald R. Letourneau, Patrick S. Spinney, Leah J. Bagley, John M. Sutton
  • Patent number: 9553062
    Abstract: A fingerprint identification device includes a first dielectric layer, a fingerprint sensing chip, a packaging layer, a first redistribution layer, a second dielectric layer, a second redistribution layer, and a third dielectric layer. The fingerprint sensing chip is disposed on the first dielectric layer and has a sensing transmission pad. The packaging layer defines a first via hole and covers the first dielectric layer and fingerprint sensing chip. Disposed on the packaging layer, the first redistribution layer contacts a drive transmission pad via the first via hole. The second dielectric layer defines a second via hole and covers the packaging layer and the first redistribution layer. Disposed on the second dielectric layer, the second redistribution layer defines a looped pattern, in addition to connect electrically with the first redistribution layer via the second via hole. The third dielectric layer covers the second dielectric layer and second redistribution layer.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 24, 2017
    Assignee: J-METRICS TECHNOLOGY CO., LTD.
    Inventors: Chen-Chih Fan, Wei-Ting Lin, Shih-Chun Kuo