Patents Issued in February 7, 2017
  • Patent number: 9564500
    Abstract: A method of forming a MOSFET device is provided including: providing an SOI wafer; forming a dummy gate oxide and dummy gates on portions of the SOI layer that serve as channel regions of the device; forming spacers and doped source/drain regions in the SOI layer on opposite sides of the dummy gates; depositing a gap fill dielectric; removing the dummy gates/gate oxide; recessing areas of the SOI layer exposed by removal of the dummy gates forming one or more u-shaped grooves that extend part-way through the SOI layer such that a thickness of the SOI layer remaining in the channel regions is less than a thickness of the SOI layer in the doped source/drain regions under the spacers; and forming u-shaped replacement gate stacks in the u-shaped grooves such that u-shaped channels are formed in fully depleted regions of the SOI layer adjacent to the u-shaped replacement gate stacks.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Robert H. Dennard, Isaac Lauer, Ramachandran Muralidhar
  • Patent number: 9564501
    Abstract: The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: February 7, 2017
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Liu, Xiuyu Cai, Ruilong Xie, Chun-chen Yeh
  • Patent number: 9564502
    Abstract: In one aspect, a method of forming a CMOS device with multiple transistors having different Vt's is provided which includes: forming nanowires and pads on a wafer, wherein the nanowires are suspended at varying heights above an oxide layer of the wafer; and forming gate stacks of the transistors at least partially surrounding portions of each of the nanowires by: i) depositing a conformal gate dielectric around the nanowires and on the wafer beneath the nanowires; ii) depositing a conformal workfunction metal on the conformal gate dielectric around the nanowires and on the wafer beneath the nanowires, wherein an amount of the conformal workfunction metal deposited around the nanowires is varied based on the varying heights at which the nanowires are suspended over the oxide layer; and iii) depositing a conformal poly-silicon layer on the conformal workfunction metal around the nanowires and on the wafer beneath the nanowires.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 9564503
    Abstract: A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a first electrode 22 containing Ti or Ta on a top face of a nitride semiconductor layer 18; a second step of forming a second electrode 24 containing Al on a top face of the first electrode 22; a third step of forming a coating metal layer 26 covering at least one of an edge of a top face of the second electrode 24 and a side face of the second electrode 24, having a window 26a exposing the top face of the second electrode 24 in a region separated from the foregoing edge, and containing at least one of Ta, Mo, Pd, Ni, and Ti; and a step of performing a thermal treatment, after the third step.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: February 7, 2017
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Patent number: 9564504
    Abstract: A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a first electrode 22 containing Ti or Ta on a top face of a nitride semiconductor layer 18; a second step of forming a second electrode 24 containing Al on a top face of the first electrode 22; a third step of forming a coating metal layer 26 covering at least one of an edge of a top face of the second electrode 24 and a side face of the second electrode 24, having a window 26a exposing the top face of the second electrode 24 in a region separated from the foregoing edge, and containing at least one of Ta, Mo, Pd, Ni, and Ti; and a step of performing a thermal treatment, after the third step.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: February 7, 2017
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Patent number: 9564505
    Abstract: Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: February 7, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael P. Chudzik, Martin M. Frank, Herbert L. Ho, Mark J. Hurley, Rashmi Jha, Naim Moumen, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri
  • Patent number: 9564506
    Abstract: Embodiments of the present invention provide methods for fabricating a semiconductor device. One method may include providing a semiconductor substrate with fins etched into the semiconductor substrate; forming a gate structure and depositing an insulating material around the gate structure; selectively etching an active device area; forming a set of spacers on the sides of the gate structure; growing a doped source and drain region; depositing an insulator over an upper surface of a deposited etch stop layer; and depositing a metal into a contact opening to form one or more contacts.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 9564507
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first tensile dielectric layer on the substrate; a metal gate in the first tensile dielectric layer; a second tensile dielectric layer on the first tensile dielectric layer; and a contact plug in the first tensile dielectric layer and the second tensile dielectric layer. Preferably, the top surface of the contact plug is even with the top surface of the second tensile dielectric layer, and a carbon content of the second tensile dielectric layer is greater than the carbon content of the first tensile dielectric layer.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: February 7, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Cheng Lin, Hui-Shen Shih
  • Patent number: 9564508
    Abstract: A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: February 7, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mattias E. Dahlstrom, Dinh Dang, Qizhi Liu, Ramana M. Malladi
  • Patent number: 9564509
    Abstract: A method of fabricating an integrated circuit device includes forming a first gate structure in a first region of a substrate and a second gate structure in a second region of the substrate. The method includes forming a protective layer overlying the first and the second gate structures. The method includes removing a portion of the protective layer over the second gate structure. The method includes forming features adjacent to the second gate structure. The method further includes forming a spacer over at least a portion of the features adjacent to the second gate structure, wherein the features separate the spacer from the substrate adjacent to the second gate structure. The method includes removing the second portion of the protective layer. Removing the second portion of the protective layer includes forming a protector over the second gate structure; and performing an etching process using a chemical comprising hydrofluoric acid (HF).
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: February 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hsi Yeh, Hsien-Hsin Lin, Ying-Hsueh Chang Chien, Yi-Fang Pai, Chi-Ming Yang, Chin-Hsiang Lin
  • Patent number: 9564510
    Abstract: A method of fabricating a MOSFET with an undoped channel is disclosed. The method comprises fabricating on a substrate a semiconductor structure having a dummy poly gate, dummy interlayer (IL) oxide, and a doped channel. The method further comprises removing the dummy poly gate and the dummy IL oxide to expose the doped channel, removing the doped channel from an area on the substrate, forming an undoped channel for the semiconductor structure at the area on the substrate, and forming a metal gate for the semiconductor structure. Removing the dummy poly gate may comprise dry and wet etch operations. Removing the dummy IL oxide may comprise dry etch operations. Removing the doped channel may comprise anisotropic etch operations on the substrate. Forming an undoped channel may comprise applying an epitaxial process to grow the undoped channel. The method may further comprise growing IL oxide above the undoped channel.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Hsiung Lin, Chia-Der Chang, Jung-Ting Chen, Tai-Yuan Wang
  • Patent number: 9564511
    Abstract: A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Jen Liu, Li-Chieh Wu, Liang-Guang Chen, Shich-Chang Suen
  • Patent number: 9564512
    Abstract: A method for fabricating a FinFET structure comprises providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a dummy gate structure having a dummy gate, a first sidewall spacer and a second sidewall spacer; removing the dummy gate to form a first trench; forming first sub-fins in the semiconductor substrate under the hard mask layer in the first trench; forming a first metal gate structure in the first trench; removing the first sidewall spacer to form a second trench; forming second sub-fins in the semiconductor substrate under the hard mask layer in the second trench; forming a second metal gate structure in the second trench; removing the second sidewall spacer to form a third trench; forming third sub-fins in the semiconductor substrate under the hard mask layer in the third trench; and forming a third metal gate structure in the third trench.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: February 7, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Haiyang Zhang, Chenglong Zhang
  • Patent number: 9564513
    Abstract: A semiconductor structure including a semiconductor substrate is provided. The semiconductor substrate includes a surface. A gate structure is provided on the surface. An interface lower than the surface is provided. An epitaxial regrowth region adjacent the gate structure is disposed on the interface. In addition, the epitaxial regrowth region extends over the surface and includes a bottom layer and a cap layer. The activation of the cap layer is lower than that of the bottom layer. Moreover, the bottom layer is lower than the surface and the gate structure. Furthermore, the bottom layer includes a first downwardly-curved edge and a second downwardly-curved edge over the first one. The first downwardly-curved edge is connected with the second downwardly-curved edge at two endpoints. The two endpoints are in contact with the surface of the semiconductor substrate.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: February 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Chieh Chang, Ying-Min Chou, Yi-Ming Huang, Chun-Ju Huang, Huai-Tei Yang, Kei-Wei Chen
  • Patent number: 9564514
    Abstract: An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Amlan Majumdar, Jeffrey W. Sleight
  • Patent number: 9564515
    Abstract: A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a first trench, a first doped region of a second conductivity type opposite to the first conductivity type, a second trench and a second doped region of the first conductivity type. The epitaxial layer of the first conductivity type is over the substrate. The first trench is in the epitaxial layer. The first doped region of the second conductivity type is in the epitaxial layer and surrounds the first trench. The second trench is in the epitaxial layer and separated from the first trench. The second doped region of the first conductivity type is in the epitaxial layer and surrounds the second trench. The second doped region has a dopant concentration greater than a dopant concentration of the epitaxial layer. A method for manufacturing the semiconductor device is also provided.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: February 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jheng-Sheng You, Che-Yi Lin, Shen-Ping Wang, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu
  • Patent number: 9564516
    Abstract: A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respectively a vertical source-contact surface and a vertical body-contact surface; a patterned dielectric layer atop the Kelvin-contact source and the trench gate; a patterned top metal layer. As a result: a planar ledge is formed atop the Kelvin-contact source; the MOSFET device exhibits a lowered body Kelvin contact impedance and, owing to the presence of the planar ledge, a source Kelvin contact impedance that is lower than an otherwise MOSFET device without the planar ledge; and an integral parallel Schottky diode is also formed.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: February 7, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Ji Pan
  • Patent number: 9564517
    Abstract: To provide a manufacturing method of a highly reliable TFT, by which a more refined pattern can be formed through a process using four or three masks, and a semiconductor device. A channel-etched bottom gate TFT structure is adopted in which a photoresist is selectively exposed to light by rear surface exposure utilizing a gate wiring to form a desirably patterned photoresist, and further, a halftone mask or a gray-tone mask is used as a multi-tone mask. Further, a step of lifting off using a halftone mask or a gray-tone mask and a step of reflowing a photoresist are used.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: February 7, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kunio Hosoya, Saishi Fujikawa, Yoko Chiba
  • Patent number: 9564518
    Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: February 7, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Vladimir Machkaoutsan, Jeffrey Junhao Xu, Stanley Seungchul Song, Mustafa Badaroglu, Choh Fei Yeap
  • Patent number: 9564519
    Abstract: There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Taek Park, Young Woo Park, Jae Duk Lee
  • Patent number: 9564520
    Abstract: A method of forming a semiconductor device is disclosed. A sacrificial oxide layer is formed on a substrate having first and second areas. Using a photoresist mask exposing the first area and covering the second area as a mask layer, by a wet etching process, the sacrificial oxide layer in the first area and an edge portion of the sacrificial oxide layer in the second area are simultaneously removed, wherein the sacrificial oxide layer remained in the second area has a sidewall with a slope smaller than 40 degrees. An oxide-nitride-oxide (ONO) layer is formed over the first and second areas. The sacrificial oxide layer and the ONO layer formed thereon in the second area are removed, so that the ONO layer remained in the first area forms a first gate insulating layer in the first area. A second gate insulating layer is formed in the second area.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 7, 2017
    Assignee: United Microelectronics Corp.
    Inventor: Tzu-Ping Chen
  • Patent number: 9564521
    Abstract: A semiconductor device comprises a first and second circuit element. The first circuit element comprises a first electrode structure including a first high-k dielectric layer, the first high-k dielectric layer having a first thickness and comprising hafnium. The second circuit element comprises a second electrode structure that includes a second high-k dielectric layer having a ferroelectric behavior, wherein the second high-k dielectric layer has a second thickness and comprises hafnium, and wherein the second thickness is greater than the first thickness.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: February 7, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Till Schloesser, Peter Baars
  • Patent number: 9564522
    Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: February 7, 2017
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Annalisa Cappellani, Martin D. Giles, Rafael Rios, Seiyon Kim, Kelin J. Kuhn
  • Patent number: 9564523
    Abstract: The present invention is notably directed to a spin-orbit coupled device. This device comprises a confinement part. It further includes a circuitry, having an input device, energizable to inject spin-polarizations to charge carriers in an input region of the confinement part. The circuitry further comprises an output device, usable to detect spin-polarizations of charge carriers in an output region of the confinement part. The confinement part may be is configured to subject charge carriers drifting therein to a non-linear spin-orbit interaction, which causes to rotate a spin polarization of the drifting charge carriers by an angle that depends non-linearly on momenta of such charge carriers. The circuitry may be configured to allow momenta of charge carriers drifting in the confinement part to be varied, while injecting spin-polarizations in the input region. Varying momenta allows spin-polarizations of drifting charge carriers to be rotated, owing to said non-linear spin-orbit interaction.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: February 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Patrick B. Altmann, Gian von Salis
  • Patent number: 9564524
    Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: February 7, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen, Simone Lavanga, Gianmauro Pozzovivo, Fabian Reiher
  • Patent number: 9564525
    Abstract: A compound semiconductor device includes: a substrate; and a buffer layer, a first carrier supply layer, a first spacer layer, a channel layer, a second spacer layer, a second carrier supply layer, and a contact layer provided in order on the substrate, wherein the first carrier supply layer is a uniformly doped layer in which an impurity is uniformly doped, the second carrier supply layer is a planar doped layer in which an impurity is locally doped, and no Al mixed crystal layer having higher resistance values than the first and second spacer layers is provided between the buffer layer and the first spacer layer and between the second spacer layer and the contact layer.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: February 7, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Susumu Hatakenaka, Harunaka Yamaguchi
  • Patent number: 9564526
    Abstract: A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Can Bayram, Christopher Peter D'Emic, William J. Gallagher, Effendi Leobandung, Devendra K. Sadana
  • Patent number: 9564527
    Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: February 7, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, Masato Nishimori, Tadahiro Imada
  • Patent number: 9564528
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. An isolation insulating layer is formed so that an upper part of the fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the fin structure. Recesses are formed in the isolation insulating layer at both sides of the fin structure. A recess is formed in a portion of the fin structure which is not covered by the gate structure. The recess in the fin structure and the recesses in the isolation insulating layer are formed such that a depth D1 of the recess in the fin structure and a depth D2 of the recesses in the isolation insulating layer measured from an uppermost surface of the isolation insulating layer satisfy 0?D1?D2 (but D1 and D2 are not zero at the same time).
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: February 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
  • Patent number: 9564529
    Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
  • Patent number: 9564530
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate; a channel region of a first type conductivity, defined in the fin active region and having a first carrier concentration; and an anti-punch through (APT) feature of the first type conductivity, wherein the APT feature is formed in the semiconductor substrate, is directly underlying the channel region, and has a second carrier concentration greater than the first carrier concentration.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ziwei Fang, Tsan-Chun Wang
  • Patent number: 9564531
    Abstract: Thin film transistors including a semiconductor channel disposed between a drain electrode and a source electrode; and a gate insulating layer disposed between the semiconductor channel and a gate electrode wherein the semiconductor channel includes a first metal oxide, the gate insulating layer includes a second metal oxide, and at least one metal of the second metal oxide is the same as at least one metal of the first metal oxide, methods of manufacturing thin film transistors, and semiconductor device including thin film transistors.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Bae Park, Myung-Kwan Ryu, Jong-Baek Seon, Sang-Yoon Lee, Bon-Won Koo
  • Patent number: 9564532
    Abstract: An array substrate including a substrate including a pixel region; a gate line on the substrate; a gate electrode on the substrate and connected to the gate line; a gate insulating layer on the gate line and the gate electrode; a data line on the gate insulating layer and crossing the gate line to define the pixel region; a source electrode and a drain electrode on the gate insulating layer and corresponding to the gate electrode, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode; and an oxide semiconductor layer on top of the source and drain electrodes.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 7, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Yong-Woo Yoo, Sang-Hyun Bae, Ju-Yeon Kim
  • Patent number: 9564534
    Abstract: The band tail state and defects in the band gap are reduced as much as possible, whereby optical absorption of energy which is in the vicinity of the band gap or less than or equal to the band gap is reduced. In that case, not by merely optimizing conditions of manufacturing an oxide semiconductor film, but by making an oxide semiconductor to be a substantially intrinsic semiconductor or extremely close to an intrinsic semiconductor, defects on which irradiation light acts are reduced and the effect of light irradiation is reduced essentially. That is, even in the case where light with a wavelength of 350 nm is delivered at 1×1013 photons/cm2·sec, a channel region of a transistor is formed using an oxide semiconductor, in which the absolute value of the amount of the variation in the threshold voltage is less than or equal to 0.65 V.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: February 7, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Kosei Noda
  • Patent number: 9564535
    Abstract: A change in electrical characteristics is inhibited and reliability is improved in a semiconductor device using a transistor including an oxide semiconductor. One embodiment of a semiconductor device including a transistor includes a gate electrode, first and second insulating films over the gate electrode, an oxide semiconductor film over the second insulating film, and source and drain electrodes electrically connected to the oxide semiconductor film. A third insulating film is provided over the transistor and a fourth insulating film is provided over the third insulating film. The third insulating film includes oxygen. The fourth insulating film includes nitrogen. The amount of oxygen released from the third insulating film is 1×1019/cm3 or more by thermal desorption spectroscopy, which is estimated as oxygen molecules. The amount of oxygen molecules released from the fourth insulating film is less than 1×1019/cm3.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: February 7, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Daisuke Kurosaki
  • Patent number: 9564536
    Abstract: The present invention is applicable to the field of electronic component technologies and provides a manufacturing method of a self-aligned metal oxide TFT component, including: selecting a substrate and preparing a gate on the substrate; successively disposing an insulation layer, a transparent electrode layer, and a photoresist on the gate; using the gate as a mask to perform exposure from a back side of the substrate, so as to form a source and a drain that are aligned with the gate; depositing a metal oxide semiconductor layer on the transparent electrode layer; performing etching on the semiconductor layer, the source, and the drain, so that outer ends of the source and the drain are exposed out of the metal oxide semiconductor layer; and depositing a passivation layer and leading out the source and the drain.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: February 7, 2017
    Assignee: SHENZHEN ROYOLE TECHNOLOGIES CO., LTD.
    Inventors: Peng Wei, Xiaojun Yu, Zihong Liu
  • Patent number: 9564537
    Abstract: Disclosed herein is a method for manufacturing an array substrate. The method includes forming a source electrode and a drain electrode on a substrate. A semiconductor layer, an organic insulating layer, and a gate electrode layer are sequentially formed to cover the substrate, the source electrode, and the drain electrode. A patterned photoresist layer is formed on the gate electrode layer. The exposed portion of the gate electrode layer, and a portion of the organic insulative layer and a portion of the semiconductor layer thereunder are removed to form a gate electrode. An organic passivation layer is formed on the gate electrode, the source electrode, and the drain electrode. The organic passivation layer has a contact window to expose a portion of the drain electrode. A pixel electrode is formed on the organic passivation layer and the exposed portion of the drain electrode.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: February 7, 2017
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Chou Lan, Ted-Hong Shinn, Henry Wang, Chia-Chun Yeh
  • Patent number: 9564538
    Abstract: A semiconductor device includes a first insulating layer having a first side wall, an oxide semiconductor layer located on the first side wall, a gate insulating layer located on the oxide semiconductor layer, the oxide semiconductor layer being located between the first side wall and the gate insulating layer, a gate electrode facing the oxide semiconductor layer located on the first side wall, the gate insulating layer being located between the oxide semiconductor layer and the gate electrode, a first electrode located below the oxide semiconductor layer and connected with one portion of the oxide semiconductor layer, and a second electrode located above the oxide semiconductor layer and connected with the other portion of the oxide semiconductor layer.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: February 7, 2017
    Assignee: Japan Display Inc.
    Inventor: Toshinari Sasaki
  • Patent number: 9564539
    Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: February 7, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mizuki Sato
  • Patent number: 9564540
    Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.
    Type: Grant
    Filed: July 18, 2015
    Date of Patent: February 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Uozaki, Yasuhiro Takeda, Keiichi Maekawa, Takumi Hasegawa, Kota Funayama, Yoshiki Maruyama, Kazutoshi Shiba, Shuichi Kudo
  • Patent number: 9564541
    Abstract: A diode is integrated on a semiconductor chip having anode and cathode surfaces opposite to each other. The diode comprises a cathode region extending inwardly from the cathode surface, a drift region extending between the anode surface and the cathode region, and a plurality of anode regions extending from the anode surface in the drift region. The diode further comprises a cathode electrode coupled with the cathode region, and an anode electrode that contacts one or more contacted anode regions of said anode regions and is electrically insulated from one or more floating anode regions of the anode regions. The diode is configured so that charge carriers are injected from the floating anode regions into the drift region in response to applying of a control voltage exceeding a threshold voltage.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: February 7, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Alessandria, Leonardo Fragapane
  • Patent number: 9564542
    Abstract: A solar cell formation method, and resulting structure, having a first film and a barrier film over a surface of a doped semiconductor, wherein the optical and/or electrical properties of the first film are transformed in-situ such that a resulting transformed film is better suited to the efficient functioning of the solar cell; wherein portions of the barrier film partially cover the first film and substantially prevent transformation of first film areas beneath the portions of the barrier film.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: February 7, 2017
    Assignee: TETRASUN, INC.
    Inventors: Adrian Bruce Turner, Oliver Schultz-Wittmann, Denis De Ceuster, Douglas E. Crafts
  • Patent number: 9564543
    Abstract: Methods for doping an absorbent layer of a p-n heterojunction in a thin film photovoltaic device are provided. The method can include depositing a window layer on a transparent substrate, where the window layer includes at least one dopant (e.g., copper). A p-n heterojunction can be formed on the window layer, with the p-n heterojunction including a photovoltaic material (e.g., cadmium telluride) in an absorber layer. The dopant can then be diffused from the window layer into the absorber layer (e.g., via annealing).
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: February 7, 2017
    Assignee: First Solar, Inc.
    Inventors: Scott Daniel Feldman-Peabody, Robert Dwayne Gossman
  • Patent number: 9564544
    Abstract: A solar cell production method, whereby: a plurality of solar cell strings connecting a prescribed number of solar cells in series are formed; a plurality of solar cell strings are lined up along a second direction intersecting a first direction in which the solar cell strings extend, and the same are arranged such that the interval at one end of the first direction between adjacent solar cell strings is smaller than the interval at the other end; the arranged plurality of solar cell strings are connected to each other and a solar cell connection body is formed; a first filling material sheet, the solar cell connection body, a second filling material sheet, and a second protective member are laminated upon a first protective member having a curved surface; pressure is applied from above the second protective member; and a solar cell module having a curved surface shape is formed.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: February 7, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yosuke Ishii, Yuki Oikawa, Satoshi Suzuki
  • Patent number: 9564545
    Abstract: The present invention is premised upon an assembly that includes at least a photovoltaic sheathing element capable of being affixed on a building structure. The shingle including at least a photovoltaic cell assembly, a body portion attached to one or more portions of the photovoltaic cell assembly. Wherein the body portion includes one or more top peripheral tabs each capable of fitting under one or more vertically adjoining devices.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: February 7, 2017
    Assignee: DOW GLOBAL TECHNOLOGIES LLC
    Inventors: James R Keenihan, Joseph A Langmaid, Leonardo C. Lopez
  • Patent number: 9564546
    Abstract: An interconnector for electrically connecting a first electronic device element and a second electronic device element includes first and second connection portions which are respectively connected to electrodes of the first and second electronic device elements. A plurality of strip-like intermediate portions are each connected to both the first connection portion and the second connection portion to electrically connect the first connection portion and the second connection portion. The intermediate portions are mutually separated from one another in the width direction and mutually extending in parallel directions. Each intermediate portion has a first curved portion which is curved to be concave at one side of the respective intermediate portion in the width direction, and a second curved portion which is curved to be concave at another side of the respective intermediate portion in the width direction.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: February 7, 2017
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Mitsuru Okubo
  • Patent number: 9564547
    Abstract: A solar cell module and a method of manufacturing the same are discussed. The solar cell module includes a plurality of back contact solar cells, an interconnector that is positioned on back surfaces of the plurality of back contact solar cells and electrically connects adjacent back contact solar cells to one another, upper and lower protective layers for protecting the plurality of back contact solar cells, a transparent member that is positioned on the upper protective layer on light receiving surfaces of the plurality of back contact solar cells, and a back sheet that is positioned under the lower protective layer on surfaces opposite the light receiving surfaces of the plurality of back contact solar cells. The upper protective layer and the lower protective layer are formed of different materials.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: February 7, 2017
    Assignee: LG ELECTRONICS INC.
    Inventor: Sungeun Lee
  • Patent number: 9564548
    Abstract: The disclosure provides for a direct wafer bonding method including providing a bonding layer upon a first and second wafer, and directly bonding the first and second wafers together under heat and pressure. The method may be used for directly bonding an GaAs-based, InP-based, GaP-based, GaSb-based, or Ga(In)N-based device to a GaAs device by introducing a highly doped (Al)(Ga)InP(As)(Sb) layer between the devices. The bonding layer material forms a bond having high bond strength, low electrical resistance, and high optical transmittance.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: February 7, 2017
    Assignee: The Boeing Company
    Inventors: Dhananjay M. Bhusari, Daniel C. Law
  • Patent number: 9564549
    Abstract: A diode comprising a light-sensitive germanium region which is totally embedded in silicon and forms with the silicon a lower interface and lateral interfaces, wherein the lateral interfaces do not extend perpendicularly, but obliquely to the lower interface and therefore produce a faceted form.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 7, 2017
    Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ-INSTITUT FUR INNOVATIVE MIKROELEKTRONIK
    Inventors: Dieter Knoll, Stefan Lischke, Lars Zimmermann, Yuji Yamamoto, Andreas Trusch
  • Patent number: 9564550
    Abstract: According to various embodiments, an optoelectronic component may be provided, the optoelectronic component including: an electrode structure disposed at least one of over and in a carrier; and a grating structure disposed over the electrode structure, the grating structure including at least a first region and a second region, wherein the first region of the grating structure includes amorphous silicon; and wherein the second region of the grating structure includes a material having a refractive index different from the refractive index of the amorphous silicon.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: February 7, 2017
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Alessia Scire, Dieter Kaiser, Tarja Hauck, Frank Zschorlich