Abstract: According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

Abstract: A semiconductor device may include a substrate, conductive patterns stacked to be spaced apart from each other on the substrate, contact plugs coming in contact with the respective conductive patterns, and first and second slit insulating layers of a first group penetrating the conductive patterns. The substrate may include a cell area and a contact area extending along a first direction from the cell area. The conductive patterns may be form a step structure. The first slit insulating layers of the first group may be opposite to each other in a second direction with any one of the contact plugs, interposed therebetween. The second slit insulating layers of the first group, which extend along the first direction in the contact area, may be opposite to each other in the second direction with the first slit insulating layers of the first group and the contact plugs, interposed therebetween.

Abstract: A method is disclosed for fabricating a semiconductor circuit. A semiconductor substrate is provided. A first semiconductor device is fabricated including a first semiconductor material on the substrate and forming an insulating layer including a cavity structure on the first semiconductor device. The cavity structure includes at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure including a second semiconductor material different from the first semiconductor material in the growth channel, forming a semiconductor starting structure for a second semiconductor device from the filling structure, and fabricating a second semiconductor device including the starting structure. Corresponding semiconductor circuits are also disclosed.

Abstract: An array substrate and a display device are provided, and the array substrate, comprising: a substrate; and gate lines (2) and data lines (1), formed on the substrate and configured to defining pixel units, wherein, each data line (1) is located in a middle part of a corresponding pixel unit and configured to dividing each pixel unit into a first sub-pixel unit (7) and a second sub-pixel unit (8), wherein the first sub-pixel unit (7) is connected to one thin film transistor (6) and the second sub-pixel unit (8) is connected to one thin film transistor (6) for independent charging, and the thin film transistors (6) are located in a region corresponding to the corresponding gate line. The data line (1) is arranged in the middle of the corresponding pixel unit, and the first sub-pixel unit (7) and the second sub-pixel unit (8) are connected to two individual thin film transistors (6) to be independently charged, a width of the gate line can be greatly reduced, and the aperture ratio of the pixel can be improved.

Abstract: A TFT array substrate having compensated gate signal delays is disclosed. The TFT array substrate includes a plurality of gate lines, a plurality of data lines insulatedly intersecting with the plurality of the gate lines, and a plurality of TFT switches, each of which is connected with one of the gate lines and one of the data lines. The TFT array substrate also includes a plurality of driving units, where the driving units are located at both ends of the gate lines, and each of the driving units is connected with at least one gate line to drive the TFT switches connected to the at least one gate line.

Abstract: A display panel is provided. The display panel includes has an active area and a border area surrounding the active area. The display panel includes a plurality of pixels, a plurality of multiplexer portion, a gate driver portion and a source routing portion. The pixels are located in the active area. The multiplexer portion is located in the border area. The gate driver portion is located in the border area. The source routing portion is located in the border area. In part of the border area, at least part of the multiplexer portion, at least part of the gate driver portion and at least part of the source routing portion are located and sequentially arranged from an internal edge of the border area to an external edge of the border area.

Abstract: An array substrate includes: a gate wiring; a source wiring, which is formed to intersect the gate wiring; a passivation film, which covers the source wiring; and a pixel electrode that is formed on the passivation film. The array substrate has a display area and a dummy pixel area. In the display area, a switching element in the vicinity of the intersection of the gate wiring and the source wiring is provided. In the display area, the pixel electrode and the source wiring do not have an overlapping area in a top view. The dummy pixel area is located outside the display area, and in the dummy pixel area, a dummy pixel electrode and two source wirings, which are adjacent to the dummy pixel electrode have an overlapping area in a top view.

Abstract: To improve productivity of a transistor that includes an oxide semiconductor and has good electrical characteristics. In a top-gate transistor including a gate insulating film and a gate electrode over an oxide semiconductor film, a metal film is formed over the oxide semiconductor film, oxygen is added to the metal film to form a metal oxide film, and the metal oxide film is used as a gate insulating film. After an oxide insulating film is formed over the oxide semiconductor film, a metal film may be formed over the oxide insulating film. Oxygen is added to the metal film to form a metal oxide film and added also to the oxide semiconductor film or the oxide insulating film.

Abstract: A TFT substrate and the manufacturing method thereof are disclosed. The method includes: providing a substrate; forming a gate electrode on the substrate; forming a first insulation layer and an active layer on the gate electrode in turn; forming a first black matrix on the active layer; forming a source electrode and a drain electrode on the first black matrix; forming a second insulation layer on the source electrode and the drain electrode; and forming a pixel electrode on the second insulation layer. The pixel electrode is electrically connected to the source electrode or the drain electrode via the second insulation layer. In this way, the masking effect of the display panel assembled by the TFT substrate can be ensured. In addition, the coupling capacitance between the data line and the scanning line may be reduced.

Abstract: The organic insulating film has an opening through which the drain electrode is partially exposed. The opening has a side wall extending from above the drain electrode. The pixel electrode has a contact portion that is in contact with the drain electrode in the opening of the organic insulating film, a wiring portion that extends directly on the side wall of the organic insulating film from the contact portion, and a body portion that is linked to the wiring portion and is located on the organic insulating film. The interlayer insulating film covers the pixel electrode. The interlayer insulating film covers the source electrode and directly covers the semiconductor film between the source-electrode side surface and the drain-electrode side surface. The common electrode has fringes opposed to the pixel electrode via the interlayer insulating film.

Abstract: A manufacturing method of a thin film transistor comprises: sequentially forming a pattern of gate, a gate insulation layer film, an active layer film and an ohmic contact layer film, a first etching resist module within a channel region to be formed, and a source and drain metallic layer film on a substrate; forming a pattern comprising the source and drain by wet etching process by shielding the active layer film and the ohmic contact layer film positioned within the channel region to be formed, by use of the first etching resist module; and forming a pattern comprising the ohmic contact layer and the active layer by dry etching process. A thin film transistor, an array substrate comprising the thin film transistor and a display device comprising the array substrate are also disclosed.

Abstract: A radiation image-pickup device includes: a drive substrate including a transistor used to read, from each of a plurality of pixels, signal charge based on radiation; a charge collection electrode provided on the drive substrate, for each of the pixels; a conversion layer formed on the charge collection electrode, and configured to generate the signal charge by absorbing radiation; a counter electrode provided on the conversion layer; and a first conductive film disposed, between the drive substrate and the charge collection electrode, to face at least a part of the charge collection electrode, and included in a first capacitive element configured to retain the signal charge.

Abstract: An image-sensor structure is provided. The image-sensor structure includes a substrate, a plurality of photoelectric conversion units formed in the substrate, and a plurality of color filter patterns including a red filter pattern having a first refractive index, a green filter pattern having a second refractive index and a blue filter pattern having a third refractive index formed above the substrate and the photoelectric conversion units, wherein at least one color filter pattern contains a component having a specific refractive index such that the second refractive index of the green filter pattern is higher than the first refractive index of the red filter pattern and the third refractive index of the blue filter pattern.

Abstract: Image sensors are provided including a substrate defining a plurality of pixel regions, the substrate having a first surface and a second surface opposite the first surface. The second surface of the substrate is configured to receive light incident thereon and the substrate defines a deep trench extending from the second surface of the substrate toward the first surface substrate and separating the plurality of pixel regions from each other. In each of the plurality of pixel regions of the substrate, a photoelectric conversion region is provided. A gate electrode is provided on the photoelectric conversion region and a negative fixed charge layer covering the second surface of the substrate and at least a portion of a sidewall of the deep trench is also provided. The image sensors further include a shallow device isolation layer on the first surface of the substrate.

Abstract: An imaging system may be formed from multiple stacked wafers. A first wafer may include backside illuminated photodiodes, floating diffusion regions, and charge transfer gate structures. The first wafer may be bonded to a second wafer that includes pixel trunk transistors such as reset transistors, source-follower transistors, row-select transistors and associated logic circuits. The pixel trunk transistors may be formed using bottom-gate thin-body transistors. The first and second wafers may share the same backend metallization layers. The second wafer may further be bonded to a third wafer that includes digital signal processing circuits. The digital signal processing circuits may also be implemented using bottom-gate thin-body transistors. Additional metallization layers may be formed over the third wafer. The first, second, and third wafers may be fabricated using the same or different technology nodes.

Abstract: The present technology relates to a solid-state imaging apparatus, a manufacturing method therefor, and an electronic apparatus by which fine pixel signals can be suitably generated. A charge accumulation section that is formed on a first semiconductor substrate and accumulates photoelectrically converted charges, a charge-retaining section that is formed on a second semiconductor substrate and retains charges accumulated in the charge accumulation section, and a transfer transistor that is formed on the first semiconductor substrate and the second semiconductor substrate and transfers charges accumulated in the charge accumulation section to the charge-retaining section are provided. A bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the transfer transistor.

Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.

Abstract: A solid-state imaging device having a backside illuminated structure, includes: a pixel region in which pixels each having a photoelectric conversion portion and a plurality of pixel transistors are arranged in a two-dimensional matrix; an element isolation region isolating the pixels which is provided in the pixel region and which includes a semiconductor layer provided in a trench by an epitaxial growth; and a light receiving surface at a rear surface side of a semiconductor substrate which is opposite to a multilayer wiring layer.

Abstract: A semiconductor structure for back side illumination (BSI) pixel sensors is provided. Photodiodes are arranged within a semiconductor substrate. A metal grid overlies the semiconductor substrate and is made up of metal grid segments that surround outer perimeters of the photodiodes, respectively, such that first openings within the metal grid overlie the photodiodes, respectively. A low-n grid is made up of low-n grid segments that surround the respective outer perimeters of the photodiodes, respectively, such that second openings within the low-n grid overlie the photodiodes, respectively. Color filters are arranged in the first and second openings of the photodiodes and have a refractive index greater than a refractive index of the low-n grid. A substrate isolation grid extends into the semiconductor substrate and is made up of isolation grid segments that surround outer perimeters of the photodiodes, respectively. A method for manufacturing the BSI pixel sensors is also provided.

Abstract: An image sensor including a color filter array layer, which includes a plurality of color filters transmitting light of different colors; and reflective partitioning walls, which define the color filters and have a lower refractive index than that of the color filters; a color separation device, which separates incident light into a plurality of colors, such that the plurality colors are incident on the plurality of color filters, respectively; and a sensor substrate, on which a plurality of light detection devices for respectively sensing light transmitted through the plurality of color filters are arranged in an array shape.

Abstract: A method of image sensor fabrication includes forming a layer of dielectric material, a layer of gate material, and a layer of hard mask material. The layer of dielectric material is disposed between the layer of gate material and a semiconductor material, and the layer of gate material is disposed between the layer of hard mask material and the layer of dielectric material. The method also includes etching the layer of hard mask material and layer of gate material, and etching forms a transfer gate from the layer of gate material. An encapsulation material is deposited proximate to a surface of the semiconductor material. Trenches are etched in the encapsulation material. A first trench extends through the encapsulation material and the layer of dielectric material, and a second trench extends through the encapsulation material and the layer of hard mask material.

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures.

Abstract: There is provided a light emitting device which enables a color display with good color balance. A triplet compound is used for a light emitting layer of an EL element that emits red color, and a singlet compound is used for a light emitting layer of an EL element that emits green color and a light emitting layer of an EL element that emits blue color. Thus, an operation voltage of the EL element emitting red color may be made the same as the EL element emitting green color and the EL element emitting blue color. Accordingly, the color display with good color balance can be realized.

Abstract: Display of a display device is made less likely to appear divided when a plurality of display panels are used as one screen. Provided is a display device including two display units and a foldable housing that includes a joint portion between the two display units and supports the two display units. Each display unit includes a display panel including a display region and a non-display region and a support having a first surface overlapped with the display region and a second surface that meets the first surface and is overlapped with the non-display region. The two display units are placed in the housing in an opened state such that the first surfaces of the supports face the same direction and the second surfaces of the supports face each other.

Abstract: A method of manufacturing a thin film transistor (TFT) substrate in which a TFT including an oxide semiconductor layer is formed, the method including: forming an insulating layer to cover the oxide semiconductor layer; and forming an opening in the insulating layer, wherein the insulating layer includes a first film, a second film which is provided above the first film and is an aluminum oxide film, and a third film which is provided above the second film and is a film including silicon, and the forming of an opening includes: forming a resist pattern above the third film; processing the third film by dry etching; and processing the second film by wet etching.

Abstract: A display device includes: a substrate; a plurality of light-emission elements arranged, on the substrate, in a first direction and a second direction intersecting each other, each of the light-emission elements having a first electrode layer, an organic layer including a luminous layer, and a second electrode layer which are laminated in that order; and a separation section disposed, on the substrate, between the light-emission elements adjacent to each other in the first direction, the separation section having two or more pairs of steps. The first electrode layers in the light-emission elements are separated from each other, and the organic layers as well as the second electrode layers in the light-emission elements adjacent to each other in the first direction are separated from each other by the steps included in the separation section.

Abstract: An organic light emitting display device comprises a common voltage line formed over a peripheral region of a substrate; a passivation layer formed over a pixel region of the substrate and the peripheral region; pixel electrodes formed over the pixel region; and a pixel defining layer formed over the pixel region and the peripheral region. The pixel defining layer defines pixel openings overlapping the pixel electrodes, respectively. The device further comprises organic light emitting layers formed over the pixel region, and disposed in the pixel openings and over the pixel electrodes, respectively; and a common electrode formed over the pixel and peripheral regions. The common electrode is disposed over the pixel defining layer and the organic light emitting layers. The common electrode contacts the common voltage line. The passivation layer comprises a portion overlapping the common voltage line but not overlapping the pixel defining layer.

Abstract: A flexible display device includes a substrate, a plurality of first pixels, and a plurality of second pixels. The substrate includes a foldable bending region and a non-foldable non-bending region. Each first pixel is disposed on the bending region. Each first pixel is spaced apart from an adjacent first pixel by a first distance. Each second pixel is disposed on the non-bending region. Each second pixel is spaced apart from an adjacent second pixel by a second distance. The first distance is greater than the second distance.

Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.

Abstract: A flexible display includes a driving circuit to drive a light emitting device. The driving circuit includes a thin film transistor which includes a column-shaped gate electrode extending in a first direction, a gate insulating layer enclosing an outer surface of the gate electrode, a semiconductor layer on an outer surface of the gate insulating layer, and first and second conductive layers enclosing first and second areas of the semiconductor layer, respectively.

Abstract: A method of fabricating an organic light emitting display device is discussed. The method in one example includes: sequentially forming a first metal film and a second metal film on a substrate and performing a mask procedure for the first and second metal films, to form a gate electrode, a first storage electrode and a pad in a thin film transistor region, a storage capacitor region and a pad region; forming a gate insulation film on the substrate provided with the gate electrode; forming a third storage electrode which overlaps the second storage electrode with a passivation film therebetween and is connected to the drain electrode; forming red, green and blue color filters in respective pixel regions of the substrate; and forming an organic light emitting diode on the substrate provided with the color filter.

Abstract: The subject technology relates to a method including steps for disposing a first electrically conductive material on a substrate to form a first layer of electrodes on the substrate, wherein the first layer includes a source electrode and a drain electrode, and printing a film including carbon nanotubes between the source electrode and the drain electrode, thereby defining at least a first interface between the carbon nanotube film and the source electrode and a second interface between the carbon nanotube film and drain electrode. In certain aspects, the method can further include steps for disposing a second electrically conductive material over the first interface between the carbon nanotube film and the source electrode and the second interface between the carbon nanotube film and the drain electrode. In certain aspects, a transistor device is also provided.

Abstract: A display device includes a pixel section that includes a plurality of pixels each of which has a display element and which are disposed in a two-dimensional manner, and a driving circuit section that drives the plurality of pixels in order to perform display, in which a first floor including the driving circuit section and a second floor including the pixel section are laminated.

Abstract: A display device comprises a base substrate, a first metal layer formed over the base substrate, an interlayer insulating layer formed over the first metal layer and comprising a contact hole, a second metal layer formed over the interlayer insulating layer and connected with the first metal layer through the contact hole, an anisotropic conductive film formed over the second metal layer and covering the contact hole, and a flexible circuit board attached to the anisotropic conductive film and configured to transmit a driving signal for the array of pixels. The first metal layer comprises a molten portion formed in the non-display area.

Abstract: Embodiments of the present invention provide improved metal-insulator-metal (MIM) capacitors. In embodiments, series resistance is reduced by forming a via underneath the bottom plate of a MIM capacitor, leading to a metallization layer or intermediate metal sublayer. In embodiments, the MIM capacitor is formed with a corrugated shape to increase the plate surface area, allowing a thicker dielectric to be used, thereby mitigating leakage issues.

Abstract: A switch driving circuit electrically opens and closes a switch circuit including two N-channel type semiconductor switching elements series connected in a reverse direction, thereby electrically opening and closing a path between a DC power supply and an inverter circuit. The switch driving circuit has a reference potential point in common with the inverter circuit and supplies an opening/closing control signal to the switch circuit. The switch driving circuit includes a half bridge circuit including two semiconductor switching elements series connected between a driving power supply and the reference potential point. Two protection diodes are connected in parallel to the semiconductor switching elements respectively. At least one current blocking diode is configured to block current from flowing from the reference potential point through the diode to the switch circuit side when the DC power supply is connected to the inverter circuit in reverse polarity.

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a first channel region and a second channel region that are formed according to at least one of a vertical channel configuration or a dual channel configuration. The first channel region operates as a first channel between a source region and a drain region of the semiconductor arrangement. The second channel region operates as a second channel between the source region and the drain region. A gate region, formed between the first channel region and the second channel region, operates to control the first channel and the second channel. Performance of the semiconductor arrangement is improved, such as an increase in current, because two current paths between the source region and the drain region are provided by the two channels.

Abstract: A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.

Abstract: A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.

Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include forming a modulation doped heterostructure, comprising forming an active portion having a first bandgap and forming a delta doped portion having a second bandgap.

Abstract: According to one embodiment, a semiconductor device includes an n-type semiconductor layer, a first electrode, and a nitride semiconductor layer. The n-type semiconductor layer includes diamond. The nitride semiconductor layer is provided between the n-type semiconductor layer and the first electrode. The nitride semiconductor layer includes AlxGa1?xN (0?x?1) and is of n-type.

Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

Abstract: Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

Abstract: A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region.

Abstract: A semiconductor device includes a semiconductor body with parallel first and second surfaces and containing hydrogen-related donors. A concentration profile of the hydrogen-related donors vertical to the first surface includes a maximum value of at least 1E15 cm?3 at a first distance to the first surface and does not fall below 1E14 cm?3 over at least 60% of an interval between the first surface and the first distance.

Abstract: A substrate is treated by means of at least one pulse of a luminous flux of determined wavelength. The substrate comprises an embedded layer that absorbs the luminous flux independently of the temperature. The embedded layer is interleaved between a first treatment layer and a second treatment layer. The first treatment layer has a coefficient of absorption of luminous flux that is low at ambient temperature and rises as the temperature rises. The luminous flux may be applied in several places of a surface of the first layer to heat regions of the embedded layer and generate a propagating thermal front in the first layer opposite the heated regions of the embedded layer, which generate constraints within the second layer.

Abstract: A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.

Abstract: According to an exemplary implementation, a transistor includes drain finger electrodes interdigitated with source finger electrodes. The transistor also includes a current conduction path in a semiconductor substrate between the drain finger electrodes and the source finger electrodes. At least one of the drain finger electrodes has a drain finger electrode end and a drain finger electrode main body, where the drain finger electrode main body is non-coplaner with at least a portion of the drain finger electrode end. The transistor may also include a dielectric material situated between at least a portion of the drain finger electrode end and the semiconductor substrate. The dielectric material can be an increasing thickness dielectric material. The dielectric material can thus elevate the drain finger electrode end over the semiconductor substrate. Further, the drain finger electrode end can have an increased radius of curvature.

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.