Abstract: In various embodiments, joined sputtering targets are formed at least in part by spray deposition of the sputtering material and/or welding.

Abstract: A system that has a plate with a holder, in which the plate is centered in the holder both at room temperatures and at higher temperatures, independently of the thermal expansion of the plate and the holder, and in which the plate can freely expand in the holder at higher temperatures.

Abstract: A control system and method of determining a signal to noise (S/N) ratio of an ion detector system, including an ion detector, electron multiplier or photomultiplier, operates by determining an area of a noise peak, determining an area of a signal peak and determining a ratio of the area of the signal peak to the area of the noise peak. Based thereon, the signal to noise ratio can be optimized. The system has particular applicability for use in mass spectrometry.

Abstract: Methods and systems for performing mass spectrometry are provided herein. In accordance with various aspects of the applicants' teachings, the methods and systems can utilize an ion mobility spectrometer operating at atmospheric or low-vacuum pressure to remove the major contributors to the contamination and degradation of critical downstream components of a mass spectrometer located within a high-vacuum system (e.g., ion optics, mass filters, detectors), with limited signal loss.

Abstract: The invention relates to a low-cost spring steel plate as the sample support on a dimensionally stable and precisely shaped substructure, machined from an aluminum alloy, for example, and using a pattern of embedded magnets so that said plate is removable and that a body is created overall which is suitable for use in robots, for example by giving it the dimensions of a conventional microtitration plate. The planarity of the surface onto which the (organic) samples are applied is provided within the near region by the spring steel plate itself and in the far region over the whole spring steel plate by the substructure. The spring steel plate may be designed for single use in order to satisfy IVD diagnostic regulations also, for example. It can be equipped with identification codes, sample site markings and pre-coatings for different types of analytical tasks, such as MALDI-TOF mass spectrometric analysis.

Abstract: In one aspect of the invention, an ion trap mass analyzer includes a variable- or multi-potential type ion guide (MPIG) assembly which has been pre-configured to produce a parabolic-type potential field. Each MPIG electrode has a resistive coating of designed characteristics. In one example the coating varies in thickness along the length of an underlying uniform substrate. The MPIG assembly can be a single MPIG electrode or an array of a plurality of MPIG electrodes. An array can facilitate delocalization for improved performance. This chemical modification of a uniform underlying substrate promotes cheaper and flexible instruments. The modified MPIG electrodes also allow miniaturization (e.g. micro and perhaps even nano-scale), which allows miniaturization of the instrument in which the single or plural modified MPIG electrode(s) are placed. This promotes portability and field use instead of limitation to laboratory settings.

Abstract: A sample inlet device and methods for use of the sample inlet device are described that include an ion funnel having a plurality of electrodes with apertures arranged about an axis extending from an inlet of the ion funnel to an outlet of the ion funnel, the ion funnel including a plurality of spacer elements disposed coaxially with the plurality of electrodes, each of the plurality of spacer elements being positioned between one or two adjacent electrodes, each of the plurality of spacer elements having an aperture with a diameter that is greater than a diameter of each adjacent electrode. The ion funnel is configured to pass an ion sample through the apertures of the electrodes and the spacer elements to additional portions of a detection system, such as to a mass analyzer system and detector.

Abstract: The present invention relates to a compact and portable mass spectrometer device comprising a source of ions, a non-scanning magnetic sector for separating ions originating at the source of ions according to their mass-to-charge ratios, and a detection means. The magnetic sector comprises an ion entrance plane and at least two ion exit planes, which allow to optimize the resolving power of the mass spectrometer for specific mass-to charge ratio sub-ranges.

Abstract: A charged particle analyzer apparatus comprising two opposing ion mirrors each mirror comprising inner and outer field-defining electrode systems elongated along an axis z, the outer system surrounding the inner, whereby when the electrode systems are electrically biased the mirrors create an electrical field comprising opposing electrical fields along z; and at least one arcuate focusing lens for constraining the arcuate divergence of a beam of charged particles within the analyzer while the beam orbits around the axis z, the analyzer further comprising a disc having two faces at least partly spanning the space between the inner and outer field defining electrode systems and lying in a plane perpendicular to the axis z, the disc having resistive coating upon both faces. A mass spectrometer system comprising a plurality of the charged particle analyzers arranged as a parallel array.

Abstract: The embodiments provide apparatus and methods for removal of etch byproducts, dielectric films and metal films near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a substrate support configured to receive the substrate. The plasma processing chamber also includes a bottom edge electrode surrounding the substrate support. The bottom edge electrode and the substrate support are electrically isolated from one another by a bottom dielectric ring. A surface of the bottom edge electrode facing the substrate is covered by a bottom thin dielectric layer. The plasma processing chamber further includes a top edge electrode surrounding a top insulator plate opposing the substrate support. The top edge electrode is electrically grounded.

Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).

Abstract: A method for the formation of a MIM capacitor on a substrate is described. Initially, a target comprising a metal is sputtered in the presence of nitrogen to form at least a portion of a bottom electrode. Next, the target is further sputtered in the presence of oxygen to form at least a part of an insulator. Finally, the target is even further sputtered in the presence of nitrogen to form a portion of a top electrode. The insulator is sandwiched between the bottom electrode and the top electrode. The formation of the bottom electrode, the insulator, and the top electrode is performed in a sputter deposition chamber without removing the substrate therefrom.

Abstract: A method of depositing a thin film includes: repeating a first gas supply cycle a first plurality of times, the first gas supply cycle including supplying a source gas to a reaction space; supplying first plasma while supplying a reactant gas to the reaction space; repeating a second gas supply cycle a second plurality of times, the second gas supply cycle including supplying the source gas to the reaction space; and supplying second plasma while supplying the reactant gas to the reaction space, wherein the supplying of the first plasma includes supplying remote plasma, and the supplying of the second plasma includes supplying direct plasma.

Abstract: Methods of selectively inhibiting deposition of silicon-containing films deposited by atomic layer deposition are provided. Selective inhibition involves exposure of an adsorbed layer of a silicon-containing precursor to a hydrogen-containing inhibitor, and in some instances, prior to exposure of the adsorbed layer to a second reactant. Exposure to a hydrogen-containing inhibitor may be performed with a plasma, and methods are suitable for selective inhibition in thermal or plasma enhanced atomic layer deposition of silicon-containing films.

Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.

Abstract: A manufacturing method for manufacturing a silicon carbide epitaxial wafer includes: introducing a cleaning gas into a growth furnace to remove dendrite-like polycrystal of silicon carbide attached to an inner wall of the growth furnace; after introducing the cleaning gas, bringing a silicon carbide substrate in the growth furnace; and growing a silicon carbide epitaxial layer on the silicon carbide substrate by introducing a processing gas into the growth furnace to manufacture a silicon carbide epitaxial wafer, wherein the cleaning gas having fluid energy of 1.6E-4 [J] or higher is introduced into the growth furnace.

Abstract: A method of manufacturing a semiconductor device, includes forming an aluminum compound film on a surface of a process chamber by supplying an aluminum (Al) source to the process chamber, the surface contacting the aluminum source in the process chamber; disposing a wafer on a susceptor provided in the process chamber after forming the aluminum compound film; and forming a thin film for the semiconductor device on the wafer.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first material layer over a substrate. The first material layer has a sidewall defining a first opening, wherein the first opening has a first shape. The method also includes forming a sacrificial feature within the first opening and the sacrificial feature has a second shape, which is different than the first shape such that there is a cavity between an edge of the sacrificial feature and the sidewall of the first material layer. The method also includes filling in cavity with a second material layer, removing the sacrificial feature to form a second opening, filling in the second opening with a third material layer, removing the second material layer to reveal the cavity and forming a conductive feature within the cavity.

Abstract: Provided is a method of manufacturing a nanowire array using induced growth, in which a nitride inorganic nanowire is grown from a nitride seed by forming the nitride seed on a sapphire or silicon substrate, forming an organic nanowire pattern and a dielectric nanotunnel using the nanowire pattern as a template on the nitride seed, and using the nanotunnel as an induced growth mask.

Abstract: A method of fabricating a transient semiconductor based on a single-wall nanotube includes stacking a thermal oxide layer on a silicon substrate and depositing a nickel thin layer on the thermal oxide layer, depositing an oxide layer on the nickel thin layer, depositing a metallic layer on the oxide layer, and patterning the metallic layer to form a gate electrode, depositing a gate insulating layer on the gate electrode, changing a surface of the gate insulating layer into a hydrophilic surface, and washing and drying the gate insulting layer, coating a single-wall nanotube on the hydrophilic surface of the gate insulating layer, forming source and drain electrodes by forming a contact opening with respect to the gate insulating layer, attaching a thermal release tape after removing a surrounding single-wall nanotube, performing a transfer onto a polyvinyl alcohol thin layer after etching the nickel thin layer, and releasing the thermal release.

Abstract: Techniques for processing materials in supercritical fluids including processing in a capsule disposed within a high-pressure apparatus enclosure are disclosed. The disclosed techniques are useful for growing crystals of GaN, AlN, InN, and their alloys, including InGaN, AlGaN, and AlInGaN for the manufacture of bulk or patterned substrates, which in turn can be used to make optoelectronic devices, lasers, light emitting diodes, solar cells, photoelectrochemical water splitting and hydrogen generation devices, photodetectors, integrated circuits, and transistors.

Abstract: A cyclic deposition and etch method is provided. The method includes depositing an epitaxial layer over a substrate at a first temperature and etching a portion of the deposited epitaxial layer at a variable temperature higher than the first temperature. The step of etching is performed while varying the temperature.

Abstract: A method of excimer laser annealing includes generating a focused long line beam with a laser beam output from at least one laser source; and scanning the long line beam in a direction perpendicular to a long axis of the long line beam along a surface of an amorphous semiconductor film on a substrate. The long line beam has a normalized beam angular divergence half-width ?=arctan(tan ?y/sin ?) that is less than a critical value ?c, where ?y represents a beam angular divergence half-width measured along the long axis of the long line beam on the surface of the amorphous semiconductor film, ? represents a mean incidence angle of the long line beam on the surface of the amorphous semiconductor film, and ?c is approximately 30°.

Abstract: If an optical path length of an optical system is reduced and a length of a laser light on an irradiation surface is increased, there occurs curvature of field which is a phenomenon that a convergent position deviates depending on an incident angle or incident position of a laser light with respect to a lens. To avoid this phenomenon, an optical element having a negative power such as a concave lens or a concave cylindrical lens is inserted to regulate the optical path length of the laser light and a convergent position is made coincident with a irradiation surface to form an image on the irradiation surface.

Abstract: The inventive concepts provide methods of forming a pattern. In the method, a block copolymer layer may be formed on a neutral layer having an uneven structure and then phase separation is induced. The neutral layer may have an affinity for all of a hydrophilic polymer and a hydrophobic polymer, so that vertical cultivation of phases of the block copolymer may be realized on the uneven structure. Thus, a self-assembled phenomenon may be induced.

Abstract: A method for fabricating a semiconductor device is provided. In the method, a first hard mask layer is formed on a stepped structure. The first hard mask layer has a level top surface and thickness sufficient to etch the structure. A second hard mask pattern is formed on the first hard mask layer. The first hard mask layer is etched using the second hard mask pattern. Size dispersion of the patterns may be reduced by the first hard mask layer.

Abstract: A method of forming a semiconductor structure by; forming a first mask trench in a first mask, where the first mask is on a substrate; forming a second mask in the first mask trench; and forming a third mask between the first mask and the second mask by reacting the first mask with the second mask, where the first mask, the second mask, and the third mask all have different etching properties and the third mask is a combination of the first mask and the second mask.

Abstract: One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed.

Abstract: The method for fabricating patterns made from first material having: providing a substrate covered by a covering layer, forming a first mask by means of a self-assembled structure of block copolymers, the first mask having first patterns, making a second mask from the first mask, the second mask having a second series of patterns organized according to the first repetition pitch or an integral multiple of the first repetition pitch, the second series having less patterns than the first series, depositing and exposing a resin layer to form an intermediate mask on the first mask, the intermediate mask covering a part of the first patterns formed in the first mask and having second holes facing the first holes, etching the covering layer through the facing first and second holes to form third holes, filling the third holes with a first material to form the patterns made from first material.

Abstract: A composite dielectric structure having one or more Leakage Blocking Layers (LBL) interleaved with one or more Laminate Dielectric Layers (LDL), Alloy Dielectric Layers (ADL), or Co-deposit Dielectric Layers (CDL). Each LDL, ADL, and CDL includes dopants incorporated in a respective base dielectric layer (BDL); where LDLs are formed by incorporating a doping layer into a BDL using a laminate method, ADLs are formed by incorporating a dopant into a BDL using an alloying method; and CDLs are formed by pulsing a BDL base material and a dopant together using a co-deposit method.

Abstract: The present disclosure relates to an enhancement mode MISFET device. In some embodiments, the MISFET device has an electron supply layer located on top of a layer of semiconductor material. A multi-dielectric layer, having two or more stacked dielectric materials sharing an interface having negative fixed charges, is disposed above the electron supply layer. A metal gate structure is disposed above the multi-dielectric layer, such that the metal gate structure is separated from the electron supply layer by the multi-dielectric layer. The multi-dielectric layer provides fixed charges at interfaces between the separate dielectric materials, which cause the transistor device to achieve a normally off disposition.

Abstract: A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the metal gate stack includes a metal gate electrode. The semiconductor device further includes a metal oxide structure formed over the insulating layer and in direct contact with the insulating layer. The metal oxide structure includes an oxidized material of the metal gate electrode.

Abstract: A subject matter of the invention is a process for the formation of nickel silicide or of cobalt silicide, comprising the stages consisting in: exposing the surface of the silicon-comprising substrate with an aqueous solution comprising from 0.1 mM to 10 mM of gold ions and from 0.6 M to 3.0 M of fluorine ions for a duration of between 5 seconds and 5 minutes, depositing by an electroless route, on the activated substrate, a layer essentially composed of nickel or of cobalt, applying a rapid thermal annealing at a temperature of between 300° C. and 750° C., so as to form the nickel silicide or the cobalt silicide. The aqueous solution comprises a surface-active agent chosen from the compounds comprising at least one anionic or nonionic polar group and an alkyl chain comprising from 10 to 16 carbon atoms. This process essentially has applications in the manufacture of NAND memories and photovoltaic cells.

Abstract: A method of manufacturing a semiconductor device includes forming a device structure in a surface of a semiconductor substrate, forming, in a face of the semiconductor substrate, a transition metal layer that contacts the semiconductor substrate, and exposing the semiconductor substrate having the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves to cause the transition metal layer to generate heat. During exposure of the semiconductor substrate to the hydrogen plasma atmosphere, a portion of the semiconductor substrate contacting the transition metal layer is heated by a transfer of the heat from the transition metal layer, and an ohmic contact is formed at an interface of the transition metal layer and the semiconductor substrate by reaction of the transition metal layer and the semiconductor substrate. When the semiconductor substrate is silicon carbide, the ohmic contact is composed of a silicide, such as a transition metal silicide.

Abstract: Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.

Abstract: An embodiment of a NOR Flash device manufacturing method includes: providing a substrate having a first polycrystalline silicon layer disposed thereon; forming a first hard mask layer on the first polycrystalline silicon layer; etching the first hard mask layer to form a first opening, and cleaning a gas pipeline connected to an etching cavity before etching the first hard mask layer; forming a second hard mask layer on the first hard mask layer, and the second hard mask layer covers the bottom and side wall of the first opening; etching the second hard mask layer to form a second opening, the width of the second opening is smaller than the width of the first opening; etching the first polycrystalline silicon, forming a floating gate. The NOR Flash device manufacturing method improves the yield of the NOR Flash device.

Abstract: Provided is a polishing liquid including cerium oxide particles, an organic acid A, a polymer compound B having a carboxyl acid group or a carboxylate group, and water, wherein the organic acid A has at least one group selected from the group consisting of —COOM group, -Ph-OM group, —SO3M group and —PO3M2 group, pKa of the organic acid A is less than 9, a content of the organic acid A is 0.001 to 1 mass % with respect to the total mass of the polishing liquid, and a content of the polymer compound B is 0.01 to 0.50 mass % with respect to the total mass of the polishing liquid, and pH is in the range of 4.0 to 7.0.

Abstract: A method of etching exposed silicon on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a hydrogen-containing precursor. The combination reacts with the patterned heterogeneous structures to remove an exposed silicon portion faster than a second exposed portion. The silicon selectivity results from the presence of an ion suppressor positioned between the remote plasma and the substrate processing region. The methods may be used to selectively remove silicon faster than silicon oxide, silicon nitride and a variety of metal-containing materials. The methods may be used to remove small etch amounts in a controlled manner and may result in an extremely smooth silicon surface.

Abstract: Method of forming a protective hard mask layer on a substrate in a semiconductor etch process, comprising the step of applying by solution deposition on the substrate a solution or colloidal dispersion of an alumina polymer, said solution or dispersion being obtained by hydrolysis and condensation of monomers of at least one aluminum oxide precursor in a solvent or a solvent mixture in the presence of water and a catalyst. The invention can be used for making a hard mask in a TSV process to form a high aspect ratio via a structure on a semiconductor substrate.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of active fins over a semiconductor substrate, sequentially forming first and second hard mask layers over the active fins, forming a first hard mask pattern by etching the second hard mask layer, trimming the first hard mask pattern to form a trimmed hard mask pattern, forming a first photo resist pattern over the first hard mask layer, forming second hard mask patterns by etching the first hard mask layer by using the trimmed hard mask pattern and the first photo resist pattern as an etching mask, and forming active fin patterns by etching the active fins by using the second hard mask patterns as an etching mask.

Abstract: A method of etching silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using anhydrous vapor-phase HF. The HF is combined with an additional precursor in the substrate processing region. The HF may enter through one channel(s) and the additional precursor may flow through another channel(s) prior to forming the combination. The combination may be formed near the substrate. The silicon oxide etch selectivity relative to silicon nitride from is selectable from about one to several hundred. In all cases, the etch rate of exposed silicon, if present, is negligible. No precursors are excited in any plasma either outside or inside the substrate processing region according to embodiments. The additional precursor may be a nitrogen-and-hydrogen-containing precursor such as ammonia.

Abstract: Embodiments of the invention describe a method for controlling etching in pitch doubling. According to one embodiment, the method includes receiving a substrate having a pattern thereon defined by spacers formed on sidewalls of a plurality mandrels, and transferring the pattern defined by the spacers into the substrate using a plasma etch process that etches the mandrels and the substrate, the transferring forming first recessed features in the substrate below the mandrels and second recessed features in the substrate between the mandrels, where the plasma etch process utilizes an etching gas containing O2 gas, and the relative amount of O2 gas in the etching gas is selected to control the depth of the first recessed features relative to the depth of second recessed features. According to another embodiment, the substrate contains a mask layer thereon and a pattern on the mask layer.

Abstract: A substrate having an insulating layer including an oxide is loaded into a chamber, and at least a part of the insulating layer is removed by injecting a process gas including an etching source gas into the chamber. The removal process is performed in a pulse type in which a first period and a second period are repeated a plurality of times. The etching source gas is supplied at a first flow rate during the first period and is supplied at a second flow rate less than the first flow rate during the second period. A temperature of the inside of the chamber remains at 100° C. or more during the removal process.

Abstract: Improved methods for stripping photoresist and removing ion implant related residues from a work piece surface are provided. According to various embodiments, plasma is generated using elemental hydrogen, a fluorine-containing gas and a protectant gas. The plasma-activated gases reacts with the high-dose implant resist, removing both the crust and bulk resist layers, while simultaneously protecting exposed portions of the work piece surface. The work piece surface is substantially residue free with low silicon loss.

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a polymeric material disposed over the semiconductor substrate and surrounding the conductor. The semiconductor device also includes an electric conductive layer between the conductor and the polymeric material. In the semiconductor device, an adhesion strength between the electric conductive layer and the polymeric material is greater than an adhesion strength between the polymeric material and the conductor.

Abstract: A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.

Abstract: A liquid processing apparatus including: a second housing; a first housing capable of being brought into contact with the second housing; a holding part configured to hold an object to be processed; a rotation driving part configured to rotate the object to be processed held by the holding part; front-side process-liquid supply nozzle configured to supply a process liquid onto a peripheral portion of a front surface of the object to be processed held by the holding part; and a storage part disposed on a side of a rear surface of the object to be processed held by the holding part, the storage part being configured to store the process liquid having been passed through the object to be processed. The respective first housing and the second housing can be moved in one direction, so that the first housing and the second housing can be brought into contact and separated from each other.

Abstract: Processing chamber shutter blade and robot blade assemblies are constructed to eliminate thermal effects on the placement of elements in processing chambers. Such blade assemblies may contain at least two parts, which may include a positioning member including a low CTE material and a thermal compensating member including a high CTE material. The positioning member includes a coupling point and a reference point on a reference axis separated by a first distance. The thermal compensating member includes a connection point and a controlled point separated by another distance that is less than the first distance. A distance ratio of the first distance to the other distance is substantially equal to a CTE ratio of the high CTE material to the low CTE material, and the positioning member is joined to the thermal compensating member through the coupling point and the connection point.

Abstract: Methods and apparatus for rapid thermal processing of a planar substrate including axially aligning the substrate with a substrate support or with an empirically determined position are described. The methods and apparatus include a sensor system that determines the relative orientations of the substrate and the substrate support.