Patents Issued in March 16, 2017
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Publication number: 20170074921Abstract: A life estimation circuit includes a temperature detector configured to detect temperature of a power element unit, an inflection point detection unit configured to detect an inflection point of temperature variation in the power element unit based on an output signal from the temperature detector, an operation unit configured to determine an absolute value of a difference between the temperature of the power element unit at an inflection point detected this time and the temperature of the power element unit at an inflection point detected last time, a count circuit configured to count the number of times that the absolute value of the difference in temperature has reached a threshold temperature, and a signal generation unit configured to output, when a count value from the count circuit reaches a threshold number of times, an alarm signal indicating that the power element is about to reach the end of its life.Type: ApplicationFiled: June 13, 2016Publication date: March 16, 2017Applicant: Mitsubishi Electric CorporationInventors: Shiori UOTA, Fumitaka TAMETANI, Takahiro INOUE, Rei YONEYAMA
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Publication number: 20170074922Abstract: A test device uses a single probe to test plurality of pads of at least one chip, and includes a test circuit, a plurality of short-circuit elements and a plurality of probes. The plurality of short-circuit elements is formed in scribe lines around the at least one chip, where each of the plurality of short-circuit elements connects the plurality of pads, and the plurality of pads includes one testing pad and at least one non-testing pad. The plurality of probes receives a plurality of test signals generated by the at least one chip from the testing pad via the plurality of short-circuit elements, so the test circuit generates a test result according to the plurality of test signals.Type: ApplicationFiled: April 13, 2016Publication date: March 16, 2017Inventors: Hung-Wei Lai, Tsung-Jun Lee
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Publication number: 20170074923Abstract: Disclosed is a chip reliability testing method that includes mounting a test chip on a test board whereby each test circuit of the test chip is connected to a different pair of input and output terminals. The reliability test can include applying a test voltage to a first (input) bump and measuring an output voltage on a second (output) bump connected to the same test circuit. The first and second bumps are, in turn, electrically connected to each other through a series of conductive materials to define the test circuit. The conductive materials include first and second contact pads under the first and second bumps with the contact pads, in turn, being connected to a conductive substrate or redistribution layer. The conductive substrate or redistribution layer is, in turn, connected to first and second conductive vias that each provide a connection to one or more of a series of conductive layers that are arranged under the conductive substrate or redistribution layer and over a silicon device.Type: ApplicationFiled: November 28, 2016Publication date: March 16, 2017Inventors: Shiang-Ruei SU, Liang-Chen LIN, Chia-Wei TU
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Publication number: 20170074924Abstract: Embodiments of the present disclosure provide techniques and configurations for integrally determining a parameter (e.g., temperature) of a die of an integrated circuit. In one instance, the apparatus may comprise a die including a first (e.g., remote) area and a second (e.g., local) area disposed at a distance from the first area, and circuitry to determine a parameter associated with the remote area of the die. The circuitry may include: a first sensing device disposed in the remote area, to provide first readings associated with the parameter; a second sensing device disposed in the local area, to provide second readings associated with the parameter; and a control module coupled with the sensing devices and disposed in the local area, to facilitate a determination of the parameter based on the first and second readings provided by the first and second sensing devices. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: Cho-Ying Lu, Matthias Eberlein, Hyung-Jin Lee
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Publication number: 20170074925Abstract: According to one embodiment, a device is disclosed. The device includes a substrate, an element provided on the substrate, and a film on the substrate. The film and the substrate constitute a cavity in which the element is housed. The device further includes a member capable of generating heat or deforming.Type: ApplicationFiled: March 10, 2016Publication date: March 16, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroaki YAMAZAKI
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Publication number: 20170074926Abstract: A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). To prevent rotation of the pins in the pin guide, a walled recess in the bottom of the pin guide engages flanges on the pins. In another embodiment, the pin guide maintains rotational alignment by being fitted around the pin profile or having projections abutting the pin. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.Type: ApplicationFiled: March 10, 2015Publication date: March 16, 2017Inventors: Jathan Edwards, Charles Marks, Brian Halvorson
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Publication number: 20170074927Abstract: One or more contacts are detected in an electron microscope image corresponding to a region of interest on an integrated circuit. One or more standard cells are identified based on the detected one or more contacts in the electron microscope image. One or more components of the integrated circuit are determined based on the identified one or more standard cells.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: Lynne M. Gignac, Chung-Ching Lin, Franco Stellari
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Publication number: 20170074928Abstract: An apparatus according to embodiments detects locations of faults in a multilayer semiconductor (MLS). The apparatus comprises a laser source that outputs a laser beam, an optical system that directs the laser beam selectively onto a target region in the MLS to generate an irradiated zone in the MLS, a stage and a scanner that control a relative position between the irradiated zone and the MLS so that the irradiated zone moves along the target region, a controller system that measures electrical signals or electrical signal changes induced by a temperature increase in the MLS, and identifies a location of the target region and locations of faults in the MLS based on the measured electrical signal or the measured electrical signal changes.Type: ApplicationFiled: September 6, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Juan Felipe TORRES, Kei MATSUOKA
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Publication number: 20170074929Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.Type: ApplicationFiled: November 22, 2016Publication date: March 16, 2017Inventor: Lee D. Whetsel
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Publication number: 20170074930Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: JASBIR SINGH NAYYAR, SHASHANK SRINIVASA NUTHAKKI, RAHUL GULATI, ARUN SHRIMALI
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Publication number: 20170074931Abstract: A semiconductor circuit has circuit units in a plurality of stages which units are continuously connected, each of the circuit units in the plurality of stages including: a first register; a second register; a first outputter; and a second outputter. The first outputter is connected to the first register and the second register, and selects and outputs one of a first input signal inputted from the first register and a second input signal inputted from the second register. The second outputter outputs at least one of the second input signal and a third input signal to a second register in a next stage, the third input signal being outputted from a logic circuit unit that performs logic operation on the basis of an input signal containing at least one of a signals outputted from the first outputters.Type: ApplicationFiled: March 10, 2016Publication date: March 16, 2017Inventor: Jun Hasegawa
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Publication number: 20170074932Abstract: A method for debugging and a method for testing a circuit design on a programmable logic device is disclosed, making use of a parameterized configuration. A corresponding system also is disclosed.Type: ApplicationFiled: November 29, 2016Publication date: March 16, 2017Inventors: Alexandra KOURFALI, Dirk STROOBANDT
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Publication number: 20170074933Abstract: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.Type: ApplicationFiled: November 22, 2016Publication date: March 16, 2017Inventor: Lee D. Whetsel
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Publication number: 20170074934Abstract: A number of switching transitions of flip-flops during testing is kept below a threshold. Scan-in test data is applied to the flip-flops. Testing result data scanned-out from the flip-flops is captured, and a prediction is made of a number of switching transitions of the flip-flops between a current capture clock cycle and a next capture clock cycle—in particular, for the next capture clock cycle—thereby using the scan-in test data for the next capture clock cycle and the testing result data scanned-out of the current capture clock cycle. Furthermore, the testing setup values are modified before the next testing cycle is executed based on the prediction in order to enter a new configuration of a testing circuit such that the predicted number of switching transitions of the flip-flops stays below the threshold. The testing setup values comprise parameters for modifying the capture clock cycle and a seed value for generating test patterns.Type: ApplicationFiled: September 11, 2015Publication date: March 16, 2017Inventors: Satya Rama S. Bhamidipati, Mary P. Kusko, Cedric Lichtenau
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Publication number: 20170074935Abstract: A number of switching transitions of flip-flops during testing is kept below a threshold. Scan-in test data is applied to the flip-flops. Testing result data scanned-out from the flip-flops is captured, and a prediction is made of a number of switching transitions of the flip-flops between a current capture clock cycle and a next capture clock cycle—in particular, for the next capture clock cycle—thereby using the scan-in test data for the next capture clock cycle and the testing result data scanned-out of the current capture clock cycle. Furthermore, the testing setup values are modified before the next testing cycle is executed based on the prediction in order to enter a new configuration of a testing circuit such that the predicted number of switching transitions of the flip-flops stays below the threshold. The testing setup values comprise parameters for modifying the capture clock cycle and a seed value for generating test patterns.Type: ApplicationFiled: November 14, 2015Publication date: March 16, 2017Inventors: Satya Rama S. Bhamidipati, Mary P. Kusko, Cedric Lichtenau
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Publication number: 20170074936Abstract: In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.Type: ApplicationFiled: November 22, 2016Publication date: March 16, 2017Inventor: Lee D. Whetsel
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Publication number: 20170074937Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.Type: ApplicationFiled: November 22, 2016Publication date: March 16, 2017Inventor: Lee D. Whetsel
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Publication number: 20170074938Abstract: An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the combinational logic, combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic, a scan output for transmitting test response data obtained from the combinational logic, and control inputs having an enable input and a select input for operating the parallel scan paths, each scan path includes flip-flops of the combinational logic that, in a test mode, are connected in series, compare circuitry indicates the result of a comparison of the received test response data and the expected data at a fail flag output, and one of the scan paths includes a scan cell having an input coupled to the fail flag output.Type: ApplicationFiled: November 23, 2016Publication date: March 16, 2017Inventor: Lee D. Whetsel
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Publication number: 20170074939Abstract: According to one embodiment, a semiconductor integrated circuit comprises: a tested block including a test control circuit; and a control circuit configured to output a first signal. The test control circuit performs a test of at least a first test pattern of the test patterns for the scan chain in accordance with the first signal during a first non-access state period of the tested block, and performs a test of at least a second test pattern following the first test pattern of the test patterns for the scan chain in accordance with the first signal during a second non-access state period of the tested block, and the test of the first test pattern and the test of the second test pattern are performed discontinuously.Type: ApplicationFiled: February 29, 2016Publication date: March 16, 2017Inventor: Kenichi Anzou
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Publication number: 20170074940Abstract: A light-on module testing device, a method for testing a light-on module and a method for testing a display panel are disclosed. The light-on module testing device includes a base, a support element disposed on the base, and a test platform disposed on the base, wherein an arm is disposed on the support element, and the arm is configured to fix a light-on module to be tested, and a tester is disposed on the test platform and the tester has a signal output end.Type: ApplicationFiled: April 22, 2016Publication date: March 16, 2017Inventors: Wei LI, Yo Seop CHEONG, Namin KWON, Minghui MA, Jinhu CAO, Xin WANG
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Publication number: 20170074941Abstract: Aspects of the invention provide a system and method for detecting inter-circuit faults within a generator stator. In one embodiment, a computer system includes: a sampler for sampling phase voltages and phase currents of a generator stator; a plurality of pre-defined blocks for enabling, based on the sampled phase voltages and currents, an inter-circuit fault detection scheme; a level detection block for determining, in response to the enabled inter-circuit fault detection scheme, a plurality of differences between the sampled phase voltages; and a comparison logic device for comparing, in response to the enabled inter-circuit fault detection scheme, each of the differences of the sampled phase voltages and determining, based on the differences, an inter-circuit fault within at least one phase of the generator stator. The system may also include a negative sequence voltage block for detection of inter-circuit fault within a generator stator.Type: ApplicationFiled: October 26, 2016Publication date: March 16, 2017Inventors: Shantanu Som, Zeeky Ashiono Bukhala
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Publication number: 20170074942Abstract: An inventive testing method is intended for testing a battery pack unit including: a battery pack including a plurality of cells electrically connected to each other; and a duct assembly through which a coolant is supplied to the cells of the battery pack. The testing method includes: a) charging the battery pack under predetermined conditions while supplying the coolant to the duct assembly; b) acquiring temperature information on the cells at predetermined time intervals during step a); and c) determining whether a difference between the highest and lowest ones of the temperatures of the cells measured at substantially the same time is equal to or greater than a predetermined reference temperature difference on the basis of the temperature information acquired in step b).Type: ApplicationFiled: September 14, 2016Publication date: March 16, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Motoki MIYAZAKI
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Publication number: 20170074943Abstract: An operation state estimation apparatus configured to estimate an operation state of an energy storage device includes a history acquirer configured to acquire a charge-discharge history of the energy storage device during a predetermined period, and a pattern data generator configured to generate pattern data in accordance with the acquired charge-discharge history, the pattern data being obtained by patterning data indicating repetitive variation out of data indicating variation in state quantity of the energy storage device during the predetermined period. An operation state estimation method of estimating an operation state of an energy storage device executed by a computer includes a history acquisition step of acquiring a charge-discharge history of the energy storage device during a predetermined period, and a pattern data generation step of generating pattern data in accordance with the acquired charge-discharge history.Type: ApplicationFiled: March 12, 2015Publication date: March 16, 2017Inventor: Yohei TAO
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Publication number: 20170074944Abstract: A test system for testing a battery pack having a high voltage terminal, a low voltage terminal, first and second battery modules, and a master microprocessor is provided. The test system includes an inverter unit and a test computer. The inverter unit iteratively grounds the high voltage terminal and the low voltage terminal. The test computer sends a first message to the master microprocessor that requests first and second voltage values of the first and second battery modules. The master microprocessor sends a second message having the first and second voltage values to the test computer which determines a first voltage deviation value. The test computer sets a test flag to a predetermined pass value if the test computer received the second message and the first voltage deviation value is less than a first threshold voltage deviation value.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: Fouad Fadel, Dalhoon Lee
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Publication number: 20170074945Abstract: A method for monitoring the status of a plurality of connected battery cells in a battery pack includes: arranging the battery cells in at least two groups of cells; connecting the groups of cells to a sensor unit; and providing a measurement of at least one parameter indicative of the state of operation of the battery pack by the sensor unit. The method further includes arranging the groups of cells m a manner so that at least two of the groups include two or more cells and at least two of the groups overlap so that a cell forms part of the overlapping groups; and connecting the sensor unit to the groups; and wherein the number of groups is less than the number of cells.Type: ApplicationFiled: June 2, 2014Publication date: March 16, 2017Applicant: VOLVO TRUCK CORPORATIONInventors: Esteban GELSO, Jonas HELLGREN
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Publication number: 20170074946Abstract: Several embodiments perform battery backup unit (BBU) degradation testing. For example, a BBU testing system can be coupled to or part of a BBU. The BBU testing system can discharge the BBU by engaging a variable load to the BBU. The BBU testing system can monitor a discharge energy consumption over time as the BBU discharges until the discharge energy consumption reaches a specified amount of energy. The BBU testing system can determine a discharge time for the discharge energy consumption to reach the specified amount of energy. The BBU testing system can then compute a degradation state of the BBU based on the discharge time.Type: ApplicationFiled: September 14, 2015Publication date: March 16, 2017Inventors: Soheil Ebrahimzadeh, Pierluigi Sarti
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Publication number: 20170074947Abstract: Each of a plurality of first magnetoresistive elements includes a double spiral pattern in plan view. The double spiral pattern includes a first spiral pattern, a second spiral pattern, and an S-shaped or inverted S-shaped pattern that joins the first spiral pattern and the second spiral pattern at a center portion of the double spiral pattern. Orientations of the double spiral patterns of the plurality of first magnetoresistive elements are different from each other in a circumferential direction, and orientations of the S-shaped or inverted S-shaped patterns differ from each other in the circumferential direction.Type: ApplicationFiled: November 22, 2016Publication date: March 16, 2017Inventors: Daisuke MORI, Syuji OKABE
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Publication number: 20170074948Abstract: A chopping technique, and associated structure, is implemented to cancel the magnetic 1/f noise contribution in a Tunneling Magnetoresistance (TMR) field sensor. The TMR field sensor comprises a first bridge circuit including multiple TMR elements to sense a magnetic field and a second circuit to apply a bipolar current pulse adjacent to each TMR element. The current lines are serially or sequentially connected to a current source to receive the bipolar current pulse. The field sensor has an output comprising a high output and a low output in response to the bipolar pulse. This asymmetric response allows a chopping technique for 1/f noise reduction in the field sensor.Type: ApplicationFiled: November 4, 2016Publication date: March 16, 2017Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Bradley Neal ENGEL, Phillip G. MATHER
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Publication number: 20170074949Abstract: According to one embodiment, a sensor includes a supporter, a film portion, a first sensing element, a second sensing element, and a processor. The film portion is supported by the supporter, and is deformable. The first sensing element is fixed to the supporter, and Includes a first magnetic layer, a second magnetic layer, and a first intermediate layer provided between the first magnetic layer and the second magnetic layer. The second sensing element is fixed to the film portion, and includes a third magnetic layer, a fourth magnetic layer, and a second intermediate layer provided between the third magnetic layer and the fourth magnetic layer. The processor outputs an output signal when a first signal is in a first state. The first signal is obtained from the first sensing element. The output signal is based on a second signal obtained from the second sensing element.Type: ApplicationFiled: August 26, 2016Publication date: March 16, 2017Inventors: Yoshihiro HIGASHI, Yoshihiko FUJI, Hideaki FUKUZAWA, Michiko HARA, Motomichi SHIBANO
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Publication number: 20170074950Abstract: An electromagnetic impedance sensing device includes a first substrate, a first patterned conductive layer, a second substrate, a second patterned conductive layer, a magneto-conductive wire and an encapsulation layer. The first substrate has a first surface, and the first patterned conductive layer is formed on the first surface. The second substrate has a second surface facing to the first surface, and the second patterned conductive layer is formed on the second surface and electrically contacted to the first patterned conductive layer. The first and second patterned conductive layers are physically integrated to define an accommodation space allowing the magneto-conductive wire passing there through. The magneto-conductive wire is encapsulated by the encapsulation layer to make the magneto-conductive wire electrically isolated from the first and second patterned conductive layers, respectively.Type: ApplicationFiled: September 9, 2016Publication date: March 16, 2017Applicant: PROLIFIC TECHNOLOGY INC.Inventors: Hung-Ta LI, Po-Feng LEE
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Publication number: 20170074951Abstract: An electromagnetic impedance sensing device includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a magneto-conductive wire and an encapsulation layer. The substrate has a surface and a trench extending into thereof. The first patterned conductive layer is formed on the surface, as well as a bottom and sidewalls of the trench. The magneto-conductive wire is disposed in the trench. The second patterned conductive layer extending across the trench and electrically in contact with the first patterned conductive layer is formed on the first patterned conductive layer to make the magneto-conductive wire sandwiched between the first and the second patterned conductive layers. The magneto-conductive wire is encapsulated by the encapsulation layer to make the magneto-conductive wire electrically isolated from the first and second patterned conductive layers.Type: ApplicationFiled: September 9, 2016Publication date: March 16, 2017Applicant: PROLIFIC TECHNOLOGY INC.Inventors: Hung-Ta LI, Po-Feng LEE
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Publication number: 20170074952Abstract: Systems and methods for sampling fluids using nuclear magnetic resonance (NMR). Specifically the system is related to a robust field oriented piping system having an improved pipe design for use at oil and gas well heads. The piping system includes integral coils for transmitting an NMR pulse sequence and detecting NMR signals and can be used as a component of an NMR instrument. The systems and methods described herein enable obtaining and analyzing NMR spectra of multi-phase in stationary and flowing states.Type: ApplicationFiled: August 31, 2016Publication date: March 16, 2017Applicant: PERM Instruments Inc.Inventors: Apostolos Kantzas, Serguei I. Krioutchkov, Zheng Yin Wang
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Publication number: 20170074953Abstract: A local transmit coil for a magnetic resonance tomograph is provided. The local transmit coil includes a signal transmission device for signal transmission to the magnetic resonance tomograph, and a transmission antenna for generating a magnetic excitation field. The local transmit coil further includes an evaluation device for monitoring a function of the local transmit coil. The evaluation device is configured to transmit a status signal relating to the local transmit coil via the signal transmission device.Type: ApplicationFiled: September 15, 2016Publication date: March 16, 2017Inventors: Nikolaus Demharter, Markus Vester, Volker Weißenberger
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Publication number: 20170074954Abstract: A magnetic resonance-local coil arrangement, a patient positioning device and a magnetic resonance device are provided. A magnetic resonance-local coil arrangement includes an assembly unit and a bracket. The bracket has a fixed end and a loose end. The fixed end of the bracket is arranged on the assembly unit. The assembly unit, with a first extension direction, may be arranged on a patient positioning device of a magnetic resonance device.Type: ApplicationFiled: September 9, 2016Publication date: March 16, 2017Inventor: Robert Rehner
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Publication number: 20170074955Abstract: An RF coil has an improved structure to prevent an excessive heat from being transferred to an object, and a magnetic resonance imaging apparatus includes the same. The MRI apparatus includes an RF coil configured to receive an RF signal, wherein the RF coil may include a first cover configured to allow thermal insulation material to be injected into the inside thereof, a second cover configured to allow thermal insulation material to be injected into the inside thereof and detachably coupled to the first cover to form an inner space with the first cover, and at least one circuit board disposed in the inner space and on which a circuit element configured to receive the RF signal is mounted.Type: ApplicationFiled: February 12, 2016Publication date: March 16, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Kyung Moo CHOI, Hae-Gweon Park, Ju Hyung Lee
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Publication number: 20170074956Abstract: A system and method for performing parallel magnetic resonance imaging (pMRI) process using a low-field magnetic resonance imaging (IfMRI) system includes a substrate configured to follow a contour of a portion of a subject to be imaged by the IfMRI system using a pMRI process. A plurality of coils are coupled to the substrate. Each coil in the plurality of coils has a number of turns and an associated decoupling mechanism selected to operate the plurality of coils to effectuate the pMRI process using the IfMRI system.Type: ApplicationFiled: March 13, 2015Publication date: March 16, 2017Inventors: Matthew S. Rosen, Lawrence L. Wald, Cristen LaPierre
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Publication number: 20170074957Abstract: Systems and methods for magnetic resonance imaging (“MRI”) using a frequency swept excitation that utilizes multiple sidebands to achieve significant increases in excitation and acquisition bandwidth are provided. The imaging sequence efficiently uses transmitter power and has increased sensitivity as compared to other techniques used for imaging of fast relaxing spins. Additionally, the imaging sequence can provide information about both fast and slow relaxing spins in a single scan. These features are advantageous for numerous MRI applications, including musculoskeletal imaging, other medical imaging applications, and imaging materials.Type: ApplicationFiled: April 24, 2015Publication date: March 16, 2017Inventors: Djaudat Idiyatullin, Curt Corum, Michael Garwood
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Publication number: 20170074958Abstract: A method of assessing tissue vascular permeability for nanotherapeutics using non-labeled dextran can include: receiving a non-labeled, physiologically-tolerable dextran solution by a subject; acquiring a plurality of magnetic resonance images of a distribution of the dextran solution within at least one region of interest of the subject for a corresponding plurality of times; and assessing a tissue vascular permeability of the at least one region of interest to dextran particles in the dextran solution based on differences between the plurality of magnetic resonance images, wherein the dextran solution is a substantially mono-disperse solution of dextran particles of one size.Type: ApplicationFiled: March 6, 2015Publication date: March 16, 2017Inventors: Guanshu Liu, Peter C. M. Van Ziji, Yuguo Li
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Publication number: 20170074959Abstract: In various embodiments, the present application discloses systems and methods for magnetic resonance imaging (MRI) of coronary arteries. In various embodiments, the invention allows for motion corrected, simultaneously acquired multiple contrast weighted images with whole-heart coverage and isotropic high resolution. In some embodiments, the invention teaches using interleaved preparatory pulses, a 3D radial golden angle trajectory and 100% respiratory gating efficiency.Type: ApplicationFiled: September 14, 2015Publication date: March 16, 2017Applicant: CEDARS-SINAI MEDICAL CENTERInventors: Debiao Li, Yibin Xie, Jianing Pang, Qi Yang
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Publication number: 20170074960Abstract: In a method and apparatus for acquiring magnetic resonance (MR) data, comprising an MR data acquisition scanner is operated, while a subject is situated therein, to acquire calibration data, and raw data for conversion into image data, by executing an accelerated echo planar imaging data acquisition sequence. The calibration data are acquired by executing a simultaneous echo refocusing sequence in which multiple slices of the examination subject are simultaneously excited. The calibration data and the acquired raw data are entered into an electronic memory during operation of said MR data acquisition scanner, and made available from a processor in electronic form, as at least one data file.Type: ApplicationFiled: September 12, 2016Publication date: March 16, 2017Applicant: Siemens Healthcare GmbHInventors: Himanshu Bhat, Mario Zeller
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Publication number: 20170074961Abstract: An example of a device comprises a signal generator to generate a signal causing a magnetic self test field for a magneto-resistive sensing element. A signal input is configures to receive a first sensor signal at a first time instant before the magnetic self test field is applied and a second sensor signal at a second time instant after the magnetic self test field is applied. An evaluation circuit is configured to determine information indicating a safe operation based on an evaluation of the first sensor signal and the second sensor signal.Type: ApplicationFiled: November 22, 2016Publication date: March 16, 2017Inventors: Franz Jost, Carlos Castro Serrato
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Publication number: 20170074962Abstract: The method and apparatus for angle of arrival estimation are used for estimating the angle of arrival of a received signal by a switched beam antenna array and a single receiver. The switched beam antenna array first collects an omnidirectional signal to be used as a reference signal. A main beam thereof is then switched to scan an angular region of interest. The collected signals from the switched beams are cross-correlated with the reference signal. The cross-correlation coefficient is the highest at the true angle of arrival and relatively negligible otherwise. The collected signal from each beam angle is cross-correlated with the omnidirectional reference signal to determine the angle of arrival of the received signal.Type: ApplicationFiled: September 16, 2016Publication date: March 16, 2017Inventors: AHMED BADAWY, TAMER KHATTAB, DANIELE TRINCHERO, TAREK ELFOULY, AMR MOHAMED
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Publication number: 20170074963Abstract: An array antenna includes a plurality of antennas capturing a coming radio wave and outputting a received signal respectively. An A-D converter converts the received signal to a digital signal, and a frequency detector detects a frequency of the received signal. A sparse signal processor calculates complex amplitudes, which are coefficients for base vectors, each of the base vectors expressing phases of the antennas of the array antenna receiving a radio wave coming from each direction in determined directions, used in expressing the received signal as a linear sum of a finite number of the base vectors, separates the received signal into direction signals for each direction, and calculates the phase of the each of the direction signals. A signal synthesizer aligns the phases of the direction signals using phase differences calculated from phases of the complex amplitudes, and synthesizes the direction signals.Type: ApplicationFiled: May 29, 2015Publication date: March 16, 2017Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Hideyuki FURUHASHI, Hiroaki TSUKAGOSHI
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Publication number: 20170074964Abstract: A method is provided, which includes scanning at least one radio frequency identification (RFID) tag to obtain an identifier of the RFID tag; querying a database using the identifier of the at least one RFID tag to collect information about a location of the at least one RFID tag; determining a bias of a vehicle relative to the location of the scanned at least one RFID tag; and calculating a location of the vehicle based on the bias and the location of the at least one RFID tag.Type: ApplicationFiled: September 16, 2015Publication date: March 16, 2017Inventors: Jingwei Xu, Bruce Bernhardt, Arnold Sheynman
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Publication number: 20170074965Abstract: A user terminal measures a location thereof. In a method for measuring a terminal location, the terminal measures received signal strength indicator (RSSI) values of signals received from a plurality of electronic devices deployed in a space. Then the terminal extracts a preliminary location of the terminal with respect to each of a plurality of predetermined algorithms by applying the plurality of algorithms to the measured RSSI values, identifies a first estimated location of the terminal by applying a predetermined weight to each preliminary location, identifies a second estimated location of the terminal using an output of at least one sensor, and determines a final location of the terminal, based on the first and second estimated locations.Type: ApplicationFiled: September 13, 2016Publication date: March 16, 2017Inventors: Yonggwon LEE, Youngkyu KIM, Taewon AHN, Dongkeon KONG, Kyungjae KIM, Junhyung KIM, Dusan BAEK
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Publication number: 20170074966Abstract: A device configured for tracking spatial placement of one or more HF (High frequency) RFID (Radio-frequency identification) tag objects on a surface is disclosed. The device includes an HF RFID reader, a transmission antenna, and a plurality of reception antennas. The transmission antenna effectively transmits power and data over an area that is defined to be a detection surface. Each one of the plurality of reception antennas is able to effectively receive data from a separate portion of the detection surface, while all of the plurality of reception antennas together are able to effectively receive data from substantially all of the detection surface. In one embodiment, the transmission antenna is constantly transmitting power.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: Peter Pirc, Tvrtko Barbaric
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Publication number: 20170074967Abstract: Apparatus (2) for tracking the position of at least one person (4) walking about a structure (6), which apparatus (2) comprises: (i) position-identifying means (8) for being worn by the person (4); (ii) a plurality of position-determining devices (10) for being positioned at known fixed positions throughout the structure (6) at which the person (4) must pass in order to move about the structure (6); and (iii) monitor means (12) for monitoring the position of a person (4) in a structure (6); and the apparatus (2) being such that: (iv) the position-determining devices (10) emit signals which are able to be received by the position-identifying means (8); (v) each position-determining device (10) emits signals which only travel a distance which is in the vicinity of the position-determining device (10), whereby as the person (4) walks about the structure (6), the position-determining devices (10) are in radio communication one at a time with the position-identifying means (8); (vi) the position-identifying meansType: ApplicationFiled: April 13, 2015Publication date: March 16, 2017Inventor: Stuart Graham Edwards
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Publication number: 20170074968Abstract: Disclosed are various embodiments for fixing a navigational position using guided surface waves launched from guided surface wave waveguide probes at various ground stations. A guided surface wave is received using a guided surface wave receive structure. A reflection of the guided surface wave is received using the guided surface wave receive structure. An amount of time that has elapsed between receiving the guided surface wave and receiving the reflection of guided surface wave is calculated. A location of the guided surface wave receive structure is determined based at least in part on the amount of time elapsed between receiving the guided surface wave and receiving the reflection of guided surface wave.Type: ApplicationFiled: September 10, 2015Publication date: March 16, 2017Inventors: James F. Corum, Kenneth L. Corum, James D. Lilly, Michael J. D'Aurelio
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Publication number: 20170074969Abstract: Disclosed are various approaches for navigation identifying one's current position. A navigation device receives a guided surface wave using a guided surface wave receive structure. The navigation device then receives a reflection of the guided surface wave using the guided surface wave receive structure. The navigation device calculates an amount of time elapsed between receiving the guided surface wave and receiving the reflection of guided surface wave. The navigation device then measures an angle between a wave front of the guided surface wave and a polar axis of the Earth. Finally the navigation device determines a location of the guided surface wave receive structure based at least in part on the angle between the wave front of the guided surface wave and the polar axis of the Earth the amount of time elapsed between receiving the guided surface wave and receiving the reflection of guided surface wave.Type: ApplicationFiled: September 10, 2015Publication date: March 16, 2017Inventors: James F. Corum, Kenneth L. Corum, James D. Lilly, Michael J. D'Aurelio
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Publication number: 20170074970Abstract: Disclosed are various approaches for determining a location using guided surface waves. A wavelength and a phase of a base guided surface wave launched from a ground station and received by the guided surface wave receive structure are identified. A range of an overlaid guided surface wave launched from the ground station and received by the guided surface wave receive structure are identified., wherein the range of the overlaid guided surface wave is measured as a number of wavelengths of the base guided surface wave. A distance of the guided surface wave receive structure from the ground station based at least in part on the phase of the base guided surface wave and the range of the overlaid guided surface wave is calculated. Finally, a location of the guided surface wave receive structure based at least in part on the distance of the guided surface wave receive structure from the ground station is determined.Type: ApplicationFiled: September 10, 2015Publication date: March 16, 2017Inventors: James F. Corum, Kenneth L. Corum, James D. Lilly, Michael J. D'Aurelio