Abstract: A method for operating a substrate processing chamber includes after performing a process using a fluorine-based gas in the substrate processing chamber: a) during a first predetermined period, supplying a gas mixture to the substrate processing chamber including one or more gases selected from a group consisting of molecular oxygen, molecular nitrogen, nitric oxide and nitrous oxide and supplying RF power to strike plasma in the substrate processing chamber; b) during a second predetermined period after the first predetermined period, supplying molecular hydrogen gas and RF power to the substrate processing chamber; c) repeating a) and b) one or more times; d) purging the substrate processing chamber with molecular nitrogen gas; e) increasing chamber pressure; f) evacuating the substrate processing chamber; and g) repeating d), e) and f) one or more times.

Abstract: A method for stabilizing a plasma is disclosed. The method includes (a) providing in an ionization chamber a number of high voltage wires and a gas suitable for forming a plasma, and (b) exposing the gas to a high voltage thereby igniting the gas to form the plasma. Upon ignition, the plasma is subjected to an amount of light. A use of the method to generate X-rays is also disclosed. The invention is further directed to an ionization chamber including (a) a gas suitable for forming a plasma, and (b) a number of high voltage wires for exposing the gas to a high voltage thereby igniting the gas to form the plasma. The ionization chamber includes a device for subjecting the plasma upon ignition to an amount of light. The invention relates to an X-ray generator including such ionization chamber and to a laser apparatus including such X-ray generator.

Abstract: A measurement state in a mass spectrometer device is determined so that the measurement method for the next round of measurement can be automatically determined. The mass spectrometer device (1) is provided with: a first calculation unit (6) that calculates the total amount of ion in a mass spectrum; a second calculation unit (6) that calculates the half-value width of a representative peak selected from peaks appearing in the mass spectrum; and a control unit (7) that determines the measurement method for use in the next round of measurement on the basis of the total amount of ion and the half-value width of the representative peak.

Abstract: A product ion spectrum is created on the basis of MS2 analysis data respectively obtained for a parent compound and a metabolite. Additionally, a neutral loss spectrum, in which the mass of each product ion is replaced with a mass difference between the mass of the product ion and that of a precursor ion, is created. Then, a common peak having the same mass on the neutral loss spectrums of both the parent compound and the metabolite is extracted, and a complementary peak appearing on the product ion spectrum of the metabolite is extracted; this peak appears at a position corresponding to the difference between the mass of the common peak and that of the precursor ion. The ion corresponding to the complementary peak is designated as a precursor ion for the next MS3 analysis, and this MS3 analysis is performed.

Abstract: Within an intermediate vacuum chamber next to an ionization chamber maintained at atmospheric pressure, an electrode group of a radio-frequency carpet composed of a plurality of concentrically arranged ring electrodes is placed before a skimmer, with its central axis coinciding with that of an ion-passing hole. Each ring electrode has a circular radial sectional shape. Radio-frequency voltages with mutually inverted phases are applied to the ring electrodes neighboring each other in the radial direction. Additionally, a different level of direct-current voltage is applied to each ring electrode to create a potential which is sloped downward from the outer ring electrode to the inner ring electrode. The circular cross section of the electrode produces a steep pseudo-potential near the electrode and thereby increases the repulsive force which acts on the ions to repel them from the electrode.

Abstract: A method including bonding a process wafer having integrated circuits and a carrier wafer having at least one alignment mark to form a wafer assembly. The method further includes aligning the wafer assembly using the at least one alignment mark of the carrier wafer.

Abstract: Aromatic resin polymers and compositions containing them are useful as underlayers in semiconductor manufacturing processes.

Abstract: A method of manufacturing a semiconductor device is provided which includes a step of performing a cycle, a predetermined number of times, to form a film on a substrate, the cycle including non-simultaneously performing: (a) a step of supplying a source gas to the substrate in a process chamber; (b) a step of removing the source gas from the process chamber; (c) a step of supplying a reactive gas having a chemical structure different from that of the source gas to the substrate in the process chamber; and (d) a step of removing the reactive gas from the process chamber, wherein the (d) includes alternately repeating: (d-1) a step of exhausting an inside of the process chamber to depressurize the inside of the process chamber; and (d-2) a step of purging the inside of the process chamber using an inert gas.

Abstract: A high power electronic device package constructed to include a high power electronic device having an epitaxial surface attached to a thermally conductive submount by a thermally conductive interface layer having a eutectic metal contact therein. A gallium nitride high electron mobility transistor (GaN HEMT) having a transistor structure formed of a GaN thin film layer bonded to a thermally conductive host substrate via a thermally conductive interface layer disposed therebetween, and a method of forming the GaN HEMT. The GaN HEMTs can be used in such applications as, for example, power amplifiers with x-band radio frequency (RF) power outputs for micro-radar applications.

Abstract: A method of forming an integrated circuit structure includes providing a wafer having a silicon substrate; forming a plurality of shallow trench isolation (STI) regions in the silicon substrate; and forming recesses by removing top portions of the silicon substrate between opposite sidewalls of the plurality of STI regions. Substantially all long sides of all recesses in the silicon substrate extend in a same direction. A III-V compound semiconductor material is then epitaxially grown in the recesses.

Abstract: Certain electronic applications, such as OLED display back panels, require small islands of high-quality semiconductor material distributed over a large area. This area can exceed the areas of crystalline semiconductor wafers that can be fabricated using the traditional boule-based techniques. This specification provides a method of fabricating a crystalline island of an island material, the method comprising depositing particles of the island material abutting a substrate, heating the substrate and the particles of the island material to melt and fuse the particles to form a molten globule, and cooling the substrate and the molten globule to crystallize the molten globule, thereby securing the crystalline island of the island material to the substrate. The method can also be used to fabricate arrays of crystalline islands, distributed over a large area, potentially exceeding the areas of crystalline semiconductor wafers that can be fabricated using boule-based techniques.

Abstract: To provide a plasma processing device and a plasma processing method capable of generating plasma stably and efficiently and processing the entire desired treated region of a substrate efficiently for a short period of time.

Abstract: A pattern forming method includes forming a spin on dielectric film on a substrate, washing the spin on dielectric film by using a washing liquid, drying a surface of the spin on dielectric film after the washing, forming a photosensitive film on the dried coating type insulation film, emitting energy rays to a predetermined position of the photosensitive film in order to form a latent image on the photosensitive film, developing the photosensitive film in order to form a photosensitive film pattern which corresponds to the latent image, and processing the spin on dielectric film with the photosensitive film pattern serving as a mask.

Abstract: A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.

Abstract: A method includes providing a semiconductor substrate; forming a doping oxide layer on the semiconductor substrate; forming a patterning layer on the doping oxide layer, the patterning layer leaving exposed regions of the doping oxide layer; performing a sputtering process to the substrate; and after the sputtering process, performing a wet etching process to the semiconductor substrate to remove the doping oxide layer from the exposed regions.

Abstract: A semiconductor device according to the invention includes p-type well region 3 and n+ source region 4, both formed selectively in the surface portion of n? drift region 2; trench 6 in contact with n+ source region 4 and extending through p-type well region 3 into n? drift region 2; field plate 8 formed in trench 6 with first insulator film 7 interposed between the trench 6 inner surface and field plate 8; gate electrode 10 formed in trench 6 with second insulator film 9 interposed between the trench 6 side wall and gate electrode 10, gate electrode 10 being formed above field plate 8; first insulator film 7 being thicker than second insulator film 9; and n? lightly doped region 21 in n? drift region 2, n? lightly doped region 21 crossing under the bottom surface of trench 6 from the corner portion thereof, n? lightly doped region 21 covering the bottom surface of trench 6.

Abstract: A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.

Abstract: The present invention provides a method of fabricating a trench field-effect device. The method includes: providing a substrate including an epitaxial layer formed on a semiconductor substrate of the substrate and a trench formed in the epitaxial layer; forming a sacrificial dielectric layer on a bottom and a sidewall of the trench; forming a heavily-doped polysilicon region at the bottom, and removing part of the sacrificial dielectric layer not covered by the heavily-doped polysilicon region to expose an epitaxial layer of the sidewall; and oxidizing the heavily-doped polysilicon region and the epitaxial layer simultaneously and forming a thick oxide layer and a trench sidewall gate dielectric layer synchronously on the bottom and the sidewall, respectively; wherein thickness of the thick oxide layer is greater than that of the trench sidewall gate dielectric layer. The method is simple, and figure of merit of the fabricated trench field-effect device is reduced.

Abstract: A manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, which comprises the following steps: 1) introducing a graphene thin film on a Ge-based substrate; 2) conducting fluorination treatment to the graphene thin film to form fluorinated graphene; 3) activating the surface of the fluorinated graphene by adopting ozone plasmas, and then forming a high-k gate dielectric on the surface of the fluorinated graphene through an atomic layer deposition technology; and 4) forming a metal electrode on the surface of the high-k gate dielectric. Since the present invention utilizes the graphene as a passivation layer to inhibit the formation of unstable oxide GeOx on the surface of the Ge-based substrate and to stop mutual diffusion between the gate dielectric and the Ge-based substrate, the interface property between Ge and the high-k gate dielectric layer is improved.

Abstract: A thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are provided. The array substrate comprises: a base substrate and an electrode arranged on the base substrate. The electrode comprises: an aluminum layer or an aluminum alloy layer on the base substrate; and a first barrier layer arranged on the aluminum layer or the aluminum alloy layer and configured for preventing the aluminum layer or the aluminum alloy layer from producing hillocks. The array substrate can eliminate bad phenomenon that the metal aluminum or aluminum alloy formed on the base substrate produces hillocks when subjected to high temperature.

Abstract: Provided are atomic layer deposition methods to deposit a tungsten film or tungsten-containing film using a tungsten-containing reactive gas comprising one or more of tungsten pentachloride, a compound with the empirical formula WCl5 or WCl6.

Abstract: Provided are electronic devices having quantum dots and methods of manufacturing the same. An electronic device includes a first nanorod, a quantum dot disposed on an upper surface of the first nanorod, and a second nanorod that covers a lateral surface of the first nanorod and the quantum dot. The first nanorod and the second nanorod are of opposite types.

Abstract: A method of etching a feature in a substrate includes forming a mask structure over the substrate, the mask structure defining at least one re-entrant opening, etching the substrate through the opening to form the feature using a cyclic etch and deposition process, and removing the mask.

Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

Abstract: In a semiconductor device manufacturing method, on a film to be processed, a mask material film is formed which has pattern openings for a plurality of contact patterns and connection openings for connecting adjacent pattern openings in such a manner that the connection between them is constricted in the middle. Then, a sidewall film is formed on the sidewalls of the individual openings in the mask material film, thereby not only making the diameter of the pattern openings smaller but also separating adjacent pattern openings. Then, the film to be processed is selectively etched with the mask material film and sidewall film as a mask, thereby making contact holes.

Abstract: The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.

Abstract: A semiconductor structure and the method of forming that semiconductor structure. The method includes formation of a plurality of fins from a layer of semiconductor material. At least one fin of the plurality of fins is at least fifty percent wider than each of a group of fins included in the plurality of fins. The method also includes selectively removing the one fin such that only the group of fins remain.

Abstract: A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, the top layer containing a photo-sensitive material. The top layer is patterned via a photolithography process, the patterned top layer including an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.

Abstract: A method for fabricating a semiconductor device comprises removing a portion of a substrate to form a first cavity in the substrate and depositing an insulator material in the first cavity. A sacrificial pattern is formed on a portion of the insulator material in the first cavity and the substrate. Exposed portions of the substrate are removed to form a fin in the substrate. A gate stack is formed over a portion of the fin.

Abstract: A method of forming a semiconductor device is provided. Metallic interconnects are formed in a dielectric layer of the semiconductor device. A hard mask is used to avoid usual problems faced by manufacturers, such as possibility of bridging different conductive elements and via patterning problems when there are overlays between vias and trenches. The hard mask is etched multiple times to extend via landing windows, while keeping distance between the conductive elements to avoid the bridging problem.

Abstract: The invention is directed to a method for patterning a material layer. The method comprises steps of providing a material layer having a first hard mask layer and a second hard mask layer successively formed thereon and then patterning the second hard mask layer. Thereafter, an etching process is performed to pattern the first hard mask layer by using the patterned second hard mask layer as a mask, and the etching process is performed with a power of about 1000 W. Next, the material layer is patterned by using the patterned first hard mask layer as a mask.

Abstract: [Problem] To provide a substrate bonding technique having a wide range of application. [Solution] A silicon thin film is formed on a bonding surface, and the interface with the substrate is surface-treated using energetic particles/metal particles.

Abstract: The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.

Abstract: A method of making crystal semi-conducting material-based elements, including providing a support having amorphous semi-conducting material-based semi-conducting elements, the support being further provided with one or more components and with a reflective protective area configured so as to reflect a light radiation in a given wavelength range, exposing the element(s) to a laser radiation emitting in the given wavelength range so as to recrystallize the elements, the reflective protective area being arranged on the support relative to the elements and to the components so as to reflect the laser radiation and protect the components from this radiation.

Abstract: A method includes molding a device die in a molding material, wherein a metal pillar of the device die is exposed through a surface of the molding material. A substrate is adhered to the molding material. The substrate includes a redistribution layer that further includes redistribution lines. A plating is performed to fill a through-opening in the substrate to form a through-via. The through-via is plated on the metal pillar of the device die. An electrical connector is formed to electrically couple to the through-via.

Abstract: An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Abstract: The disclosed technology relates generally to methods and systems for controlling the release of micro devices. Prior to transferring micro devices to a destination substrate, a native substrate is formed with micro devices thereon. The micro devices can be distributed over the native substrate and spatially separated from each other by an anchor structure. The anchors are physically connected/secured to the native substrate. Tethers physically secure each micro device to one or more anchors, thereby suspending the micro device above the native substrate. In certain embodiments, single tether designs are used to control the relaxation of built-in stress in releasable structures on a substrate, such as Si (1 1 1). Single tether designs offer, among other things, the added benefit of easier break upon retrieval from native substrate in micro assembly processes. In certain embodiments, narrow tether designs are used to avoid pinning of the undercut etch front.

Abstract: A substrate processing apparatus and method includes, a plate that has a size equal to or larger than a principal face of the substrate, and has a horizontal and flat liquid holding face opposing the principal face of the substrate from below. A processing liquid supply unit supplies a processing liquid to the liquid holding face. A control unit controls the processing liquid supply unit and a movement unit to supply the processing liquid to the liquid holding face to form a processing liquid film, a contact step of bringing the principal face of the substrate and the liquid holding face close to each other to bring the principal face of the substrate into contact with the processing liquid film, and a liquid contact maintenance step of maintaining the processing liquid in contact with the principal face of the substrate.

Abstract: The inventive substrate treatment apparatus includes: a rotative treatment control unit which controls a first chemical liquid supplying unit and a second chemical liquid supplying unit to perform a first chemical liquid supplying step of supplying a first chemical liquid to a substrate rotated by a substrate holding and rotating mechanism and a second chemical liquid supplying step of supplying a second chemical liquid to the substrate rotated by the substrate holding and rotating mechanism after the first chemical liquid supplying step; and a cleaning control unit which controls the cleaning liquid supplying unit to spout the cleaning liquid from the cleaning liquid outlet port to supply the cleaning liquid to the cup inner wall and/or the base wall surface before start of the second chemical liquid supplying step after end of the first chemical liquid supplying step, and/or during and/or after the second chemical liquid supplying step.

Abstract: A substrate holding device is provided with an electrostatic chuck that has an electrode therein and is provided with a substrate holding surface, on one side of which a substrate is held; a displacement gauge that is disposed above or below the substrate holding surface; and a controller which, along with using the displacement gauge to measure a first distance to the substrate when a substrate is placed on the substrate holding surface, uses the displacement gauge to measure a second distance to the substrate after a predetermined voltage is applied to the electrode of the electrostatic chuck and, based on the difference between the measured distances, ascertains whether the clamping of the substrate to the electrostatic chuck has been performed in a normal manner.

Abstract: A wafer transport method is provided. The wafer transport method includes loading an initial carrier containing a first wafer and a second wafer on a first semiconductor apparatus, and processing the first wafer by the first semiconductor apparatus, and loading the first wafer into a first carrier disposed on the first semiconductor apparatus. The wafer transport method also includes processing the second wafer by the first semiconductor apparatus, and loading the second wafer into a second carrier disposed on the first semiconductor apparatus. The wafer transport method further includes processing the first wafer by a second semiconductor apparatus, and loading the first wafer into an integration carrier disposed on the second semiconductor apparatus. The wafer transport method further includes processing the second wafer by the second semiconductor apparatus, and loading the second wafer into the integration carrier disposed on the second semiconductor apparatus.

Abstract: A fixture for conveying a mask plate comprising: a conveying bracket; and a fixation structure that is arranged on the conveying bracket and configured to fix the mask plate to be conveyed. The fixture has the following advantageous effects: it is able to prevent the hands from being in direct contact with the mask plate, thereby reducing the risk of conveyance damage of the mask plate which improves the operation efficiency.

Abstract: A substrate aligner providing minimal substrate transporter extend and retract motions to quickly align substrate without back side damage while increasing the throughput of substrate processing. In one embodiment, the aligner having an inverted chuck connected to a frame with a substrate transfer system capable of transferring substrate from chuck to transporter without rotationally repositioning substrate. The inverted chuck eliminates aligner obstruction of substrate fiducials and along with the transfer system, allows transporter to remain within the frame during alignment. In another embodiment, the aligner has a rotatable sensor head connected to a frame and a substrate support with transparent rest pads for supporting the substrate during alignment so transporter can remain within the frame during alignment. Substrate alignment is performed independent of fiducial placement on support pads.

Abstract: In various aspects of the disclosure, a semiconductor substrate processing system may include an electrostatic chuck for holding a semiconductor substrate attached to an electrically insulating carrier; and an AC power supply electrically coupled to the electrostatic chuck.

Abstract: A method for adhesive bonding in microelectronic device processing is provided that includes bonding a handling wafer to a front side of a device wafer with an adhesive comprising phenoxy resin; and thinning the device wafer from the backside of the device wafer while the device wafer is adhesively engaged to the handling wafer. After the device wafer has been thinned, the adhesive comprising phenoxy resin may be removed by laser debonding, wherein the device wafer is separated from the handling wafer.

Abstract: A peeling device separates a superposed substrate, in which a target substrate and a support substrate are joined to each other with an adhesive, into the target substrate and the support substrate. The peeling device includes a holding unit configured to hold the superposed substrate, and a plurality of position adjustment units movable forward and backward with respect to a side surface of the superposed substrate held in the holding unit, and the position adjustment unit configured to perform a position adjustment of the superposed substrate by contacting the side surface of the superposed substrate.

Abstract: A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.

Abstract: A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts.

Abstract: An embodiment of a method of manufacturing a semiconductor device includes forming an oxygen diffusion barrier on a first surface of a Czochralski or magnetic Czochralski silicon substrate. A silicon layer is formed on the oxygen diffusion barrier. P-doped and n-doped semiconductor device regions are formed in the silicon layer. The method also includes forming first and second load terminal contacts.