Abstract: A thin film transistor is provided, which includes a gate electrode on a substrate; a channel layer overlapping the gate electrode; a dielectric layer between the gate electrode and the channel layer; a source electrode and a drain electrode electrically connecting to the channel layer; a passivation layer overlying the source electrode, the drain electrode, and the gate dielectric layer, wherein the channel layer includes two contact portions being in contact with the source electrode and the drain electrode, respectively, and a non-contact portion located between the two contact portions, and wherein one of the two contact portions has a first thickness in a first direction perpendicular to a surface of the substrate, and the non-contact portion has a second thickness less than the first thickness in the first direction.

Abstract: Exemplary embodiments of the present invention relate to a panel and a display device including the same, the panel including a substrate, a signal line arranged on the substrate, the signal line configured to transmit a driving signal, an insulating layer arranged on the signal line, and a pixel electrode and a contact assistant arranged on the insulating layer. The contact assistant is electrically connected to a portion of the signal line, the contact assistant includes indium zinc oxide doped with a metal oxide not including indium or zinc, and the metal oxide has a smaller Gibbs free energy than zinc oxide.

Abstract: A liquid crystal display including a plurality of pixels that display an image, each pixel includes a thin film transistor that includes a gate electrode, a source electrode having a bar-shape and partially overlapping the gate electrode, and a drain electrode facing the source electrode at a location corresponding to the gate electrode, the drain electrode includes a first end portion having a C-shape that surrounds a distal end of the bar-shaped source electrode. This design eliminates an overlap between a data line and the gate electrode, which eliminates an overlap between the data line and the channel area of a semiconductor layer, which reduces a parasitic capacitor of the data line, resulting in less current to drive the data line, resulting in reduced power consumption of the display.

Abstract: The present invention provides a dual gate TFT substrate structure utilizing COA skill, comprising a substrate (1), a bottom gate (2) positioned on the substrate (1), a bottom gate isolation layer (3) covering the bottom gate (2) and the substrate (1), an active layer (4) positioned on the bottom gate isolation layer (3) above the bottom gate (2), an etching stopper layer (5) positioned on the active layer (4) and the bottom gate isolation layer (3), a source/a drain (6) positioned on the etching stopper layer (5) and respectively contacted with two ends of the active layer (4), color filter (8) positioned on the source/the drain (6) and the etching stopper layer (5), and a top gate (9) positioned on the color filter (8) and contacted with the bottom gate (2); the active layer (4) and the thin film of the previous manufacture process can be effectively protected and the original property and the stability of the active layer (4) and the thin film of the previous manufacture process can be ensured.

Abstract: A display device is disclosed. In one aspect, the device includes a plurality of pixels. Each of the pixels includes a first thin-film transistor (TFT) formed over a substrate and comprising gate electrode, a source electrode, and a drain electrode. Each pixel also includes a storage capacitor formed over the substrate, wherein the storage capacitor includes first and second electrodes, and a dielectric layer interposed between the first and second electrodes. The first electrode, the dielectric layer, and the second electrode have substantially the same pattern.

Abstract: Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor (105), a charge equivalent to a threshold value of a TFT (104) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor (105) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT (101). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT (101).

Abstract: A display device is provided. A substrate includes a thin film transistor. A pixel electrode is connected to the thin film transistor. A common electrode is formed on the pixel electrode. A microcavity including liquid crystal molecules is interposed between the pixel electrode and the common electrode. A roof layer is formed on the common electrode. The roof layer includes at least one protrusion. A support member is formed under the at least one protrusion and in a column shape. The support member is surrounded by the liquid crystal molecules. An overcoat is formed on the roof layer and a side of the microcavity.

Abstract: A thin film transistor array substrate includes a thin film transistor including a first gate electrode, an active layer, a source electrode, and a drain electrode. A first conductive layer pattern is on a same layer as the source electrode and the drain electrode and formed of a same material as the source electrode and the drain electrode. An insulating layer is on the first conductive layer pattern and has an opening exposing a patterning cross-section of the first conductive layer pattern. A pixel electrode is on the insulating layer and is coupled to the source electrode or the drain electrode through a contact hole passing through the insulating layer. A diffusion prevention layer covers the patterning cross-section of the first conductive layer pattern and inclined side surfaces of the insulating layer exposed through the opening.

Abstract: The present invention provides a manufacturing method of an array substrate, comprising steps of: forming a gate and a gate line on a substrate; forming a gate insulating layer on the gate and the gate line; forming a pixel electrode on the gate insulating layer; and forming a first connecting via in a portion of the gate insulating layer in a non-display region and corresponding to the gate line, wherein the first connecting via is configured to connect a scanning signal trace to the gate line.

Abstract: A nanowire array is described herein. The nanowire array comprises a substrate and a plurality of nanowires extending essentially vertically from the substrate; wherein: each of the nanowires has uniform chemical along its entire length; a refractive index of the nanowires is at least two times of a refractive index of a cladding of the nanowires. This nanowire array is useful as a photodetector, a submicron color filter, a static color display or a dynamic color display.

Abstract: Some embodiments include a semiconductor device. The semiconductor device includes a transistor having a gate metal layer, a transistor composite active layer, and one or more contact elements over the transistor composite active layer. The transistor composite active layer includes a first active layer and a second active layer, the first active layer is over the gate metal layer, and the second active layer is over the first active layer. Meanwhile, the semiconductor device also includes one or more semiconductor elements forming a diode over the transistor. The semiconductor element(s) have an N-type layer over the transistor, an I layer over the N-type layer, and a P-type layer over the I layer. Other embodiments of related systems and methods are also disclosed.

Abstract: A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure includes: a wafer to be packaged including multiple chip regions and scribe line regions between the chip regions; pads and image sensing regions located on a first surface of the wafer and located in the chip regions; first dike structures covering surfaces of the pads and the scribe line regions; a packaging cover arranged facing the first surface of the wafer; and second dike structures located on a surface of the packaging cover. The second dike structures are arranged corresponding to the scribe line regions. The packaging cover and the wafer are jointed fixedly via the second dike structures and the first dike structures.

Abstract: The present disclosure is an optical filter which includes: a Fabry-Perot resonator equipped with a laminated structure including one sheet of first metal layer, one sheet of second metal layer, and a dielectric layer; and one sheet of plate-shaped wire grid polarizer. The second metal layer is parallel to the first metal layer, the dielectric layer is interposed between the first metal layer and the second metal layer, the one sheet of plate-shaped wire grid polarizer is embedded in the dielectric layer, the one sheet of plate-shaped wire grid polarizer comprises three or more metal wire layers, the metal wire layers are parallel to one another, and the one sheet of plate-shaped wire grid polarizer is parallel to the first metal layer. In the optical filter according to the present invention, the effective extinction ratio of the wire grid polarizer is increased.

Abstract: A method of manufacturing a solid-state imaging apparatus, comprising preparing a semiconductor substrate including a photoelectric conversion portion and a structure which includes an insulating member formed on the photoelectric conversion portion and a wiring pattern formed in the insulating member, forming a film made of SiC and/or SiCN on the structure, forming an opening immediately above the photoelectric conversion portion by removing part of the film and part of the insulating member, and depositing a member in the opening and on the film, and forming a light-guide portion by polishing the member so as to expose the film.

Abstract: The present invention provides a solid state image sensor including a pixel array having a plurality of pixels arranged therein, each of the plurality of pixels including a photoelectric conversion device and a microlens configured to guide incident light to the photoelectric conversion device, the microlens having a lower surface, on an exit side of the incident light, which has a convex shape with respect to the photoelectric conversion device, with a vertex of the convex shape shifting from a center position of the microlens to a central side of the pixel array.

Abstract: The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface, a plurality of sensor elements disposed at the front surface of the substrate. Each of the plurality of sensor elements is operable to sense radiation projected towards the back surface of the substrate. The image sensor also includes a high-k dielectric grid disposed over the back surface of the substrate. The high-k dielectric grid has a high-k dielectric trench and sidewalls. The image sensor also includes a color filter and a microlens disposed over the high-k dielectric grid.

Abstract: A solid-state image capturing apparatus, comprising a plurality of photoelectric conversion portions disposed in a first semiconductor region of a first conductivity type, a first portion of the first conductivity type disposed in the first semiconductor region and configured to supply a first potential to the first semiconductor region, and a second semiconductor region of a second conductivity type configured to receive a second potential, wherein the first portion is disposed between first and second photoelectric conversion portions neighboring each other, and the second semiconductor region is disposed between the first portion and each of the first and second photoelectric conversion portions.

Abstract: An image pickup device which suppresses an increase in chip area of peripheral circuits without degrading the performance of a pixel section and makes it possible to prevent costs from being increased. The image pickup device includes a first semiconductor substrate and a second semiconductor substrate. A pixel section includes photo diodes each for generate electric charges by photoelectric conversion, floating diffusions each for temporarily storing the electric charges generated by the photo diode, and amplifiers each connected to the floating diffusion, for outputting a signal dependent on a potential of the associated floating diffusion. Column circuits are connected to vertical signal lines, respectively, for performing predetermined processing on signals output from the pixel section to vertical signal lines.

Abstract: An image sensor with an organic photoelectric film for converting light into charge may be provided. The image sensor may include an array of image sensor pixels. Each image sensor pixel may include a charge-integrating pinned diode that collects photo-generated charge from the photoelectric film during an integration period. An anode electrode may be coupled to an n+ doped charge injection region in the charge-integrating pinned diode and may be used to convey the photo-generated charge from the photoelectric film to the charge-integrating pinned diode. Upon completion of a charge integration cycle, a first transfer transistor gate may be pulsed to move the charge from the charge-integrating pinned diode to a charge-storage pinned diode. The charge may be transferred from the charge-storage pinned diode to a floating diffusion node for readout by pulsing a gate of a second charge transfer transistor.

Abstract: A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film.

Abstract: A method for producing a semiconductor device includes preparing a wafer having plural portions and having an insulator having plural openings thereon, forming an embedding member in each of the plural openings and on the insulator, removing at least a part of the embedding member, and planarizing the embedding member. The plural portions have a first portion and a second portion and each of the first portion and the second portion has a first region and a second region. The density of the openings in the first region is higher than that in the second region. The process of removing at least a part of the embedding member includes removing the embedding member positioned in the second region of the first portion, and removing the embedding member positioned in the second region of the second portion. A first removal amount and a second removal amount in the processes are different.

Abstract: An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, in an n-type semiconductor substrate, a p-type well as a p-type semiconductor region forming a part of a photodiode is formed and a gate electrode of a transfer transistor is formed. Then, after an n-type well as an n-type semiconductor region forming the other part of the photodiode is formed, a microwave is applied to the semiconductor substrate to heat the semiconductor substrate. Thereafter, a drain region of the transfer transistor is formed.

Abstract: An optoelectronic device comprising a mesa structure including: a first and a second semiconductor portions forming a p-n junction, a first electrode electrically connected to the first portion which is arranged between the second portion and the first electrode, the device further comprising: a second electrode electrically connected to the second portion, an element able to ionize dopants of the first and/or second semiconductor portion through generating an electric field in the first and/or second semiconductor portion and overlaying at least one part of the side flanks of at least one part of the first and/or second semiconductor portion and of at least one part of a space charge zone formed by the first and second semiconductor portions, upper faces of the first electrode and of the second electrode form a substantially planar continuous surface.

Abstract: An optoelectronic device including a semiconductor substrate having a face, light-emitting diodes arranged on the face and including wired conical or frustoconical semiconductor elements, and an at least partially transparent dielectric layer covering the light-emitting diodes, the refractive index of the dielectric layer being between 1.6 et 1.8.

Abstract: The disclosed technology relates to a magnetic memory device. In one aspect, the device includes a first electrode comprising a conductive pillar formed over the substrate and elongated in a vertical direction crossing a lateral surface of the substrate. The device additionally includes a second electrode extending in a lateral direction crossing the first direction, where the second electrode intersects the first electrode. The device additionally includes a magnetic tunnel junction (MTJ) formed at an intersection between the first electrode and the second electrode, where the MTJ continuously surrounds the first electrode. The MTJ includes a reference layer continuously surrounding the pillar of the first electrode, a free layer continuously surrounding the free layer, and a dielectric tunnel barrier interposed between the reference layer and the free layer.

Abstract: The present disclosure relates to a method of forming an integrated circuit that prevents damage to MIM decoupling capacitors, and an associated structure. In some embodiments, the method comprises forming one or more lower metal interconnect structures within a lower ILD layer over a substrate. A plurality of MIM structures are formed over the lower metal interconnect structures, and one or more upper metal interconnect structures are formed within an upper ILD layer over the plurality of MIM structures. Together the lower and upper metal interconnect structures electrically couple the plurality of MIM structures in a series connection between a first voltage potential and a second voltage potential. By placing the MIM structures in a series connection, dissipation of the first voltage potential (e.g., a supply voltage) is spread out over the MIM structures, thereby reducing the voltage potential difference between electrodes of any one of the MIM structures.

Abstract: A cross bar array device includes first electrodes arranged adjacent to each other and extending in a first direction, the first electrodes including a main electrode layer and a scalable electrode layer. Second electrodes are arranged transversely to the first electrodes, the second electrodes including a main electrode layer and a scalable electrode layer. An electrolyte layer is disposed between the scalable electrode layers of the first electrodes and the second electrodes. A scalable electrode is formed from a scalable electrode layer and includes an undercut having a side laterally recessed from a width of a corresponding main electrode.

Abstract: A solid-state image pickup device includes at least two stacked first and second photoelectric conversion sections in each of a plurality of pixels. Sensitivity of the first photoelectric conversion section to a light incident angle is equivalent to sensitivity of the second photoelectric conversion section to a light incident angle, for each of the pixels.

Abstract: An organic light emitting display device may include: a cell array comprising gate lines and data lines intersecting each other on a substrate so as to define a plurality of pixel areas, a plurality of thin film transistors formed at intersections between the gate lines and the data lines to correspond to the plurality of pixel areas, and a protective film evenly formed over the substrate to cover the thin film transistors; a plurality of first electrodes formed such that portions of an metal oxide layer corresponding to emission areas of the respective pixel areas, is made conductive, the metal oxide layer evenly disposed on the protective film; a bank constituting the remaining portion of the metal oxide layer in which the first electrodes are not formed and formed so as to have insulating properties; an emission layer formed over the metal oxide layer; and a second electrode formed on the emission layer so as to face the first electrodes.

Abstract: An organic light emitting display includes a data driving unit connected to data lines, a scan driving unit connected to scan lines, and a display panel having pixel groups arranged in a region where the data lines and scan lines intersect. A pixel group includes a first pixel unit having a first organic light emitting diode configured to emit light of a first color and a second pixel unit having a second organic light emitting diode configured to emit light of second color. The first pixel unit further includes an organic light emitting diode configured to emit light of a third color and the second pixel unit further includes an organic light emitting diode configured to emit light of the third color.

Abstract: An organic light emitting display panel and associated methods, the panel including a substrate; an organic light emitting diode (OLED) on the substrate; and an encapsulation member to separate the OLED from an external environment, wherein the OLED includes a first electrode on the substrate; a pixel defining layer exposing the first electrode and including a flat planar surface and an inclined planar surface extending from the flat planar surface such that the inclined planar surface overlaps an edge of the first electrode; an organic layer, the organic layer including a first region on the first electrode and a second region on the inclined planar surface; and a second electrode on the organic layer, and wherein, in the second region, a thickness of the organic layer is decreased along a direction extending away from the first region.

Abstract: An organic light-emitting display having an improved aperture ratio, the organic light-emitting display including a rear electrode, an opposite electrode, and a pixel electrode between the rear electrode and the opposite electrode. Here, an insulating layer is interposed between the pixel electrode and the rear electrode, wherein the pixel electrode, the insulating layer, and the rear electrode are configured as a capacitor of the organic light-emitting display. In such a structure, as the capacitor is disposed in a light-emitting area where the pixel electrode exists, it is not necessary to provide an additional space for a capacitor, thus improving an aperture ratio of the display.

Abstract: A transparent display device includes a first substrate including a pixel region and a light amount controlling region. An organic light emitting display is positioned in the pixel region and includes an anode electrode, a pixel defined layer, an organic light emitting layer positioned on the anode electrode and in an opening part of the pixel defined layer, and a cathode electrode positioned on the organic light emitting layer. A liquid crystal display is positioned in the light amount controlling region and includes a pixel electrode, a roof layer facing the pixel electrode, and a liquid crystal layer having a plurality of microcavities between the pixel electrode and the roof layer. The microcavities include liquid crystal molecules. A second substrate seals the organic light emitting display and the liquid crystal display.

Abstract: Disclosed is an organic light emitting device (OLED) that may include a first electrode on a substrate, the first electrode having a pattern of a plurality of cells, with each cell defined with an emitting area and a non-emitting area; a second electrode facing the first electrode; an organic layer between the first electrode and the second electrode; a short-circuit preventing layer contacting at least a portion of the first electrode; and an auxiliary electrode on the short-circuit preventing layer in the non-emitting area of each cell, wherein an aperture ratio of the short-circuit preventing layer and the auxiliary electrode in each cell is 30% or more.

Abstract: An organic light emitting display device includes a driving thin film transistor (TFT), the driving thin film TFT includes a lower gate, a source, and a drain on a substrate and on the same layer; a first gate insulating layer covering the lower gate, the source, and the drain; an active layer on the first gate insulating layer; a conductive line contacting the source and the drain; a second gate insulating layer on the active layer; and an upper gate on the second gate insulating layer, wherein the lower gate of the driving TFT is a light shield that blocks light from being irradiated onto the active layer, and the lower gate and the source include the same metal.

Abstract: A flexible display having an array of pixels or sub-pixels is provided. The display includes a flexible substrate and an array of thin film transistors (TFTs) corresponding to the array of pixels or sub-pixels on the substrate. The display also includes a first plurality of metal lines coupled to gate electrodes of the TFTs and a second plurality of metal lines coupled to source electrodes and drain electrodes of the TFTs. At least one of the first plurality of metal lines and the second plurality of metal lines comprises a non-stretchable portion in the TFT areas and a stretchable portion outside the TFT areas.

Abstract: The present invention provides an OLED backplate structure. Multiple auxiliary conducting layers contacting the cathode are provided under the cathode of the OLED, which can diminish the electrical resistance of the cathode to enhance the conductivity of the cathode and to even the in plane voltages. The uniformity of the OLED display can be improved to prevent the uneven brightness issue and to decrease the thickness of the cathode for saving the production cost.

Abstract: Embodiments of the present invention provide an AMOLED device having a non-circular base substrate made of crystalline silicon and doped with an impurity, a crystalline silicon layer over the base substrate, multiple pre-defined anode regions having a high pre-defined work-function and made of one or more electrically conductive materials, one or more functional organic layers capable of generating and emitting light and arranged in a predefined pattern of a plurality of emitters. Each emitter has one-to-one mapping to each anode region. The AMOLED device also includes one or more cathode regions adjacent to the one or more functional organic layers. The one or more cathode regions are capable of transmitting the light and have a low pre-defined work-function. The AMOLED device also includes an encapsulation.

Abstract: In a light emitting device, luminance irregularities caused by fluctuation in threshold of TFTs for supplying a current to EL elements among pixels hinder the light emitting device from improving the image quality. A voltage equal to the threshold of a TFT 110 is held in capacitor means 111 in advance. When a video signal is inputted from a source signal line, the voltage held in the capacitor means is added to the signal, which is then applied to a gate electrode of the TFT 110. Even when threshold is fluctuated among pixels, each threshold is held in the capacitor means 111 of each pixel, and therefore, influence of the threshold fluctuation can be removed. Since the threshold is stored in the capacitor means 111 alone and the voltage between two electrodes is not changed while a video signal is written, fluctuation in capacitance value has no influence.

Abstract: An organic light emitting diode display device includes a semiconductor on a substrate with a driving channel, an auxiliary storage electrode on the substrate with a storage electrode formed of a same material as the semiconductor and separated therefrom, a first insulating layer covering the semiconductor and the auxiliary storage electrode, a driving gate electrode overlapping the auxiliary storage electrode to define an auxiliary storage capacitor, a second insulating layer covering the driving gate electrode and the first insulating layer, a main storage electrode overlapping the driving gate electrode to define a main storage capacitor, a passivation layer covering the data wire and the second insulating layer, a pixel electrode on the passivation layer, an organic emission layer on the pixel electrode, and a common electrode on the organic emission layer.

Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided. Provided is a semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The oxide semiconductor layer includes a first region having a crystal whose size is less than or equal to 10 nm and a second region which overlaps with the insulating layer with the first region provided therebetween and which includes a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the surface of the oxide semiconductor layer.

Abstract: An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.

Abstract: A semiconductor structure including: trench-defining layer; an epitaxial layer; and a set of defect-blocking member(s). The trench-defining layer includes a trench surface which defines an elongated interior space called the “trench.” The epitaxial layer is grown epitaxially in the interior space of the trench. Each defect blocking member of the set of defect blocking members: (i) extends from a portion of trench surface into the interior space of the trench; and (ii) is located below a top surface of the epitaxial layer. The defect blocking member(s) are designed to arrest the propagation of generally-longitudinal defects in the epitaxial layer, as it is grown, where the generally-longitudinal defects are defects that propagate at least generally in the elongation direction of the trench.

Abstract: A method for manufacturing a fin structure. The method includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second and first semiconductor layers to form an initial fin; selectively etching the first semiconductor layer of the initial fin so that the first semiconductor layer has a lateral recess; forming an isolation layer having a portion that fills the lateral recess, wherein the isolation layer, except the portion that fills the lateral recess, has a top surface lower than a top surface of the first semiconductor layer but higher than a bottom surface of the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer.

Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. The first gate electrode layer is in contact with a side wall of the separation plug.

Abstract: Semiconductor devices including STI structures and their fabrication methods are provided. A mask layer is provided on a semiconductor substrate and patterned to form an opening in the mask layer to expose a surface portion of the semiconductor substrate. A trench is then formed in the semiconductor substrate by etching along the opening. A first dielectric layer is formed in the trench and has a top surface lower than a top surface of the semiconductor substrate to provide an uncovered sidewall surface of the trench in the semiconductor substrate. An epitaxial layer is formed on the uncovered sidewall surface of the trench in the semiconductor substrate. The epitaxial layer includes a spacing to expose a surface portion of the first dielectric layer. A second dielectric layer is formed on the exposed surface portion of the first dielectric layer to fill the spacing formed in the epitaxial layer.

Abstract: A semiconductor includes a substrate including a first region and a second region, a fin extending in a first direction in the first region of the substrate, wherein the fin includes a first semiconductor pattern and a second semiconductor pattern that are disposed on each other, a first wire pattern extending in a second direction in the second region of the substrate, a first gate electrode disposed on the fin, wherein the first gate electrode extends in a third direction that is different from the first direction, and a second gate electrode surrounding an outer perimeter of the first wire pattern and extending in a fourth direction that is different from the second direction.

Abstract: A structure of a semiconductor device is described. A device structure including a gate structure, a source region and a drain region is disposed on a first surface of a substrate. Contact holes are etched through the source and drain regions and through a first portion of the substrate. The contact holes are filled with a conductive material to produce contact studs coupled to the source and drain regions. A second portion of the substrate is removed. A surface of the contact studs is exposed through a second surface of the substrate opposite to the gate structure for connection to a wiring layer disposed over the second surface of the substrate.

Abstract: A method of providing an out-of-plane semiconductor structure and a structure fabricated thereby is disclosed. The method comprises acts of: providing a substrate defining a major surface; providing a template layer having a predetermined template thickness on the major surface of the substrate; forming a recess in the template layer having a recess pattern and a recess depth smaller than the template thickness; and epitaxially growing a semiconductor structure from the recess. A planar shape of the recess pattern formed in the template layer substantially dictates an extending direction of the semiconductor structure.

Abstract: A gate pad and a source pad are disposed on a semiconductor layer. The gate pad is disposed at the center portion of the semiconductor layer and has the shape of a circle centered on the center of the semiconductor layer as viewed in plan. The source pad is disposed so as to surround the gate pad, and has the shape of a circular ring centered on the center of the semiconductor layer as viewed in plan. A plurality of unit cells that compose a trench type MOSFET element are formed in the semiconductor layer.