Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O2) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).

Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.

Abstract: A semiconductor device includes a fin structure protruding from a substrate and having a top face and a first side face and a second side face opposite to the first side face, and first semiconductor layers disposed over the first and second side faces of the fin structure. A thickness in a vertical direction of the first semiconductor layers is smaller than a height of the fin structure.

Abstract: An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process.

Abstract: Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.

Abstract: Among other things, a semiconductor device comprising one or more faceted surfaces and techniques for forming the semiconductor device are provided. A semiconductor device, such as a finFET, comprises a fin formed on a semiconductor substrate. The fin comprises a source region, a channel, and a drain region. A gate is formed around the channel. A top fin portion of the fin is annealed, such as by a hydrogen annealing process, to create one or more faceted surfaces. For example the top fin portion comprises a first faceted surface formed adjacent to a second faceted surface at an angle greater than 90 degrees relative to the second faceted surface, which results in a reduced sharpness of a corner between the first faceted surface and the second faceted surface. In this way, an electrical field near the corner is substantially uniform to electrical fields induced elsewhere within the fin.

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

Abstract: A semiconductor device in which a shift of the threshold voltage of a transistor is suppressed is provided. A semiconductor device in which a decrease in the on-state current of a transistor is suppressed is provided. The semiconductor device is manufactured as follows: forming a gate electrode layer over a substrate; forming a gate insulating film over the gate electrode layer; forming an oxide semiconductor film over the gate insulating film; forming a metal oxide film having a higher reducing property than the oxide semiconductor film over the oxide semiconductor film; performing heat treatment while the metal oxide film and the oxide semiconductor film are in contact with each other, thereby the metal oxide film is reduced so that a metal film is formed; and processing the metal film to form a source electrode layer and a drain electrode layer.

Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

Abstract: An oxide semiconductor layer in which “safe” traps exist exhibits two kinds of modes in photoresponse characteristics. By using the oxide semiconductor layer, a transistor in which light deterioration is suppressed to the minimum and the electric characteristics are stable can be achieved. The oxide semiconductor layer exhibiting two kinds of modes in photoresponse characteristics has a photoelectric current value of 1 pA to 10 nA inclusive. When the average time ?1 until which carriers are captured by the “safe” traps is large enough, there are two kinds of modes in photoresponse characteristics, that is, a region where the current value falls rapidly and a region where the current value falls gradually, in the result of a change in photoelectric current over time.

Abstract: A highly reliable semiconductor device which uses an oxide semiconductor film for a backplane is provided. A semiconductor device includes a first conductive film, a first insulating film over the first conductive film, an oxide semiconductor film which is over the first insulating film and overlaps with the first conductive film, a second insulating film over the oxide semiconductor film, and a pair of second conductive films electrically connected to the oxide semiconductor film through an opening portion included in the second insulating film. The second insulating film overlaps with a region of the oxide insulating film in which a carrier flows between the pair of second conductive films and overlaps with end portions of the oxide semiconductor film.

Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

Abstract: One object of the present invention is to provide a structure of a transistor including an oxide semiconductor in a channel formation region in which the threshold voltage of electric characteristics of the transistor can be positive, which is a so-called normally-off switching element, and a manufacturing method thereof. A second oxide semiconductor layer which has greater electron affinity and a smaller energy gap than a first oxide semiconductor layer is formed over the first oxide semiconductor layer. Further, a third oxide semiconductor layer is formed to cover side surfaces and a top surface of the second oxide semiconductor layer, that is, the third oxide semiconductor layer covers the second oxide semiconductor layer.

Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures.

Abstract: A p-type anode layer (2) is provided on an upper surface of an n-type drift layer (1). An n-type cathode layer (3) is provided on a lower surface of the n?-type drift layer (1). An n-type buffer layer (4) is provided between the n?-type drift layer (1) and the n-type cathode layer (3). A peak impurity concentration in the n-type buffer layer (4) is higher than that in the n?-type drift layer (1) and lower than that in the n-type cathode layer (3). A gradient of carrier concentration at a connection between the n?-type drift layer (1) and the n-type buffer layer (4) is 20 to 2000 cm?4.

Abstract: A process is provided for contacting a nanostructured surface. In that process, a substrate is provided having a nanostructured material on a surface, the substrate being conductive and the nanostructured material being coated with an insulating material. A portion of the nanostructured material is at least partially removed. A conductor is deposited on the substrate in such a way that it is in electrical contact with the substrate through the area where the nanostructured material has been at least partially removed.

Abstract: A method and apparatus is disclosed for doping a semiconductor substrate with a dopant concentration greater than 1020 atoms per cubic centimeter. The method is suitable for producing an improved doped wide bandgap wafer for power electronic devices, photo conductive semiconductor switch, or a semiconductor catalyst.

Abstract: The present invention relates to a CZTSe-based composite thin film, a method for preparing the CZTSe-based composite thin film, a solar cell using the CZTSe-based composite thin film, and a method for preparing the solar cell using the CZTSe-based composite thin film.

Abstract: A photoelectric conversion element includes a superlattice semiconductor layer including barrier sub-layers and quantum sub-layers (quantum dot sub-layers) alternately stacked and also includes a wavelength conversion layer containing a wavelength conversion material converting the wavelength of incident light. The wavelength conversion layer converts incident light into light with a wavelength corresponding to an optical transition from a quantum level of the conduction band of the superlattice semiconductor layer to a continuum level of the conduction band.

Abstract: A method for manufacturing a solar cell according to an embodiment of the present invention includes preparing a semiconductor substrate having a first conductivity type dopant; ion-implanting a pre-amorphization elements into a front surface of the semiconductor substrate to form an amorphous layer; and forming an emitter layer by ion-implanting second conductivity type dopant into the front surface of the semiconductor substrate. The method then further includes heat-treating the layers to activate the second conductivity type dopant. The method further includes forming a back surface field layer at a back surface of the semiconductor substrate by ion-implanting a first conductivity type dopant.

Abstract: A mounting system for photovoltaic solar panels providing support for different sized panels, and/or panels having mounting holes located in different locations. A universal panel clamp includes at least one elongated hole or slot to attach to a mounting hole on a solar panel frame. A clamp is attached to an upper hole, and a second clamp is attached to a lower mounting hole. The upper clamps are attached to an upper lateral support member, and the lower clamps are attached to a lower lateral support member. This assembly may be supported by A-shaped support members having adjustable tilt arms, or posts with specially configured brackets.

Abstract: A solar cell module having high reliability by increasing heat release of a bypass diode is provided. A solar cell panel including a photoelectric conversion unit, a holding member disposed at a periphery of the solar cell panel to hold the solar cell panel, a heat release plate spaced from the solar cell panel and disposed on the holding member, and a bypass diode attached to the heat release plate so as to be spaced from the solar cell panel and electrically connected to the photoelectric conversion unit are included. An attachment surface of the bypass diode to the heat release plate is disposed to face the holding member.

Abstract: The present invention includes upconversion materials such as lanthanide-sensitized oxides that are useful for converting low-energy photons into high-energy photons. Because silicon-based solar cells have an intrinsic optical band-gap of 1.1 eV, low-energy photons having a wavelength longer than 1100 nm, e.g., infrared photons, cannot be absorbed by the solar cell and used for photovoltaic energy conversion. Only those photons that have an energy equal to or greater than the solar cell's band gap, e.g., visible photons, can be absorbed and used for photovoltaic energy conversion. The oxides described herein transform photons having an energy less than the energy of a solar cell's band gap into photons having an energy equal to or greater than the energy of the band gap. When these oxides are incorporated into a solar cell, they provide more photons for photovoltaic energy conversion than otherwise would be available in their absence.

Abstract: The present disclosure provides a method of manufacturing a pattern including: forming a trench structure on a substrate using an inkjet method; filling an interior portion of the trench structure with a filler; and removing the trench structure, and a pattern manufactured using the same, and a method of manufacturing a solar battery using the method of manufacturing a pattern and a solar battery manufactured using the same.

Abstract: A method for producing a micro system, said method comprising: providing a substrate (2) made of aluminum oxide; producing a thin film (6) on the substrate (2) by depositing lead zirconate titanate onto the substrate (2) with a thermal deposition method such that the lead zirconate titanate in the thin film (6) is self-polarized and is present predominantly in the rhombohedral phase; and cooling down the substrate (2) together with the thin film (6).

Abstract: A method of manufacture of I-III-VI-absorber photovoltaic cells involves sequential deposition of films comprising one or more of silver and copper, with one or more of aluminum indium and gallium, and one or more of sulfur, selenium, and tellurium, as compounds in multiple thin sublayers to form a composite absorber layer. In an embodiment, the method is adapted to roll-to-roll processing of photovoltaic cells. In an embodiment, the method is adapted to preparation of a CIGS absorber layer having graded composition through the layer of substitutions such as tellurium near the base contact and silver near the heterojunction partner layer, or through gradations in indium and gallium content. In a particular embodiment, the graded composition is enriched in gallium at a base of the layer, and silver at the top of the layer. In an embodiment, each sublayer is deposited by co-evaporation of copper, indium, gallium, and selenium, which react in-situ to form CIGS.

Abstract: A flexible solar module strand manufactured by a method including providing a first conveyor track for applying flexible solar cells; guiding the first conveyor track around two or more deflecting means; providing individual flexible solar cells; applying the individual solar cells to the first conveyor track; deflecting the first conveyor track by guiding the first conveyor track over a first one of the deflecting means; separating the first conveyor track from the at least one deflected solar cell strip in such a manner that the solar cells are released, with their respective first or second sides facing the first conveyor track, from the first conveyor track; and applying the at least one deflected solar cell strip to a first film web in such a manner that the solar cells are oriented, with their respective first or second sides separated from the first conveyor track, away from the first film web.

Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact composed of a sequence of layers over the first subcell at a temperature of 280° C. or less and having a contact resistance of less than 5×10?4 ohms-cm2.

Abstract: A method includes placing at least two substrates on a substrate carrier at a distance from one another, placing the substrate carrier in a reaction chamber, depositing a precursor on the at least two substrates, and performing a first annealing process on the at least two substrates. The at least two substrates include a first content of a first material. The distance between the at least two substrates is based on the first content of the first material and at least one processing parameter. The disclosed method advantageously provides for improved Na-dosing control.

Abstract: To provide a Group III nitride semiconductor light-emitting device production method, which is intended to grow a flat light-emitting layer without reducing the In concentration of the light-emitting layer. The method of the techniques includes an n-side superlattice layer formation step, in which an InGaN layer, a GaN layer disposed on the InGaN layer, and an n-type GaN layer disposed on the GaN layer are repeatedly formed. In formation of the InGaN layer, nitrogen gas is supplied as a carrier gas. In formation of the n-type GaN layer, a first mixed gas formed of nitrogen gas and hydrogen gas is supplied as a carrier gas. The first mixed gas has a hydrogen gas ratio by volume greater than 0% to 75% or less.

Abstract: An optoelectronic device comprises a semiconductor stack, wherein the semiconductor stack comprises a first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer; an electrode formed on the second semiconductor layer, wherein the first electrode further comprises a reflective layer; and an insulative layer formed on the second semiconductor layer, and a space formed between the first electrode and the insulative layer.

Abstract: A low cost, high efficiency light-emitting diode design is disclosed. In some embodiments, a p-n junction of a light-emitting diode is formed in an epitaxial layer grown on a substrate. Grinding the backside of an associated wafer after encapsulation not only opens a light path for the light emitting diode but removes most residual defects.

Abstract: This disclosure discloses a light-emitting device. The light-emitting device comprises: a substrate; an intermediate layer formed on the substrate; a transparent bonding layer; a first semiconductor window layer bonded to the semiconductor layer through the transparent bonding layer; and a light-emitting stack formed on the first semiconductor window layer. The intermediate layer has a refractive index between the refractive index of the substrate and the refractive index of the first semiconductor window layer.

Abstract: Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The active region includes a first sub-region having a first center wavelength and a second sub-region having a second center wavelength different from the first center wavelength.

Abstract: LED structures are disclosed to reduce non-radiative sidewall recombination along sidewalls of vertical LEDs including p-n diode sidewalls that span a top current spreading layer, bottom current spreading layer, and active layer between the top current spreading layer and bottom current spreading layer.

Abstract: A method of fabricating a flip-chip photonic-crystal light-emitting diode (LED) is disclosed. The method includes the steps of: providing an initial substrate including an epitaxial-growth surface and a light-output surface; performing a nanoimprint process on the epitaxial-growth surface of the initial substrate to form a nano-level patterned substrate; forming a flip-chip LED structure on the epitaxial-growth surface of the nano-level patterned substrate; and performing a nanoimprint process on the light-output surface of the nano-level patterned substrate to form the flip-chip photonic-crystal LED. The formation of the photonic-crystal structure on the light-output surface results in enhanced LED light extraction and emission efficiency.

Abstract: An epitaxial structure includes a substrate, a first epitaxial layer and a second epitaxial layer. The substrate has a surface, and the first epitaxial layer is disposed over the substrate and defines a plurality of stepped air voids and an opening over each of the stepped air voids. The second epitaxial layer is disposed on the first epitaxial layer and collectively defines the stepped air voids with the surface and the first epitaxial layer.

Abstract: According to an embodiment, a semiconductor light emitting device includes a foundation layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer. The foundation layer has an unevenness having recesses, side portions, and protrusions. A first major surface of the foundation layer has an overlay-region. The foundation layer has a plurality of dislocations including first dislocations whose one ends reaching the recess and second dislocations whose one ends reaching the protrusion. A proportion of a number of the second dislocations reaching the first major surface to a number of all of the second dislocations is smaller than a proportion of a number of the first dislocations reaching the first major surface to a number of all of the first dislocations. A number of the dislocations reaching the overlay-region of the first major surface is smaller than a number of all of the first dislocations.

Abstract: A light-emitting diode chip includes a semiconductor body including a radiation-generating active region, at least two contact locations electrically contacting the active region, a carrier and a connecting medium arranged between the carrier and the semiconductor body, wherein the semiconductor body includes roughening on outer surfaces facing the carrier, the semiconductor body mechanically connects to the carrier by the connecting medium, the connecting medium locally directly contacts the semiconductor body and the carrier, and the at least two contact locations are arranged on the upper side of the semiconductor body facing away from the carrier.

Abstract: A step of forming, on a surface of a semiconductor structure layer, easily-to-be-etched portions arranged on the basis of crystal directions on the surface of the semiconductor structure layer and a step of subjecting the surface of the semiconductor structure layer to wet etching to form an uneven structure surface including a plurality of protrusions derived from a crystal structure of the semiconductor structure layer on the surface of the semiconductor structure layer are included.

Abstract: A nanostructure semiconductor light emitting device may includes: a base layer having first and second regions and formed of a first conductivity-type semiconductor material; a plurality of light emitting nanostructures disposed on an upper surface of the base layer, each of which including a nanocore formed of the first conductivity-type semiconductor material, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on the nanocore; and a contact electrode disposed on the plurality of light emitting nanostructures, wherein a tip portion of each of light emitting nanostructures disposed on the first region may not be covered with the contact electrode, and a tip portion of each of light emitting nanostructures disposed on the second region may be covered with the contact electrode.

Abstract: A light emitting device includes a substrate, a plurality of light emitting cells separated from each other and disposed on the substrate, and a plurality of conductive interconnection layers electrically connecting two neighboring light emitting cells. Each light emitting cell includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer, a first electrode, a second electrode, and an etching area. The light emitting structure further includes a first side surface and a second side surface, and if a width between the first side surface and the second side surface is defined as W, the second electrode is disposed in an area between a position separated from the first side surface by 1 5 ? W and a position separated from the first side surface of the light emitting structure by 1 2 ? W .

Abstract: A light-emitting device is provided. The light-emitting device comprises: a light-emitting stack having an active layer; an electrode structure on the light-emitting stack and comprising a first electrode and an extension electrode protruding from the first electrode toward an edge of the light-emitting device in a first extending direction; a transparent insulating layer between the light-emitting stack and the electrode structure, wherein the transparent insulating layer comprises a first part and an extension part protruding from the first part toward the edge of the light-emitting device in a second extending direction; wherein a surface area of a surface of the first electrode distal from the transparent insulating layer is smaller than a surface area of a surface of the transparent insulating layer distal from the light-emitting stack, the first electrode is right above the first part, and a part of the extension electrode is right above the extension part.

Abstract: A light emitting device has a plurality of light emitting elements that are arranged with gaps between the devices on a mounting board in a first direction, a wavelength-conversion member that covers the plurality of light emitting elements, a light reflective resin. Each light emitting element has an n-type semiconductor layer, an active layer provided in a part of the n-type semiconductor layer, and a p-type semiconductor layer provided on the active layer. In a second direction which is perpendicular to the first direction, an n-side electrodes are provided at least in regions at both ends of the n-type semiconductor layer, and a p-side electrode is provided on the surface of the p-type semiconductor layer, and wherein in the second direction, the wavelength-conversion member is positioned to approximately align both sides with both active layer side faces, or to dispose its sides outward of the active layer side faces.

Abstract: A method of manufacturing a light-emitting apparatus includes arranging a plurality of semiconductor light-emitting elements in a straight line on a substrate and applying a sealing material, including an optical wavelength converter, in a straight line on the substrate to collectively seal the semiconductor light-emitting elements with the sealing material. The sealing material is applied so that a contour of a longitudinal end of the sealing material has a curvature, in a plan view of the substrate.

Abstract: A submount-free light emitter package with primary optic and method of fabricating the same are disclosed, these packages and methods comprising a light emitter with an optic. The optic may have a shape, which includes a portion that is wider at a point further from the light emitter than a point which is closer. The method includes a light emitter disposed on a carrier surface with at least one structure at least partially surrounding the light emitter. The encapsulant is over the light emitter forming a primary optic. The intermediate element at least partially defines the shape of the primary optic.

Abstract: Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities.

Abstract: Light sources are disclosed utilizing LED dies that have a light emitting surface. A patterned low refractive index layer that can support total internal reflection within the LED die is provided in optical contact with a first portion of the emitting surface. In optical contact with a second portion of the emitting surface is an input surface of an optical element. The refractive index of the low index layer is below both that of the optical element and the LED die. The optical element can have a variety of shapes and sizes.

Abstract: A Light Emitting Diode (LED) component includes a lead frame and an LED that is electrically connected to the lead frame without wire bonds, using a solder layer. The lead frame includes a metal anode pad, a metal cathode pad and a plastic cup. The LED die includes LED die anode and cathode contacts with a solder layer on them. The metal anode pad, metal cathode pad, plastic cup and/or the solder layer are configured to facilitate the direct die attach of the LED die to the lead frame without wire bonds. Related fabrication methods are also described.