Abstract: Disclosed herein is a structure conductive lines disposed in a base layer and separated by a first region. Pillars are each disposed over a respective one of the conductive lines. A dielectric fill layer is disposed over the pillars and extending between the pillars into the first region, and a void is disposed in the dielectric fill layer in the first region between the conductive lines.

Abstract: A semiconductor device includes metal wirings formed in a first interlayer dielectric layer disposed over a substrate, a first insulating layer covering portions of the metal wirings and the first interlayer dielectric layer, a second interlayer dielectric layer with air gaps disposed in a recess between adjacent two metal wirings, and a protective layer formed in a portion of an upper surface of the first interlayer dielectric layer, where the recess is not formed.

Abstract: A method embodiment includes forming a hard mask over a dielectric layer, patterning the hard mask to form an opening, forming a passivation layer on sidewalls of the opening, and forming a trench in the dielectric layer by extending the opening into the dielectric layer using an etching process. The sidewalls of the opening are etched to form a rounded profile in the hard mask and a substantially perpendicular profile in the dielectric layer.

Abstract: Manufacturing stability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes the steps of: forming an etching stopper film over a first interlayer insulating film; forming an inorganic insulating film over the etching stopper film; forming a resist film over the inorganic insulating film; selectively etching the etching stopper film and the inorganic insulating film by using the resist film as a mask to form a first opening in the etching stopper film and to form a second opening in the inorganic insulating film; removing the resist film by O2 plasma ashing; forming a second interlayer insulating film over the inorganic insulating film; and etching the second interlayer insulating film to form a wiring groove that is coupled to the second opening, and etching a portion located under the first opening of the first interlayer insulating film to form a via hole.

Abstract: Various embodiments provide semiconductor devices and fabrication methods. In an exemplary method, a dielectric layer can be formed on a semiconductor substrate. A plurality of pillar structures having a matrix arrangement can be formed on the dielectric layer. A plurality of sidewall spacers can be formed on the dielectric layer. Each sidewall spacer can be formed on a sidewall surface of one of the plurality of pillar structures. A distance between adjacent pillar structures in a same row or in a same column can be less than or equal to a double of a thickness of the each sidewall spacer on the sidewall surface. The plurality of pillar structures can be removed. The dielectric layer can be etched using the plurality of sidewall spacers as an etch mask to form a plurality of trenches or through holes in the dielectric layer.

Abstract: A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a convex portion including an interconnect and a first film above a substrate, forming a second film on the convex portion, and forming a concave portion having a first bottom face of the first film and a second bottom face lower than the upper face of the first film in the second film. The method further includes forming a polymer film in the concave portion by using a polymer that includes first and second portions respectively having first and second affinities for the first film, phase-separating the first and second portions to form a first pattern containing the first portion and located on the first bottom face and a second pattern containing the second portion and located on the second bottom face in the polymer film, and selectively removing the first or second pattern.

Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.

Abstract: Method and apparatus for direct writing of passive structures having a tolerance of 5% or less in one or more physical, electrical, chemical, or optical properties. The present apparatus is capable of extended deposition times. The apparatus may be configured for unassisted operation and uses sensors and feedback loops to detect physical characteristics of the system to identify and maintain optimum process parameters.

Abstract: Methods and systems for stress relieving through-silicon vias are disclosed and may include forming a semiconductor device comprising a stress relieving stepped through-silicon-via (TSV), said stress relieving stepped TSV being formed by: forming first mask layers on a top surface and a bottom surface of a silicon layer, forming a via hole through the silicon layer at exposed regions defined by the first mask layers, and removing the first mask layers. The formed via hole may be filled with metal, second mask layers may be formed covering top and bottom surfaces of the silicon layer and a portion of top and bottom surfaces of the metal filling the formed via hole, and metal may be removed from the top and bottom surfaces of the metal exposed by the second mask layers to a depth of less than half a thickness of the silicon layer.

Abstract: An aluminum interconnection apparatus comprises a metal structure formed over a substrate, wherein the metal structure is formed of a copper and aluminum alloy, a first alloy layer formed underneath the metal structure and a first barrier layer formed underneath the first alloy layer, wherein the first barrier layer is generated by a reaction between the first alloy layer and an adjacent dielectric layer during a thermal process.

Abstract: A method for fabricating semiconductor device comprising: providing a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; removing part of the gate structure; forming a first mask layer on the first ILD layer and the gate structure; removing the first mask layer on the first ILD layer and part of the first mask layer on the gate structure for forming a first hard mask on the gate structure; forming a second mask layer on the first ILD layer, the first hard mask, and the gate structure; and planarizing the second mask layer to form a second hard mask on the gate structure, in which the top surfaces of the first hard mask, the second hard mask, and the first ILD layer are coplanar.

Abstract: Disclosed are embodiments of a method, wherein metal lines and vias of an integrated circuit IC) metal level of are formed without requiring separate cut masks to pattern the trenches for the metal lines and the via holes for the vias. Trenches are formed in an upper portion of a dielectric layer. Each trench is filled with a sacrificial material. A mask is formed above the dielectric layer and patterned with one or more openings, each opening exposing one or more segments of the sacrificial material in one or more of the trenches, respectively. A sidewall spacer is formed in each opening and a selective etch process is performed to form one or more via holes that extend through the sacrificial material and through the lower portion of the dielectric layer below. Subsequently, all the sacrificial material is removed and metal is deposited, thereby forming self-aligned metal lines and via(s).

Abstract: An electronic device package has a base and an electronic device chip mounted on the base. The electronic device chip includes a semiconductor substrate having a front side and a back side, a electronic component disposed on the front side of the semiconductor substrate, an interconnect structure disposed on the electronic component, a through hole formed through the semiconductor substrate from the back side of the semiconductor substrate, connecting to the interconnect structure, and a TSV structure disposed in the through hole. The interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having an upper surface and a bottom surface; and forming a deep hole in the substrate from the upper surface. The method also includes forming an amorphous silicon layer on a side surface and a bottom surface of the deep hole to promote a preferred crystal orientation in subsequently formed layers. Further, the method includes forming a barrier layer having a preferred orientation along the (111) crystal face on the barrier layer. Further, the method also includes forming a metal layer having a preferred orientation along the (111) crystal face on the barrier layer to fill the through hole.

Abstract: A method of preparing semiconductor dies from a semiconductor wafer having a plurality of fabrication regions separated by dicing lines on the top side of the wafer, and an adhesive coating on the back side of the wafer, comprises applying a repellent material to the fabrication regions and dicing lines where the adhesive coating is not intended to be printed; applying the adhesive coating to the back side of the wafer; removing the repellent material; and separating the wafer along the dicing lines into individual dies.

Abstract: A method for manufacturing a semiconductor device is provided with: a step of preparing a semiconductor wafer (22) in a state where the circumference of the semiconductor wafer, which has been divided into semiconductor device parts, is adhered on a dicing sheet (21) supported by a wafer ring (23); a step of fixing the wafer ring (23) after transferring the wafer ring to a table (14) where laser printing is to be performed; and a step of marking on the main surface where the semiconductor material of the semiconductor device parts which configure the semiconductor wafer (22) is exposed, by radiating laser beams through the dicing sheet and an adhesive layer.

Abstract: Forming a semiconductor layer on a semiconductor substrate, a top surface of the semiconductor layer above a fin in a second region is higher than a top surface of the semiconductor layer in a first region, etching the semiconductor layer and a mask in the first region to expose a top surface of the semiconductor substrate to form a first stack, and etching the semiconductor layer and the mask in the second region to expose a top surface of the fin to form a second stack, epitaxially growing a semiconductor material on a top surface of the fin not covered by the second stack, recessing the first and second stack to expose a top surface of the semiconductor layer, a portion of the mask remains above the semiconductor layer in the first stack, top surfaces of each of the first and second stacks each are substantially flush with one another.

Abstract: A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a first source/drain (S/D) region at a base of the narrow fin and forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin. The gate conductor layer and the gate dielectric layer are patterned to form a vertical gate structure and a three-dimensional (3D) gate structure. Gate spacers are formed over sidewalls of the gate structures. A planarizing layer is deposited over the vertical gate structure and the 3D gate structure. A top portion of the narrow fin is exposed. S/D regions are formed on opposite sides of the 3D gate structure to form a 3D transistor, and a second S/D region is formed on the top portion of the narrow fin to form a vertical transistor.

Abstract: Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

Abstract: A method for forming a semiconductor structure includes sequentially providing a semiconductor substrate having NFET regions and NFET regions; forming an insulation layer on the semiconductor substrate; forming a sacrificial layer on the insulation layer; forming first trenches in the PFET regions, and second trenches in the NFET regions; forming a third trench on the bottom of each of the first trenches and the second trenches; forming a first buffer layer in each of the first trenches and the second trenches by filling the third trenches; forming a first semiconductor layer on each of the first buffer layers in the first trenches and the second teaches; removing the first semiconductor layers in the second trenches; forming a second buffer layer with a top surface lower than the insolation layer in each of second trenches; and forming a second semiconductor layer on each of the second buffer layers.

Abstract: A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

Abstract: ALD of HfxAlyCz films using hafnium chloride (HfCl4) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfCl4 pulse time allows for control of the Al % incorporation in the HfxAlyCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxAlyCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ˜4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.

Abstract: A method of measuring a breakdown voltage of a semiconductor element includes the steps below. A wafer provided with a plurality of semiconductor elements each having an electrode is prepared. The wafer is divided into a plurality of chips provided with at least one semiconductor element. After the step of division into the plurality of chips, a breakdown voltage of the semiconductor element is measured while a probe is in contact with the electrode of the semiconductor element in an insulating liquid.

Abstract: An integrated circuit chip includes trenches at least partially surrounding a critical portion of a circuit that is sensitive to temperature variations. The trenches are locally interrupted in order to permit circuit connections to pass between the critical portion and an outer portion containing a remainder of the circuit. The critical portion includes heating resistors and a temperature sensor.

Abstract: A picking-up and placement process for electronic devices comprising: (a) providing a first substrate having a plurality of electronic devices formed thereon, the electronic devices being arranged in an array, and each of the electronic devices comprising a magnetic portion; (b) selectively picking-up parts of the electronic devices from the first substrate via a magnetic force generated from an electric-programmable magnetic module; and (c) bonding the parts of the electronic devices picked-up by the electric-programmable magnetic module with a second substrate.

Abstract: Provided is a technique capable of uniformizing the characteristics of a film after a plurality of substrates are processed. A method of manufacturing a semiconductor device may include: (a) loading a substrate into a process chamber; (b) processing the substrate by performing: (b-1) supplying and exhausting a process gas into and from the process chamber without activating the process gas; (b-2) supplying and exhausting the process gas into and from the process chamber while activating the process gas; (b-3) measuring an amount of impurity desorbed from the substrate while performing (b-2); and (b-4) measuring a gas exhausted from the process chamber after performing (b-3); (c) calculating a process data based on: a first measurement data obtained by repeating (b-3); and a second measurement data obtained by repeating (b-4); and (d) determining whether to terminate (b) based on the process data.

Abstract: An analysis device includes an X-ray generation part configured to generate four monochromatic X-rays with different energies to irradiate a sample, an electrically conductive sample stage configured to place the sample thereon and formed of an electrically conductive material, an electrode configured to detect an electric current carried by irradiating the sample with the four monochromatic X-rays with different energies, and an electric power source configured to apply a voltage between the electrically conductive sample stage and the electrode, wherein the four monochromatic X-rays with different energies are X-rays included within a range from an absorption edge of a compound semiconductor included in the sample to a higher energy side of 300 eV.

Abstract: A method of controlling polishing includes polishing a region of a substrate at a first polishing rate, measuring a sequence of characterizing values for the region of the substrate during polishing with an in-situ monitoring system, determining a polishing rate adjustment for each of a plurality of adjustment times prior to a polishing endpoint time, and adjusting a polishing parameter to polish the substrate at a second polishing rate. The time period is greater than a period between the adjustment times and the projected time is before the polishing endpoint time. The second polishing rate is the first polishing rate as adjusted by the polishing rate adjustment.

Abstract: A system for programming integrated circuit (IC) dies formed on a wafer includes an optical transmitter that outputs a digital test program as an optical signal. At least one optical sensor (e.g., photodiode) is formed with the IC dies on the wafer. The optical sensor detects and receives the optical signal. A processor formed on the wafer converts the optical signal to the digital test program and the digital test program is stored in memory on the wafer in association with one of the IC dies. The optical transmitter does not physically contact the dies, but can flood an entire surface of the wafer with the optical signal so that all of the IC dies are concurrently programmed with the digital test program.

Abstract: An integrated circuit on a substrate includes a peripheral portion that surrounds an active area and is positioned close to a scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in the peripheral portion on different planes of metallizations starting from the substrate and forms an integrated antenna. Magnetic trench structures are provided adjacent the integrated antenna.

Abstract: Various embodiments provide a temperature regulated circuit. The temperature regulated circuit includes a suspended mass that is positioned in an opening of a frame. The suspended mass is suspended from the frame by a plurality of support beams that may be made of thermally insulating material. The suspended mass provides a thermally isolated substrate for an integrated circuit. The suspended mass also includes a temperature sensor configured to measure a temperature of the integrated circuit, and a heater configured to heat the integrated circuit. A controller is positioned on the frame and is configured to receive temperature measurements from the temperature sensor and control the heater based on the temperature measurements.

Abstract: Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure for an integrated circuit (IC) assembly may include a molded lid structure having a body portion, and a side portion that extends from the body portion and forms a cavity configured to house the IC assembly, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, the contiguous interior material having an opening formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the opening. Other embodiments may be described and/or claimed.

Abstract: Method of making through-substrate-vias in glass substrates includes providing a first substrate on which a plurality of needles protruding vertically from the substrate are made; providing a second substrate made of glass; locating the substrates adjacent each other such that the needles on the first substrate face the second substrate; applying heat to a temperature where the glass softens, by heating the glass or the needle substrate or both; applying a force such that the needles on the first substrate penetrate into the glass to provide impressions in the glass; and finally, removing the first substrate and providing material filling the impressions in the second substrate made of glass. A device includes a silicon substrate having a cavity in which a MEMS component is accommodated, and a cap wafer made of a material having a low dielectric constant, and through substrate vias of metal, is bonded to the silicon substrate.

Abstract: The present disclosure relates generally to encapsulant materials, a method of making thereof and the use thereof for maintaining the electrical and mechanical integrity of solder connections between electronic devices and substrates. More specifically, the present disclosure relates to reflow encapsulant materials with fluxing properties and a method of making thereof. The present disclosure further relates to a method of manufacturing flip-chip assemblies using the reflow encapsulant materials of the present disclosure wherein only one heating cycle is utilized.

Abstract: An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the module may reduce the area occupied by the circuit as compared to a circuit where the inductor is disposed adjacent to the module, or to a circuit where the inductor is disposed in the module adjacent to other components of the module. Furthermore, disposing the inductor outside of the module may allow one to install or replace the inductor.

Abstract: Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs containing Embedded Ground Planes (EGPs) and backside EGP interconnect structures are provided. In one embodiment, the method includes electrically coupling an EGP to a backside terminal of a first microelectronic device through a backside EGP interconnect structure. A molded package body is formed around the first microelectronic device, the EGP, and the EGP interconnect structure. The molded package body has a frontside at which the EGP is exposed. One or more Redistribution Layers are formed over the frontside of the molded packaged body and contain at least one interconnect line electrically coupled to the backside contact through the EGP and the backside EGP interconnect structure.

Abstract: A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically coupling a semiconductor die to the first redistribution layer, and forming a first encapsulant layer on the redistribution layer and around the semiconductor die. The dummy substrate may be removed thereby exposing a second surface of the first redistribution layer. A dummy film may be temporarily affixed to the exposed second surface of the redistribution layer and a second encapsulant layer may be formed on the exposed top surface of the semiconductor die, a top surface and side edges of the first encapsulant layer, and side edges of the first redistribution layer. The dummy film may be removed to again expose the second surface of the first redistribution layer, and a second redistribution layer may be formed on the first redistribution layer and on the second encapsulant layer.

Abstract: Methods for depositing silicon on a semiconductor or metallic surface include cycling dosing of silane and chlorosilane precursors at a temperature between 50° C. and 300° C., and continuing cycling between three and twenty three cycles until the deposition self-limits via termination of surface sites with Si—H groups. Methods of layer formation include depositing a chlorosilane onto a substrate to form a first layer, wherein the substrate is selected from the group consisting of InxGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99. The methods may include pulsing a silane to form a silicon monolayer and cycling dosing of the chlorosilane and the silane. Layered compositions include a first layer selected from the group consisting of InxGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises Si—H and Si—OH.

Abstract: A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer.

Abstract: A semiconductor device includes a semiconductor chip which can be a heat-generating semiconductor chip or a semiconductor relay substrate in which an integrated circuit or wiring is built in. A sintered-silver-coated film is adhered on a surface layer part of the semiconductor substrate, interposed by a silicon oxide film. A heat-dissipating fin (heat sink), which may be copper or aluminum, is bonded on the sintered-silver-coated film, interposed by an adhesive layer.

Abstract: An electronic device is provided, which includes an electronic element and a heat dissipating element disposed on the electronic element through a thermal conductor, wherein a width of the thermal conductor is smaller than a width of the electronic element. The thermal conductor includes silver to thereby greatly increase the thermal conductivity of the thermal conductor and hence improve the thermal conduction efficiency of the electronic device.

Abstract: The present disclosure relates to a power semiconductor module comprising a printed circuit board (PCB), and to method of cooling such a power semiconductor module. The module comprises a power semiconductor device and an island of thermally conducting foam embedded into the printed circuit board. The power semiconductor device and the island of thermally conducting foam are positioned on top of each other, and the island is arranged to form a path for a flowing coolant cooling the power semiconductor device.

Abstract: A semiconductor device may include: a plurality of output paths, which include a plurality of through silicon vias (TSVs), respectively, and suitable for transmission of test confirmation information; an information provider suitable for providing the test confirmation information to the plurality of TSVs; and an output controller suitable for selectively blocking one of the output paths including a failed one among the plurality of TSVs.

Abstract: An integrated circuit wafer and fabrication method includes a probe pad structure in saw lanes between integrated circuits. The probe pad structure includes a probe pad with a plurality of pad segments. The pad segments are elements of an interconnect level of the wafer.

Abstract: A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor substrate, and a through-via penetrating across a front surface and a rear surface of the semiconductor substrate while avoiding the element forming region of the semiconductor substrate to form a conductive path between the front surface and the rear surface; a circuit component mounted on a circuit component connection surface at the same side as the front surface of the semiconductor substrate of the semiconductor chip; and an external connection members formed on the rear surface of the semiconductor substrate.

Abstract: A component can include a substrate having an opening extending between first and second surfaces thereof, and an electrically conductive via having first and second portions. The first portion can include a first layer structure extending within the opening and at least partially along an inner wall of the opening, and a first principal conductor extending within the opening and at least partially overlying the first layer structure. The first portion can be exposed at the first surface and can have a lower surface located between the first and second surfaces. The second portion can include a second layer structure extending within the opening and at least partially along the lower surface of the first portion, and a second principal conductor extending within the opening and at least partially overlying the second layer structure. The second portion can be exposed at the second surface.

Abstract: A method including forming a through-substrate via through a thickness of a substrate, the thickness of the substrate is measured from a front side of the substrate to a back side of the substrate, removing a first portion of the substrate to form an opening in the back side of the substrate such that a second portion of the substrate remains in direct contact surrounding a vertical sidewall of the through-substrate via, and filling the opening with an alternate material having a lower modulus of elasticity than the substrate.

Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.