Abstract: An early fault detection system for a low voltage distribution network including: at least two detectors, each located on one of two power poles at either end of a section of a power distribution line; each detector includes a GPS unit, an uninterruptable power supply, a communication means to send data to a base station, antenna sensors having a bandwidth range of 1 MHz to 3 GHz for each wire in the power line, and a processor receiving signals from each sensor and collecting data relating to a maximum value, a time of maximum value, a minimum value, and a time of minimum value for partial discharge signals within the bandwidth range; and the processor or base station being programmed to analyze the collected data to identify a location of pulses above a predetermined value and record the number of such pulses at each location over a predetermined time interval.

Abstract: An electrical power supply includes DC source outputting Vm and a device that detects insulation defects in the DC source. The device includes input terminals connected to the source's terminals, impedances Z1 and Z2 connected in series between the input terminals, where Z1=Z2=Z and Vm/Imax<z<(3/2)*Vm/Imax, wherein Imax is a maximum insulation defect current defined by a standardized safety threshold, and a current-detection circuit connected between ground and an intermediate point between the impedances. The current-detection circuit includes a microcontroller that receives a voltage proportional to the defect current originating from the intermediate point, the input terminal being connected by Z3 to a power supply with Vcc<Vm, the input terminal being connected to ground by way of Z4. The microcontroller is configured to determine amplitude of an insulation defect as a function of the voltage applied to the input terminal, wherein Z*Vcc/(4*Vm)<(Z3,Z4)<Ztmax=Z*Vcc/2Vm.

Abstract: An insulation inspection technique for allowing the occurrence of sparks to be detected more satisfactorily and allowing a board in which sparks have occurred to be more satisfactorily detected as being detective is provided. An insulation inspection apparatus detects a voltage induced between insulation inspection target wiring patterns by the application of a voltage during a time period from the start of the voltage application between the insulation inspection target wiring patterns to a predetermined time when the voltage between the insulation inspection target wiring patterns has stabilized. When a voltage drop due to sparks occurring between the insulation inspection target wiring patterns is detected during the time period, the board to be inspected is determined to be defective. In particular, supply current during the time period is set in accordance with the number of inspection points of an upstream wiring pattern of the insulation inspection target wiring patterns.

Abstract: Circuitry, systems and methods for testing integrated circuits for the presence of anomalies. Techniques include applying a plurality of inputs to an integrated circuit under test to obtain a first plurality of measurements at least partially characterizing power leakage in the integrated circuit under test, encode the first plurality of measurements, by computing a plurality of random linear combinations of measurements in the first plurality of measurements, to obtain a second plurality of encoded measurements determining whether the integrated circuit under test contains at least one anomaly based, at least in part, on the second plurality of encoded measurements.

Abstract: A computer processor implemented method of developing irradiance mapping using a distributed network of solar photovoltaic systems, the method comprising the steps of: selecting a predetermined geographic area having at least five solar photovoltaic systems to provide a photovoltaic system; calibrating the photovoltaic system; reversing the photovoltaic system performance model using a computer processor to solve the irradiance input value; calculating irradiance according to irradiance input value, energy output and weather data using the computer processor to provide a single irradiance point; and mapping at least two single irradiance points to create an irradiance map.

Abstract: A method of verifying a protection apparatus is provided. The method includes: setting a plurality of relay elements for sensing an abnormal state of the protection apparatus; receiving an input regarding test information for testing each of the plurality of relay elements; and when at least one of the plurality of relay elements is in an abnormal state from the reception of the input regarding the test information, identifying whether the protection apparatus has created an abnormal state sensing signal.

Abstract: Provided is a handler apparatus that conveys a device under test to a test socket, including: a socket fitting unit which the test socket fits, prior to fitting of a device holder holding the device under test to the test socket; a test-socket position detecting section that detects a relative position of the socket fitting unit with respect to the test socket in a state in which the socket fitting unit fits the test socket; an actuator that adjusts a position of the device under test on the device holder, based on the detected relative position of the socket fitting unit; and a conveyer that conveys the device holder in which the position of the device under test has been adjusted, to fit the test socket.

Abstract: A test handler comprises a main rotary turret and a loading station operative to convey electronic components to functional modules of the main rotary turret. An auxiliary rotary turret incorporating multiple carrier modules then receives electronic components from the functional modules of the main rotary turret. Multiple testing stations located along a periphery of the auxiliary turret are operative to receive electronic components from the carrier modules for testing while the loading station is concurrently conveying electronic components to the functional modules of the main rotary turret, so that the impact of transfer time is reduced or eliminated in a test process cycle of the test handler.

Abstract: An aging detection circuit is provided. The aging detection circuit is configured on a chip and includes a testing circuit and an aging signal generation circuit. The testing circuit is electrically coupled to the aging signal generation circuit. The testing circuit generates an output signal. The aging signal generation circuit includes a signal generation circuit and a selection circuit. The signal generation circuit generates multiple input signals having different frequencies. The selection circuit selectively outputs one of the input signals as an aging signal to an input terminal of the testing circuit or feeds back the output signal generated by the testing circuit to the input terminal of the testing circuit.

Abstract: A method for detecting static-current failure devices in a chip is provided. The method includes providing a chip and determining existence of a static-current failure device in the chip. The method also includes detecting positions of a plurality of hotspots in the chip when the existence of the static-current failure devices is determined; and selecting a common circuit path according to position information of the hotspots in a circuit layout file of the chip. Further, the method includes converting a circuit layout of the common circuit path into a corresponding electrical diagram and marking the positions of the plurality of hotspots on corresponding positions on the electrical diagram; and detecting a shared device of the hotspots in the electrical diagram. Further, the method includes marking a position of the shared device in the circuit layout as a position of a static-current failure device.

Abstract: A semiconductor device includes a built-in self-test controller suitable for generating a test command and test data, and generating a test result signal in response to test result data, in a built-in self-test mode, an internal circuit suitable for performing a test operation in response to the test command and the test data and generating the test result data as a result of the test operation, and a signal transfer controller suitable for outputting the test command, the test data, and the test result signal through a set probe pad and a set bump pad in the built-in self-test mode.

Abstract: Systems and methods may provide for a debug tool including a debug port and a controller including logic to send, via the debug port, a debug mode request to an external port of a target device. Additionally, the target device may include a connector having the external port and a port controller coupled to the external port, wherein the port controller includes logic to detect the debug mode request via the external port, activate a program path between the external port and the port controller in response to the debug mode request, and process one or more commands received via the program path. In one example, the target device further includes a multiplexer coupled to the external port and the port controller, wherein the logic is to send a routing signal to the multiplexer to activate the program path.

Abstract: Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.

Abstract: In one form, a scan flip-flop includes a clock gating cell and a dedicated clock flip-flop. The clock gating cell provides an input clock input signal as a scan clock signal when a scan shift enable signal is active, and provides the input clock signal as a data clock signal when the scan shift enable signal is inactive. The dedicated clock flip-flop stores a data input signal and provides the data input signal, so stored, as a data output signal in response to transitions of the data clock signal, and stores a scan data input signal and provides the scan data input signal, so stored, as the data output signal in response to transitions of the scan clock signal. The clock gating cell may further provide the input clock signal as the data clock signal when both a scan shift enable signal is inactive and a data enable signal is active.

Abstract: A method of probing wafers includes providing a processor running a parametric test program generator algorithm which execute steps including reading a stored first probe program including a first test sequence (TS1) having a first tests configured for probing at least a first circuit element (FCE) in a first scribe line module. TS1 includes (i) electrical pinning and geometrical data and (ii) first Variable Group data specific for the FCE including first test parameters having at least first forcing conditions. The (ii) is modified with modified second variable group data specific to a second circuit element (SCE) in a second scribe line module. The modified second Variable Group data includes modified second test parameters having second forcing conditions. (i) of TS1 is merged with the modified second Variable Group data to generate code for a second test sequence of a second probe program that is configured for probing the SCE.

Abstract: Systems and methods disclosed herein provide for generating extra variables for an ATPG system utilizing compressed test patterns in the event an ATPG process is presented with faults requiring a higher number of care-bits than can be supported efficiently by the current hardware. The systems and methods provide for a multi-stage decompressor network system with an embedded serializer-deserializer. The systems and methods use a XOR decompressor in a first stage and a serializer-deserializer in conjunction with a second XOR decompressor in a second stage.

Abstract: An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.

Abstract: An ion implantation method includes generating a first ion beam and a second ion beam, the first ion beam having a different configuration from the second ion beam. The method further includes scanning and directing the first ion beam along a first path toward a workpiece to perform ion implantation on the workpiece. The method alternatively includes directing the second ion beam along a second path toward the workpiece to perform ion implantation on the workpiece. The first path is different from the second path.

Abstract: A system on chip (SOC) is provided. The system on chip (SOC) includes: at least one core including a plurality of scan chains operated by a trigger signal; a delay controller generating a delay target selection signal selecting at least one of the plurality of scan chains and a delay depth control signal indicating a delay depth of the trigger signal; and a delay signal generating unit delaying the trigger signal based on the delay target selection signal and the delay depth control signal and providing the delayed trigger signal to the plurality of scan chains.

Abstract: A system and method for testing devices are presented. Embodiments of the present invention use a central controller to coordinate the testing of a plurality of devices under test as well as a plurality of channel circuits that are each operable to be coupled to at least one I/O pin of a device under test of the aforementioned plurality of devices under test. Also, embodiments of the present invention include a plurality of intermediate processors that are each coupled to the central controller and operable to receive and send control signals. These intermediate processors are each coupled to a different set of channel circuits of the plurality of channel circuits and are operable to execute their own instantiation of a test program that is independent of any other intermediate processor of the plurality of intermediate processors for the testing of a device under test associated therewith.

Abstract: A method is disclosed for determining fault states in a half-bridge circuit having at least a first semiconductor switch and a second semiconductor switch are connected in series with one another and each controllable by a control signal to switch between an open and a closed switching state. For each of the first and second semiconductor switches, an actual switching state and a setpoint switching state are determined. A bridge short circuit in the half-bridge circuit is identified if both (a) the actual switching state of the first semiconductor switch is different than the setpoint switching state of the first semiconductor switch and (b) the actual switching state of the second semiconductor switch is different than the setpoint switching state of the second semiconductor switch.

Abstract: The present invention provides an intelligent calibration system for backup-power automatic switching devices, including a power supply module, a control module for logic controls, a voltage output module and a current output module for outputting simulated voltage and current, a signal feedback module for sampling outputted voltage and current signals, a simulated circuit-breaker group, an auxiliary relay, a USB interface for communication, a keyboard for information input, a display module for information interaction and real-time panel presentation, an interface module to facilitate plug-in wires, an indicator light for indicating operation status and a computer for controlling the testing globally. The present invention facilitates easy and fast wiring, and conveniently displays operation interface and related information. The operation is intuitive and simple, overall test efficiency is improved.

Abstract: A system for managing a battery may comprise: an interruption determiner configured to determine an interruption of a vehicle battery voltage; a State Of Charge (SOC) calculator configured to calculate the SOC of the vehicle battery and reset the SOC if the interruption of the battery voltage occurs; and an After Sale Service (AS) generation determiner configured to determine whether the AS of a vehicle component is performed if the interruption of the battery voltage does not occur.

Abstract: Provided is a battery pack, which can prevent a plurality of battery modules from being abnormally assembled. The battery pack may include n battery modules; n slave battery management systems (BMSs) corresponding to the n battery modules, the n slave BMSs respectively and sequentially coupled to each other; and a master BMS coupled to the n slave BMSs. Here, the master BMS is configured to apply a trigger signal to a first slave BMS, the first to (n?1)th slave BMSs are configured to transmit the trigger signal and first to (n?1)th signals, which are different from each other, to a next slave BMS, an nth slave BMS is configured to transmit an nth signal to the master BMS.

Abstract: A measurement system according to one aspect of the present invention includes a battery pack and at least one type of connected device to which the pack is connected. The pack includes a first detection device detecting a predetermined physical quantity in the pack and having a predetermined measurement range. The connected device includes a second detection device detecting a physical quantity the same as the predetermined physical quantity and having a measurement range different from the range of the first detection device. One of the pack and the connected device includes a receiving device and a measurement processing device that performs a predetermined measurement process by using one of: a detection-value-related information received by the receiving device; and a detection result by one device of the first detection device and the second detection device, the one device being provided in one of the pack and the connected device.

Abstract: A Hall effect sensor arrangement comprises at least four (2×n) Hall effect components (where n=integer and n?2), wherein the Hall effect components each have two contact terminals C1, C2 and a signal terminal T1-T4, wherein the contact terminals of the at least four Hall effect components are interconnected with one another such that the at least four Hall effect components are arranged together in a parallel-series interconnection, and comprises a control device 150, which is couplable to the signal terminals T1-T4 of the at least four Hall effect components in a plurality of operating phases such that in the different operating phases at least one of the Hall effect components responds to a first magnetic field component B1 in a first detection direction, and at least another of the Hall effect components responds to a second magnetic field component B2 in a second detection direction, wherein the second detection direction is different than the first detection direction.

Abstract: Magnetic field sensor arrangements and methods provide a magnetic field sensor positioned proximate to a magnet with an axis of sensitivity aligned relative to the magnet in orientations that provide a good sensitivity and a mechanical difference from other arrangements.

Abstract: A MEMS device including a first proof mass, a first magnetized magnetic material disposed partially on a surface of the first proof mass, a first spring anchored to a substrate to support the first proof mass, and a first sensing element coupled to the first proof mass and operable to sense the motion of the first proof mass caused by an ambient acceleration. The MEMS device further includes a second sensing element coupled to the first proof mass and operable to sense the motion of the first proof mass caused by an ambient magnetic field.

Abstract: An alternating magnetic field sensing device comprises at least one magnet and at least one force-electricity converting module. The magnet is mechanically connected to the force-electricity converting module and converts a magnetic signal received in an alternating magnetic field to mechanical force and transmits the mechanical force to the force-electricity converting module. The force-electricity converting module converts the mechanical force provided by the magnet to an electrical signal.

Abstract: A method of fabricating fluxgate devices to measure the magnetic field in two orthogonal, in plane directions, by using a composite-anisotropic magnetic core structure.

Abstract: A method for measuring an angular position of a rotating shaft, the method including providing a magnetic field which rotates with the shaft about an axis of rotation, positioning an integrated circuit having first and second magnetic sensing bridges within the magnetic field at a radially off-center position from the axis of rotation, the first and second magnetic sensing bridges respectively providing first and second signals representative of first and second magnetic field directions, the integrated circuit having a set of adjustment parameters for modifying attributes of the first and second signals, modifying values of the set of adjustment parameters until errors in the first and second signals are substantially minimized, and determining an angular position of the shaft based on the first and second signals.

Abstract: The present invention discloses plural planar Hall-effect sensors each having a magnetic sensing region of an elongated shape, the magnetic sensing regions having plural orientations, wherein, for a ratio of long axis length to short axis length greater than a predetermined number, effective single magnetic domain behavior is exhibited in the sensing region, the sensing having shape-induced uniaxial magnetic anisotropy with the easy axis parallel to the long axis of the magnetic sensing region; further wherein the magnitude of the uniaxial magnetic anisotropy depends on the ratio of the thickness of the sensing region to the length of the short axis, and method of operating the same to measure plural magnetic field components.

Abstract: The present disclosure provides for techniques to improve the sensitivity of magnetic sensor systems. One embodiment of a magnetic sensor system includes a magnetic biasing body comprised of a hard magnetic material and including a recess therein. The recess corresponds to a magnetic flux guidance surface of the magnetic biasing body. The magnetic sensor system also includes a magnetic sensing element arranged in or proximate to the recess. A magnetic flux concentrator, which is made of a soft magnetic material, is disposed in the recess between the magnetic flux guidance surface and the magnetic sensing element. Other techniques are also described.

Abstract: Embodiments relate to xMR sensors having very high shape anisotropy. Embodiments also relate to novel structuring processes of xMR stacks to achieve very high shape anisotropies without chemically affecting the performance relevant magnetic field sensitive layer system while also providing comparatively uniform structure widths over a wafer, down to about 100 nm in embodiments. Embodiments can also provide xMR stacks having side walls of the performance relevant free layer system that are smooth and/or of a defined lateral geometry which is important for achieving a homogeneous magnetic behavior over the wafer.

Abstract: A magnetic field probe, a magnetic field measurement system, and a magnetic field measurement method are provided. The magnetic field probe includes a probe head. The probe head includes a first and second inner metal layer. The first inner metal layer includes a first sensing part and a first connecting part coupled thereto. The first sensing part is configured for detecting a magnetic field signal of a device under test to form a first magnetic field distribution signal. The second inner metal layer includes a second sensing part and a second connecting part coupled thereto. The second sensing part is configured for detecting the magnetic field signal of the device under test to form a second magnetic field distribution signal. A distance between the first sensing part and the device under test is smaller than that between the second sensing part and the device under test.

Abstract: An automated blood sampling system for PET imaging applications that can be operated in or very near to the field of view (FOV) of an MR scanner, such as in a combined MR/PET imaging system. A radiation detector uses APDs (avalanche photo-diodes) to collect scintillation light from crystals in which the positron-electron annihilation photons are absorbed. The necessary gamma shielding is made from a suitable shielding material, preferably tungsten polymer composite. Because the APDs are quite small and are magnetically insensitive, they can be operated in the strong magnetic field of an MR apparatus without disturbance.

Abstract: A method of providing a material sample in a state favorable to retaining spin polarization includes cooling a material sample from a temperature above a freezing point of the material sample down to a second temperature below the freezing point of the material sample; maintaining the sample at about the second temperature for a period of about several hours; and reducing temperature of the material sample to a third temperature lower than the second temperature to provide the material sample in a state favorable to retaining spin polarization, where the steps of cooling, maintaining and reducing are performed in the absence of an adulterant material. The method of providing a sample of pyruvic acid in a state favorable to retaining spin polarization may include cooling the sample of pyruvic acid in the absence of an adulterant material from a temperature above a freezing point of the sample of pyruvic acid down to less than about 200 Kelvin to provide the sample.

Abstract: An electrical circuit with one or more semiconductor components (10) is characterized in that at least one semiconductor junction of at least one of the semiconductor components of the electrical circuit is disposed such that the average direction of motion of the charge carriers in the semiconductor junction is essentially parallel to the lines of force of the magnetic field B0, wherein the corresponding semiconductor component is disposed directly on a substrate (12), which is made of a material with good thermal conduction properties. In this way, undistorted characteristics of the semiconductor component used can be ensured despite the very strong magnetic field and the low operating temperatures.

Abstract: A magnetic resonance apparatus includes a magnet unit that contains a high-frequency antenna unit, and a housing casing unit enclosing the magnet unit. The housing casing unit includes a side casing unit, a front casing unit, and a rear casing unit. The side casing unit, the front casing unit, and/or the rear casing unit includes at least one casing part. At least one boundary region of the housing casing unit is disposed between the different casing parts. The housing casing unit includes at least one membrane unit that contains a barrier for the propagation and/or transmission of sound waves and that covers at least one boundary region between two casing parts.

Abstract: a radio frequency (RF) coil device includes a plurality of RF coil elements configured to generate an RF magnetic field, and a support member configured to support the plurality of RF coil elements so that at least one of the plurality of RF coil elements is movable.

Abstract: A magnetic resonance multi-core array radio frequency device and a magnetic resonance signal receiving method are provided. The device comprises a radio frequency receiver which includes a radio frequency coil (11), a low noise preamplifier (13), a multiplexer (15), a radio frequency band-pass filter (17), a program control amplifier (19), a frequency synthesizer (21), a mixer (23), an analog to digital converter (29) and a controller (31). The controller (31) is used for controlling the multiplexer (15) to select a corresponding radio frequency coil channel, a corresponding filtering channel, gain of the radio frequency band-pass filter (17), and receiving a magnetic resonance digital signal transmitted by the analog to digital converter (29). Due to the multiplexer (15), there is no need to configure different circuits respectively for different nuclear magnetic resonance, redundancy of the circuits is reduced, and cost is reduced.

Abstract: An imaging unit of an MRI apparatus collects NMR signals using high frequency pulses including a pre-RF pulse exciting a first region and an excitation RF pulse exciting a second region different from the first region. A shimming parameter calculation unit calculating a shimming parameter for adjusting a radiation magnetic field distribution generated by the high-frequency pulses radiated from a plurality of channels sets different shimming parameters in the pre-RF pulse and the excitation RF pulse. The imaging unit performs imaging using the pre-RF pulse and the excitation RF pulse adjusted with the different shimming parameters.

Abstract: A radiation therapy system comprises: a radiation therapy subsystem (20, 22, 32) configured to perform radiation therapy by applying radiation pulses to a region of a subject at pulse intervals (Tpi); a magnetic resonance (MR) imaging subsystem (10, 16, 30, 36) configured to acquire a dataset of MR imaging data samples from the region of the subject over one or more MR sampling intervals (TAQ) that are longer than the pulse intervals, the one or more MR sampling intervals overlapping at least some of the pulse intervals; a synchronizer (40) configured to identify MR imaging data samples of the dataset whose acquisition times overlap pulse intervals; and a reconstruction processor (44) configured to reconstruct the dataset without the measured values for the MR imaging data samples identified as having acquisition times overlapping pulse intervals to generate a reconstructed MR image.

Abstract: A method of generating a magnetic resonance image includes: generating composite data by using a plurality of data sets acquired from a plurality of coils, based on coil characteristics of the plurality of coils; generating first interpolation data by interpolating the composite data; generating a plurality of filtered data sets by filtering the first interpolation data with respect to a plurality of frequency bands; and generating the magnetic resonance image by using the plurality of filtered data sets.

Abstract: In a method for controlling a magnetic resonance system with multiple radio-frequency transmission channels, via which parallel RF pulse trains are emitted in operation, as well as a magnetic resonance system and a pulse optimization device therefor, RF pulse trains respectively include at least one radio-frequency pulse. The RF pulse trains are initially determined so that a minimum B1 field maximum value is not exceeded by the radio-frequency pulse. In an examination subject-specific adjustment step, a current component-dependent B1 field maximum value is then determined, and the radio-frequency pulse is temporally shortened, with its amplitude being increased dependent on the current component-dependent B1 field maximum value.

Abstract: Systems, methods, and devices for intra-scan motion correction to compensate not only from one line or acquisition step to the next, but also within each acquisition step or line in k-space. The systems, methods, and devices for intra-scan motion correction can comprise updating geometry parameters, phase, read, and/or other encoding gradients, applying a correction gradient block, and/or correcting residual errors in orientation, pose, and/or gradient/phase.

Abstract: A magnetic resonance imaging apparatus according to an embodiment includes sequence controlling circuitry and image generating circuitry. The sequence controlling circuitry executes a pulse sequence which applies a excitation pulse and then continuously applies a readout gradient magnetic field with alternating polarity thereof and acquires echo signals continuously generated by the pulse sequence from a plurality of receive channels. The image generating circuitry corrects the echo signals so as to generate an image, correcting the echo signals for all of the receive channels collectively on the basis of phase differences between echo signals corresponding to even lines of k-space and echo signals corresponding to odd lines of k-space, and corrects the echo signals for each of the receive channels individually on the basis of magnitude differences between echo signals corresponding to the even lines of k-space and echo signals corresponding to the odd lines of k-space.

Abstract: A first off resonance radio frequency (RF) pulse and a second off resonance RF pulse having a phase difference of 180 degrees from the first off resonance RF pulse are applied, one or more auxiliary gradient magnetic fields for offsetting inhomogeneity of a main magnetic field generated by applying the first and second off resonance RF pulses are applied, and magnitudes and signs of the auxiliary gradient magnetic fields are appropriately adjusted. Therefore, artifacts generated due to inhomogeneity of a main magnetic field in an imaging method using an off resonance RF pulse may be removed. When this method is applied to an imaging method using a spatial pre-saturation RF pulse, the phenomenon in which spins excited by the pre-saturation RF pulse are excited again by the off resonance RF pulse to return signals, such that undesired signals overlap and appear in an ultimately-obtained signal, may be removed.

Abstract: A method for measuring scattering parameters in a device under test (DUT) using a vector network analyzer (VNA), includes calibrating the VNA to generate corrections for deterministic setup defects and mapping a plurality of error terms based on a plurality of time indices, wherein each time indicia is associated with an error term. A test signal is transmitted to the DUT to obtain a measurement signal from the DUT in response to the test signal. The generated corrections to obtained measurements are time aligned based on the mapped error terms.

Abstract: A system for directionally classifying of a radio signal originating from an emitter. The system includes a receiving-station, which includes at least two antennas, a single-channel-receiver producing a first and a second received signals and a switch alternately coupling each of the antennas with the single-channel-receiver. The system further includes another receiving-station which includes another receiver, producing another received signal, coupled with a first other antenna. The system further includes directional-classifier which includes a phase-difference-detector, coupled with the single-channel-receiver and with said another receiver. The phase-difference-detector produces a first phase difference measurement when the switch couples one antenna with the single-channel-receiver. The phase-difference-detector further produces a second phase-difference-measurement when the switch couples the other antenna with the single-channel-receiver.