Patents Issued in March 28, 2017
  • Patent number: 9606818
    Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 28, 2017
    Assignee: Qualcomm Incorporated
    Inventors: Erich James Plondke, Lucian Codrescu, Christopher Edward Koob, Piyush Patel, Thomas Andrew Sartorius
  • Patent number: 9606819
    Abstract: The present invention provides a wireless network, an implementation method thereof, and a terminal. The wireless network includes a terminal, a mobile communication network, and a network cloud, where the terminal is connected to the network cloud through the mobile communication network; a virtual machine corresponding to the terminal is provided in the network cloud; a tenant corresponding to the virtual machine is provided on the terminal; the virtual machine is configured to run an application and/or process a file as a proxy of the terminal, and upon reception of an operation command sent by the tenant, transmit display screen image data that is of the application and/or file and corresponds to the operation command to the tenant through a wireless air interface.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 28, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Bingfu Wang, Sheng Liu
  • Patent number: 9606820
    Abstract: A replay core ensures that references to objects are removed at the same relative times and in the same relative order within a program's execution during both record time and replay time. A register method of a Finalizer class is modified to cause the register method to pass, to a specified programmatic mechanism, an object that was passed to the register method; modifying a finalize method of a class of the object to (a) cause the object to invoke a first method of the programmatic mechanism when the finalize method is invoked by a virtual machine and (b) prevent a remainder of the finalize method from completing under specified conditions, thereby causing a call to the finalize method to remain undispatched. The first method, when invoked, (a) adds, to the object, a reference that temporarily prevents the object from being deleted and (b) records an identifier of the object.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: March 28, 2017
    Assignee: CA, Inc.
    Inventors: Jeffrey Daudel, Suman Cherukuri, Humberto Yeverino, Dickey Singh, Arpad Jakab, Marvin Justice, Jonathan Lindo
  • Patent number: 9606821
    Abstract: A virtual environment manager (“VEM”) simplifies the usability of virtual machines and provides users with an enhanced design for creating and/or for managing virtual machines (“VMs”). For example, a user can select description information and management information to be included in descriptors and according to which a VEM will create and manage various VM environments for various host environments. The VEM automatically creates the VM environments and host environments by sending descriptor description information and data files associated with the description information to virtual machine monitors (VMMs), which create the VM environments according to the description information. A VEM at each host may manage VM environments executed by the VMM, according to the descriptor management information. Thus, a set of descriptors to create and manage a set of VMs for a home computer may be easily modified by a user to create and manage a set of VMs for a work or laptop computer.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Scott H. Robinson, Vijay Tewari, Robert C. Knauerhase
  • Patent number: 9606822
    Abstract: Virtual machines are made lightweight by substituting a library operating system for a full-fledged operating system. Consequently, physical machines can include substantially more virtual machines than otherwise possible. Moreover, a hibernation technique can be employed with respect to lightweight virtual machines to further increase the capacity of physical machines. More specifically, virtual machines can be loaded onto physical machines on-demand and removed from physical machines to make computational resources available as needed. Still further yet, since the virtual machines are lightweight, they can be hibernated and restored at a rate substantially imperceptible to users.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 28, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Galen C. Hunt, Reuben R. Olinsky
  • Patent number: 9606823
    Abstract: Exemplary methods, apparatuses, and systems determine a virtual processing unit utilization value representing utilization for a first virtual machine of a plurality of virtual machines running on a host computer. A host processing unit utilization value representing utilization for the host computer including the plurality of virtual machines running on the host computer is also determined. A target coalescing rate is selected based upon the virtual processing unit utilization and host processing unit utilization values. A coalescing rate or a coalescing depth for the first virtual machine is updated based upon the selected target coalescing rate.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: March 28, 2017
    Assignee: VMware, Inc.
    Inventor: Jin Heo
  • Patent number: 9606824
    Abstract: In a distributed computing environment that includes which each execute a VMM, where each VMM supports execution of one or more VMs, administering the VMs may include: assigning, by a VMM manager, the VMMs of the distributed computing environment to a logical tree topology, including assigning one of the VMMs as a root VMM of the tree topology; and executing, amongst the VMMs of the tree topology, a gather operation, including: sending, by the root VMM, to other VMMs in the tree topology, a request to retrieve one or more VMs supported by the other VMMs; pausing, by the other VMMs, each VM requested to be retrieved; and providing, by the other VMMs to the root VMM, the VMs requested to be retrieved.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Archer, Michael A. Blocksome, James E. Carey, Philip J. Sanders
  • Patent number: 9606825
    Abstract: According to one example, a method includes with a hypervisor, detecting that a guest has executed a memory monitor command for a virtual processor, making a copy of a memory address associated with the memory monitor command, the copy being placed in hypervisor memory, and with the hypervisor, in response to detecting that the guest system has executed a wait command, executing a loop until the copy is different than the data stored in the memory address.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: March 28, 2017
    Assignee: Red Hat Israel, Ltd
    Inventors: Michael Tsirkin, Paolo Bonzini
  • Patent number: 9606826
    Abstract: A method, system and computer program product for selecting virtual machines to be migrated to a public cloud. The current resource usage for virtual machine instances running in the private cloud is determined. Furthermore, any scaling policies attached to the virtual machine instances running in the private cloud are obtained. Additional resource usages for any of the virtual machine instances with a scaling policy are computed for when these virtual machine instances are scaled out. A cost of running a virtual machine instance in the public cloud is then determined using its current resource usage as well as any additional resource usage if a scaling policy is attached to the virtual machine instance based on the cost for running virtual machine instances in a public cloud. If the cost is less than a threshold cost, then the virtual machine instance is selected to be migrated to the public cloud.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Rahul Ghosh, Giribabu V. Paramkusham, Aaron J. Quirk, Upendra Sharma
  • Patent number: 9606827
    Abstract: In an approach to sharing memory between a first guest and a second guest both running on a data processing system, one or more computer processors provide a virtual device to a first guest for proxying memory accesses between the first guest and a second guest, where the first guest is associated with the second guest, and where the first guest is running a first operating system and the second guest is running a second operating system. The one or more computer processors send one or more device related functions to the second guest, wherein the virtual device enables sharing memory between the first guest and the second guest.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Utz Bacher, Dominik Dingel, Thomas P. Grosser
  • Patent number: 9606828
    Abstract: A method, system and computer program product for selecting virtual machines to be migrated to a public cloud. The current resource usage for virtual machine instances running in the private cloud is determined. Furthermore, any scaling policies attached to the virtual machine instances running in the private cloud are obtained. Additional resource usages for any of the virtual machine instances with a scaling policy are computed for when these virtual machine instances are scaled out. A cost of running a virtual machine instance in the public cloud is then determined using its current resource usage as well as any additional resource usage if a scaling policy is attached to the virtual machine instance based on the cost for running virtual machine instances in a public cloud. If the cost is less than a threshold cost, then the virtual machine instance is selected to be migrated to the public cloud.
    Type: Grant
    Filed: April 11, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Rahul Ghosh, Giribabu V. Paramkusham, Aaron J. Quirk, Upendra Sharma
  • Patent number: 9606829
    Abstract: A technique for suspending transactional memory transactions without stack corruption. A first function that begins a transactional memory transaction is allocated a stack frame on a default program stack, then returns. Prior to suspending the transaction, or after suspending the transaction but prior to allocating any suspended mode stack frames, either of the following operations is performed: (1) switch from the default program stack to an alternative program stack, or (2) switch from a default region of the default program stack where the first function's stack frame was allocated to an alternative region of the default program stack. Prior to resuming the transaction, or after resuming the transaction but prior to allocating any transaction mode stack frames, either of the following operations is performed: (1) switch from the alternative program stack to the default program stack, or (2) switch from the alternative stack region to the default stack region.
    Type: Grant
    Filed: October 11, 2014
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventor: Paul E. McKenney
  • Patent number: 9606830
    Abstract: Examples of the present disclosure provide a method and device for handling an optimization process, which belong to computer technologies. The method includes: at least one process being executed is determined; a default category process matching with each process in the at least one process is identified, based on a default process category list, in which the default process category list includes a default category process and feature information of the default category process; based on the feature information of the default category process matching with each process in the at least one process, an optimization handling is performed on the at least one process.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: March 28, 2017
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventor: Xiaowen Liang
  • Patent number: 9606831
    Abstract: Embodiments relate to systems and methods for reclassifying a set of virtual machines in a cloud-based network. The systems and methods can analyze virtual machine data to determine performance metrics associated with the set of virtual machines, as well as target data to determine a set of target machines to which the set of virtual machines can be reassigned or reclassified. In embodiments, benefits of reassigning any of the set of virtual machines to any of the set of target virtual machines can be determined. Based on the benefits, the systems and methods can reassign or reclassify appropriate virtual machines to appropriate target virtual machines.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: March 28, 2017
    Assignee: Red Hat, Inc.
    Inventors: James Michael Ferris, Gerry Edward Riveros
  • Patent number: 9606832
    Abstract: A method, system and program product for remote scheduling of at least one job to run on a plurality of computers in a computer network. The job scheduler enables selection of a domain that includes at least a subset of the computers on which the job is to run. A list of computers in the selected domain is automatically generated. The computers on which the job is to run can be selected from the generated list of computers. A configuration file is created for storing an identification of the selected domain and the job to be run on the selected computers in the domain.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: March 28, 2017
    Assignee: Open Invention Network, LLC
    Inventor: Colin Lee Feeser
  • Patent number: 9606833
    Abstract: Method and apparatuses are provided for providing preemptive task scheduling for a Real Time Operating System (RTOS). A two-level priority is assigned to each task that is created. The two-level priority includes a kernel priority and a user-defined priority. A priority bitmap corresponding to the kernel priority is created. A priority bit in the priority bitmap is enabled. The priority bit indicates a status of a respective task.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: March 28, 2017
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Tushar Vrind, Balaji Somu Kandaswamy, Raju Siddappa Udava, Venakata Raju Indukuri
  • Patent number: 9606834
    Abstract: Methods, reservation stations and processors for allocating resources to a plurality of threads based on the extent to which the instructions associated with each of the threads are speculative. The method comprises receiving a speculation metric for each thread at a reservation station. Each speculation metric represents the extent to which the instructions associated with a particular thread are speculative. The more speculative an instruction, the more likely the instruction has been incorrectly predicted by a branch predictor. The reservation station then allocates functional unit resources (e.g. pipelines) to the threads based on the speculation metrics and selects a number of instructions from one or more of the threads based on the allocation. The selected instructions are then issued to the functional unit resources.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: March 28, 2017
    Assignee: Imagination Technologies Limited
    Inventors: Hugh Jackson, Paul Rowland
  • Patent number: 9606835
    Abstract: A plurality of processing entities in which a plurality of tasks are executed are maintained. Memory access patterns are determined for each of the plurality of tasks by dividing a memory associated with the plurality of processing entities into a plurality of memory regions, and for each of the plurality of tasks, determining how many memory accesses take place in each of the memory regions, by incrementing a counter associated with each memory region in response to a memory access. Each of the plurality of tasks are allocated among the plurality of processing entities, based on the determined memory access patterns for each of the plurality of tasks.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 9606836
    Abstract: Specialized processing devices comprise both processing circuitry that is pre-configured to perform a discrete set of computing operations more quickly than generalized central processing units and network transport circuitry that communicationally couples each individual specialized processing device to a network as its own unique network client. Requests for hardware acceleration from workflows being executed by generalized central processing units of server computing devices are directed to hardware accelerators in accordance with a table associating available hardware accelerators with the computing operations they are optimized to perform. Load balancing, as well as dynamic modifications in available hardware accelerators, is accomplished through updates to such a table.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: March 28, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Douglas Christopher Burger, Adrian M. Caulfield, Eric S. Chung, Andrew R. Putnam
  • Patent number: 9606837
    Abstract: A method, apparatus and program product utilize an empirical approach to determine the locations of one or more IO adapters in an HPC environment. Performance tests may be run using a plurality of candidate mappings that map IO adapters to various locations in the HPC environment, and based upon the results of such testing, speculative adapter affinity information may be generated that assigns one or more IO adapters to one or more locations to optimize adapter affinity performance for subsequently-executed tasks.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Wen C. Chen, Tsai-Yang Jea, Wiliam P. LePera, Hung Q. Thai, Hanhong Xue, Zhi Zhang
  • Patent number: 9606838
    Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Brian M. Bass, Bartholomew Blaner, George W. Daly, Jr., Jeffrey H. Derby, Ross B. Leavens, Joseph G. McDonald
  • Patent number: 9606839
    Abstract: Systems and methods for task distribution are provided. A total number of available computing system's processing units is defined, where the total number of available processing units includes a set of regular processing units available for executing tasks and a set of processing units that constitute the reserve pool. Tasks are assigned to processing units. The number of processing units assigned to the next task in the queue is no more than the total number of processing units available at the time, multiplied by the availability ratio. Iterative assignment of processing units to tasks according to the method described is performed as long as there are idle processing units available for task execution, when no more processing units are available, the processing units from the reserve pool are assigned. As a result, the method allows processing units to be available for allocation to a new incoming task at any time.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 28, 2017
    Assignee: ABBYY InfoPoisk LLC
    Inventors: Stepan Matskevich, Tatiana Danielyan
  • Patent number: 9606840
    Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for predicting resource consumption in cloud infrastructures. Implementations include actions of receiving event data from one or more enterprise data sources, determining that an event associated with the event data is a known event, retrieving resource consumption information associated with the event, and providing a resource consumption schedule to a cloud infrastructure, the resource consumption schedule indicating resources expected to be consumed during execution of the event.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 28, 2017
    Assignee: SAP SE
    Inventor: Andreas Schaad
  • Patent number: 9606841
    Abstract: A method for scheduling processes of a workload on a plurality of hardware threads configured in a plurality of processing elements of a multithreading parallel computing system for processing thereby. Process dimensions for each process are determined based on processing attributes associated with each process, and a place and route algorithm is utilized to map the processes to a processor space representative of the processing resources of the computing system based at least in part on the process dimensions to thereby distribute the processes of the workload.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer
  • Patent number: 9606842
    Abstract: A multi-core processor provides circuitry for jointly scaling the number of operating cores and the amount of resources per core in order to maximize processing performance in a power-constrained environment. Such scaling is advantageously provided without the need for scaling voltage and frequency. Selection of the number of operating cores and the amount of resources per core is made by examining the degree of instruction and thread level parallelism available for a given application. Accordingly, performance counters (and other characteristics) implemented in by a processor may be sampled on-line (in real time) and/or performance counters for a given application may be profiled and characterized off-line. As a result, improved processing performance may be achieved despite decreases in core operating voltages and increases in technology process variability over time.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: March 28, 2017
    Assignee: National Science Foundation
    Inventor: Nam Sung Kim
  • Patent number: 9606843
    Abstract: Aspects include computing devices, systems, and methods for adjusting the assignment of tasks to processor cores in a multi-core processing system to increase operating life and maximize device performance by wear-leveling the processor cores. A reliability engine may be configured to collect operation or built in self test data of thermal output and current leakage, and historical operation time for a group of equivalent processor cores configured for the same purpose. Collected data may be applied to a weighted function to determine priorities for each equivalent processor core in the group. The reliability engine may rearrange a virtual processor identification translation table according to the priorities of the equivalent processor cores. A high level operating system may issue a process request specifying a processor core and the specified processor core may be translated to a different processor core according to the order of processor cores dictated by the priorities.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: March 28, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Jon James Anderson, Richard Alan Stewart
  • Patent number: 9606844
    Abstract: Embodiments are directed to interacting with a server in a read-eval-print loop (REPL) environment. In an embodiment, a client computer system receives a proxy object from a remotely-hosted server. The server maintains an execution context with which the client computer system interacts. The client system presents the received proxy object to the user for interaction with the object. The user input indicates how the data in the proxy object is to be processed. The interaction allows the user to manipulate the remotely-hosted data through the local computer system. The client system then, based on the user interaction, sends a user-initiated command to the remotely-hosted server using the proxy object. The user-initiated command indicates various portions of data hosted on the server that are to be returned to the user. The data received from the remotely-hosted server is then displayed at the client computer system.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: March 28, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Samuel Ng, John F. Lam
  • Patent number: 9606845
    Abstract: A first application is constrained from calling a middleware subsystem, where the middleware subsystem is able to access at least one feature selected from among a basic input/output system (BIOS) and hardware. The first application accesses the middleware system through a proxy, where accessing the middleware subsystem allows the first application to communicate with the at least one feature.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: March 28, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Guoxing Yang, Nazih H. Hage, Christopher H. Stewart
  • Patent number: 9606846
    Abstract: A system and method are described in which skeletons and/or stubs are manipulated based on deployment information. For example, a method according to one embodiment of the invention comprises: compiling source code to generate program code executable on an application server comprised of a plurality of different virtual machines, the program code containing stubs and/or skeletons; analyzing the program code to identify stubs and/or skeletons generated for objects which are located within the same virtual machine and/or the same physical machine; removing the stubs and/or skeletons for those objects which are located in the same virtual machine and/or same physical machine to generate modified program code; and deploying the modified program code.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: March 28, 2017
    Assignee: SAP SE
    Inventors: Mladen I. Droshev, Ivan T. Atanassov, Nikolai W. Neichev, Georgi N. Stanev
  • Patent number: 9606847
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for detecting and reporting errors in a machine check environment. A processing device includes an error monitoring module, which detects an error corresponding to data associated with execution of an instruction by the processing device and determines whether the error occurs on portion of the data that affects a result of the instruction. The processing device further enables error detection when it is determined that the error occurs on the portion of the data that affects the result of the execution of the instruction.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Jesus San Adrian Corbal, Dennis R. Bradford, Rohan Sharma
  • Patent number: 9606848
    Abstract: Several types of noise limit the performance of remote sensing systems, e.g., systems that determine the location, color, or shape of remote objects. When noise detected by sensors of the remote sensing systems is known and well estimated, a Kalman filter can converge on an accurate value without noise. However, non-Gaussian noise bursts can cause the Kalman filter to diverge from an accurate value. Current approaches arbitrarily boost noise with fixed additive or multiplicative factors, which slows filter response and often fails to give timely results. Such noise boosts prevent divergence due to badly corrupted measurements. Disclosed embodiments eliminate a subset of noise measurements having the largest errors from a data set of noise measurements and process the remaining data through the Kalman filter. Advantageously, disclosed embodiments enable a Kalman filter to converge on an accurate value without the introduction of noise boost estimates.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 28, 2017
    Assignee: Raytheon Company
    Inventors: William H. Wellman, Eric J. Gudim, Lee M. Savage
  • Patent number: 9606849
    Abstract: The present invention provides a watchdog apparatus in which a main MCU and a sub MCU are connected by SPI communication, including: a token generating unit which generates a seed value and generates at least two tokens using the seed value; a watchdog signal generating unit which generates a watchdog signal corresponding to the generated token; a signal determining unit which determines whether the generated watchdog signal is in a normal state and thus provides an advantageous effect which may detect an abnormality of the MCU only using a software logic without providing an additional configuration.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: March 28, 2017
    Assignee: HYUNDAI MOBIS CO., LTD.
    Inventor: Jaehyun Park
  • Patent number: 9606850
    Abstract: A data processing apparatus comprises processing circuitry for executing a stream of instructions, and exception handling circuitry for selecting, from one or more exceptions, an exception to be handled by the processing circuitry. The unselected exceptions are referred to as pending exceptions. The data processing apparatus further comprises trace generating circuitry that generates trace data packets in dependence on activity of the processing circuitry. The trace generating circuitry detects pending exceptions and, if an exception is detected to be pending, includes an indication of the pending exception in at least one trace data packet. By tracking when a particular exception is pended, rather than when it is selected for handling by the processing circuitry, it is possible to more precisely determine when the exception occurred, as opposed to when it is finally handled.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 28, 2017
    Assignee: ARM Limited
    Inventors: John Michael Horley, Simon John Craske
  • Patent number: 9606851
    Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Michael B. Healy, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • Patent number: 9606852
    Abstract: In one aspect, the present disclosure provides a microcontroller device that has, in one chip: a central processing unit; a plurality of peripheral circuits configured to execute respective prescribed processes in response to corresponding trigger signals; and a peripheral control unit that controls respective activations of the plurality of peripheral circuits, wherein at least one of the peripheral circuits is configured to: control operation of an external device; determine whether or not the operation of the external device has ended without an error; enter a standby mode to accept a next trigger signal when the operation of the external device ended without an error; and generate an interrupt signal to interrupt the central processing unit when the operation of the external device ended with an error.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: March 28, 2017
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Masato Soshi
  • Patent number: 9606853
    Abstract: In an embodiment, a computing device may include a memory device that may be rendered unusable after a certain number of operations are performed on the memory device. The computing device may incorporate one or more techniques for protecting the memory device. Processing logic contained in the computing device may be configured to implement the techniques. The techniques may include, for example, acquiring a request to write or erase information stored in a memory device contained in a first computing device, saving the request for execution after a user visible event has been generated on the first computing device, generating the user visible event on the first computing device, and executing the saved request after the user visible event has been generated. In addition, the techniques may include reporting the request. The request may be reported to, for example, an anti-malware agent.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Nitin V. Sarangdhar, Sudhakar Otturu
  • Patent number: 9606854
    Abstract: An insider attack resistant system for providing cloud services integrity checking is disclosed. In particular, the system utilizes an automated integrity checking script and virtual machines to check the integrity of a service. The system may utilize the integrity checking script and virtual machines to execute a set of operations associated with the service so as to check the integrity of the service. When executing the set of operations, the system may only have access to the minimum level of access to peripherals that is required for each operation in the set of operations to be executed. After each operation is executed, the system may log each result for each operation, and analyze each result to determine if a failure exists for any of the operations. If a failure exists, the system may determine that a change in an expected system behavior associated with the service has occurred.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: March 28, 2017
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: Thusitha Jayawardena, Jeffrey E. Bickford, Mikhail Istomin, John Liefert, Gokul Singaraju, Christopher Van Wart
  • Patent number: 9606855
    Abstract: Corruption of program stacks is detected by using guard words placed in the program stacks. A called routine executing on a processor checks a guard word in a stack of a calling routine. The checking determines whether the guard word has an expected value. Based on determining the guard word has an unexpected value, an indication of corruption of the stack is provided. Some routines, however, may not support use of guard words. Thus, routines that are interlinked may have differing protection capabilities. A determination is made as to the differing protection capabilities, an indication of the same is provided, and the routines are executed without failing due to the differing protection capabilities.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karl J. Duvalsaint, Michael K. Gschwind, Valentina Salapura
  • Patent number: 9606856
    Abstract: A method, computer program product, and system to control event logging and error recovery in a system including adapters, ports, and channels are described. The method includes storing a recovery threshold for each event type among a plurality of event types and storing a level-specific logging threshold for each event type, implementing event handlers for each of the channels, the ports, and the adapters of the system, and implementing a threshold manager for the events identified by the event handlers based on the level-specific logging threshold and the recovery threshold for each of the respective event types of each of the events. For any identified event corresponding with a given event type, the implementing the threshold manager includes considering the recovery threshold and the level-specific logging threshold at every level regardless of a level at which the identified event is identified.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Richard K. Errickson, Patrick J. Sugrue, Peter K. Szwed
  • Patent number: 9606857
    Abstract: An electronic control unit includes first and second devices. A transmitter of the first device transmits data to a receiver of the second device by start-stop synchronization communication. On detecting a communication error, the second device transmits a communication stop signal to the first device, recovers the receiver, and transmits a restart signal to the first device when the receiver is recovered. Upon receipt of the communication stop signal, the first device stops the transmitter and initializes a transmission buffer, and commands the transmitter to restart transmitting the data upon receipt of the communication restart signal from the second device.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: March 28, 2017
    Assignee: DENSO CORPORATION
    Inventor: Kenji Mochizuki
  • Patent number: 9606858
    Abstract: A processing module encodes data using a dispersed storage error coding function to produce a set of encoded data slices and identifies storage units for storage of the set of encoded data slices. The processing module determines that a storage unit of the storage units is unavailable, where the storage unit is targeted to store an encoded data slice of the set of encoded data slices. The processing module selects a foster storage unit of the storage units for temporarily storing the encoded data slice. When the storage unit is available, the processing module transfers the encoded data slice from the foster storage unit to the storage unit.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason K. Resch, Andrew Baptist, Ilya Volvovski
  • Patent number: 9606859
    Abstract: In an embodiment, a method for performing forward error correction (FEC) on protected data packets is disclosed. The method involves creating a FEC table having columns for application data and columns for error-correction data (EC data). Then, a number of protected application data packets are received and placed in the FEC table. If an application data packet is received, then the application data from the packet is placed in the application data column. If an application data packet is not received, generated zeroes are placed in the application data column. Once the application data columns of the FEC table are full, EC data corresponding to the application data is received and placed in the EC data columns of the FEC table. The rows of the FEC table are then fed to the decoder for error correction.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: March 28, 2017
    Assignee: NXP B.V.
    Inventors: Joerg Fischer, Dirk Johannes van Ginkel
  • Patent number: 9606861
    Abstract: A plurality of data words are written into a TCAM; each has binary digits and don't-care digits. Contemporaneously, for each of the words: a first checksum is calculated on the binary digits; and the following are stored in a corresponding portion of a RAM: an identifier of the binary digits and the first checksum. The ternary content-addressable memory is queried with an input word. Upon the querying yielding a match, further steps include retrieving, from the random-access memory, corresponding values of the identifier of the binary digits and the first checksum; computing a second checksum on the input word, using the identifier of the binary digits; and if the second and first checksums are not equal, determining in real time that the match is a false positive.
    Type: Grant
    Filed: March 28, 2015
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION ARMONK
    Inventors: Bulent Abali, Bartholomew Blaner
  • Patent number: 9606863
    Abstract: Embodiments of apparatus, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 28, 2017
    Assignee: SMART High Reliability SOlutions, LLC
    Inventor: Ajoy Aswadhati
  • Patent number: 9606864
    Abstract: A nonvolatile memory device includes a memory cell array including a selected page including multiple error correction code (ECC) units, and a voltage generation unit configured to generate a read voltage to read data from the selected page. Read voltage levels are set individually for the respective ECC units according to data detection results for each of the ECC units. During a read retry section performed with respect to selected ECC units of the selected page for which read errors have been detected, a re-read operation of the selected ECC units is performed according to the respective read voltage levels set for the selected ECC units.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Yeon Lee, Hee-Woong Kang, Jong-Nam Baek, San Song
  • Patent number: 9606865
    Abstract: Apparatus and methods implemented therein use an ECC procedure to verify and correct errors in data corresponding to pre-programmed configuration data. Verification and correction is performed in a memory system comprising a non-volatile memory (NVM) and a read only memory (ROM). The NVM comprises a plurality of memory pages. On detecting a power-on reset (POR) command at the memory system, a determination is made whether the memory system has previously received the POR command from a host. When it is determined that the memory system has not previously received the POR command from the host, pre-programmed configuration data is read from the ROM and the memory system is initialized using the pre-programmed configuration data. An error correction code (ECC) is generated for the pre-programmed configuration data and the pre-programmed configuration data including the ECC is store in one of the plurality of pages of the NVM memory.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: March 28, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Nian Yang, Abhijeet Manohar, Daniel Edward Tuers
  • Patent number: 9606866
    Abstract: Method of defining a layout mapping function for a parity distributed RAID array including target objects, the layout mapping function defining the mapping of the stripe group-address space to the target-address space in the array and including a matrix defining a unit space across target objects, the matrix includes columns defining the objects and rows defining equally-offset sequential units on the objects, the method including: specifying P target objects, where P>1; b) specifying A target objects as spare space, where A<P and A?1; defining a sub-matrix of P? columns, where P?=P?A; defining a layout of stripe groups across the P? target objects in the sub-matrix, each stripe group comprising data units and parity units; adding A columns, representative of the A spare space target objects, to the sub-matrix to form a complete matrix defining the layout mapping function; and implementing the layout mapping function on the objects.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: March 28, 2017
    Assignee: XYRATEX TECHNOLOGY LIMITED
    Inventor: Eugene Mathew Taranta, II
  • Patent number: 9606867
    Abstract: When an access metric regarding an encoded data object exceeds an access threshold, a method begins by a processing module of a dispersed storage network (DSN) retrieving encoded data slices of a first plurality of sets of encoded data slices and recovering the data object utilizing first dispersed storage error encoding parameters. The method continues with the processing module re-encoding the recovered data object using second dispersed storage error encoding parameters to produce a re-encoded data object, where the re-encoded data object includes a second plurality of sets of encoded data slices. The method continues with the processing module outputting the second plurality of sets of encoded data slices to storage units of the DSN for storage therein and sending a message to retrieving devices of the DSN, where the message indicates use of the second plurality of sets of encoded data slices for the data object.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ilya Volvovski, Bruno Hennig Cabral, Manish Motwani, Thomas Darrel Cocagne, Timothy W. Markison, Gary W. Grube, Wesley Leggette, Jason K. Resch, Michael Colin Storm, Greg Dhuse, Yogesh Ramesh Vedpathak, Ravi Khadiwala
  • Patent number: 9606868
    Abstract: A block of data is partitioned into a plurality of sub-blocks each including a logical array having rows and columns of data symbols, encoded using a row linear block code and a column linear block code. Each product codeword includes a logical array of code symbols having rows which include respective row codewords and columns which include respective column codewords. The product codewords are encoded by encoding groups of L symbols, using a rate-L/(L+M) linear block code to produce a plurality of (L+M)-symbol codewords which are logically arranged in nQ encoded blocks (where n is an integer greater than zero). Each of the nQ encoded blocks includes an array having rows and columns of code symbols in which each column includes a codeword of the column code.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roy D. Cideciyan, Simeon Furrer, Mark A. Lantz, Keisuke Tanaka
  • Patent number: 9606869
    Abstract: A method includes dividing a data file into a plurality of data regions. For each data region, the method includes determining a segmentation approach; determining a dispersed storage error encoding function; segmenting the data region into a plurality of data segments in accordance with the segmentation approach; and dispersed storage error encoding the plurality of data segments to produce a plurality of sets of encoded data slices in accordance with the dispersed storage error encoding function. The method includes creating a segment allocation table (SAT) for the data file and dispersed storage error encoding the segment allocation table to produce a set of encoded SAT slices. The method includes outputting the set of encoded SAT slices with at least one of the pluralities of sets of encoded data slices for storage in storage units of the DSN.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ilya Volvovski, Andrew Baptist, Wesley Leggette, Jason K. Resch