Abstract: A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.

Abstract: Techniques are provided for granular load and refresh of columnar data. In an embodiment, a particular data object that contains particular data formatted different from column-major format is maintained, the particular data including first data and second data. First and second data objects contain the first and second data, respectively, organized in the column-major format. In response to changes being committed to the first data in the particular data object, invalidating one or more rows of the first data object. In response to a number of invalidated rows of the first data object exceeding a threshold, automatically performing a refresh operation on the first data object independent of any refresh operation on the second data object.

Abstract: A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry includes identifiers of multiple possible actions that can be taken in response to a systemwide combined response. Master logic issues a memory access request on a system fabric of the data processing system. The master logic, responsive to receiving the systemwide combined response and a selection of one of the multiple possible actions from a source of the memory access request prior to receipt of the systemwide combined response, selects the particular entry based on the systemwide combined response and selects one of the multiple possible actions identified in the particular entry based on the received selection. The master logic services the memory access request in accordance with the systemwide combined response by performing the selected one of the multiple possible actions.

Abstract: An information processing device includes a plurality of processors including an Acquire side processor and a Release side processor, and a shared memory. The Acquire side processor and the Release side processor includes a cache, a memory access control unit in the Release side processor configured to issue a StoreFence instruction for requesting a guarantee of completing the cache invalidation by the Acquire side processor, a memory access control unit in the Acquire side processor configured to issue a LoadFence instruction in response to the StoreFence instruction for guaranteeing completion of the cache invalidation in accordance with the invalidation request from the shared memory after completing a process for the cache invalidation, and an invalidation request control unit configured to perform a process for invalidating the cache in accordance with the invalidation request from the shared memory.

Abstract: The exemplary embodiments described herein relate to supporting fast and deterministic execution and simulation in multi-core environments. Specifically, the exemplary embodiments relate to systems and methods for implementing determinism in a memory system of a multithreaded computer. A exemplary system comprises a plurality of processors within a multi-processor environment, a cache memory within the processor and including metadata, and a hardware check unit performing one of a load check and a store check on the metadata to detect a respective one of a load metadata mismatch and a store metadata mismatch, and invoking a runtime software routine to order memory references upon a detection of one of the load metadata mismatch and the store metadata mismatch.

Abstract: In one embodiment, a processor includes a caching home agent (CHA) coupled to a core and a cache memory and includes a cache controller having a cache pipeline and a home agent having a home agent pipeline. The CHA may: receive, in the home agent pipeline, information from an external agent responsive to a miss for data in the cache memory; issue a global ordering signal from the home agent pipeline to a requester of the data to inform the requester of receipt of the data; and report issuance of the global ordering signal to the cache pipeline, to prevent the cache pipeline from issuance of a global ordering signal to the requester. Other embodiments are described and claimed.

Abstract: A system for pre-fetching a data frame from a system memory to a cache memory includes a processor, a queue manager, and a pre-fetch manager. The processor issues a de-queue request associated with the data frame. The queue manager receives the de-queue request, identifies a frame descriptor associated with the data frame, and generates a pre-fetch hint signal. The pre-fetch manager receives the pre-fetch hint signal and generates a pre-fetch signal and enables the cache memory to pre-fetch the data frame. Subsequently, the queue manager de-queues the frame descriptor. The processor receives the frame descriptor and reads the data frame from the cache memory.

Abstract: A system includes a set-associative storage container and a processor configured to generate a vector that is a random number. Two or more residue functions are applied to the vector that each produces a state signal including a different number of states based on the vector. A set status is determined that identifies whether each set of the set-associative storage container is enabled or disabled. One of the state signals is selected that has a same number of states as a number of the sets that are enabled. The selected state signal is mapped to the sets that are enabled to assign each of the states of the selected state signal to a corresponding one of the sets that are enabled. A set selection of the set-associative storage container is output based on the mapping to randomly select one of the sets that are enabled from the set-associative storage container.

Abstract: A memory system includes: a memory controller which executes a data access process with an external device using an access unit; a first memory which is connected to the memory controller via a bus and has a first latency; and a second memory which is connected to the memory controller via a bus and has a second latency longer than the first latency. The access unit comprises a first access size assigned to the first memory and a second access size assigned to the second memory. The memory controller executes a data access process with the first memory using the first access size, and executes a data access process with the second memory using the second access size.

Abstract: Embodiments of the invention relate to leveraging disk controller cache memory to simulate non-volatile random access memory. At least one logical block address in cache memory of the disk controller is designated and set aside as permanently dirty. Read operations may be supported with data in the cache memory; including data retained in any block address designated as permanently dirty. Write operations may also be supported by storing the write data in the logical block address designated as permanently dirty.

Abstract: In one embodiment, a system includes a disk cache and a controller configured to create a cache resident partition in the disk cache, the cache resident partition being configured to store data thereto that is not subject to HSM, manage the cache resident partition to have a size that is greater than a first minimum size and less than or equal to a total size of the disk cache, receive data to store to the disk cache, store the data to the cache resident partition at least initially, create tape-managed partitions in the disk cache, each of the tape-managed partitions being configured to store data that is subject to HSM, and manage the tape-managed partitions to have a size that is greater than a second minimum size and less than or equal to a total size of the disk cache less a size of all other partitions combined.

Abstract: Some implementations disclosed herein provide techniques and arrangements for indicating a length of an instruction from an instruction set that has variable length instructions. A plurality of bytes that include an instruction may be read from an instruction cache based on a logical instruction pointer. A determination is made whether a first byte of the plurality of bytes identifies a length of the instruction. In response to detecting that the first byte of the plurality of bytes identifies the length of the instruction, the instruction is read from the plurality of bytes based on the length of the instruction.

Abstract: A storage device includes a magnetic storage unit storing data, a semiconductor storage unit, and a controller configured to determine whether or not to control the semiconductor storage unit to store a portion of the data, based on history of access to the data, and control the semiconductor storage unit to store the portion of the data according to the determination.

Abstract: An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

Abstract: Mechanisms are provided for performing a matrix operation. A processor of a data processing system is configured to perform cluster-based matrix reordering of an input matrix. An input matrix, which comprises nodes associated with elements of the matrix, is received. The nodes are clustered into clusters based on numbers of connections with other nodes within and between the clusters, and the clusters are ordered by minimizing a total length of cross cluster connections between nodes of the clusters, to thereby generate a reordered matrix. A lookup table is generated identifying new locations of nodes of the input matrix, in the reordered matrix. A matrix operation is then performed based on the reordered matrix and the lookup table.

Abstract: A method for preventing non-temporal entries from entering small critical structures is disclosed. The method comprises transferring a first entry from a higher level memory structure to an intermediate buffer. It further comprises determining a second entry to be evicted from the intermediate buffer and a corresponding value associated with the second entry. Subsequently, responsive to a determination that the second entry is frequently accessed, the method comprises installing the second entry into a lower level memory structure. Finally, the method comprises installing the first entry into a slot previously occupied by the second entry in the intermediate buffer.

Abstract: Methods, systems, and computer readable media generalize control registers in the context of memory address translations for I/O devices. A method includes maintaining a table including a plurality of concurrently available control register base pointers each associated with a corresponding input/output (I/O) device, associating each control register base pointer with a first translation from a guest virtual address (GVA) to a guest physical address (GPA) and a second translation from the GPA to a system physical address (SPA), and operating the first and second translations concurrently for the plurality of I/O devices.

Abstract: Various systems and methods for adjusting threshold access frequency based on cache pressure are disclosed. The threshold access frequency is adjusted based on a block of data in a storage volume that has an access frequency matching or exceeding the threshold access frequency. The threshold access frequency is used to determine whether the block of data should be inserted into the cache from the storage volume.

Abstract: A method is used in managing caches in storage systems. A set of block entries is reserved in a reserved block entries list of a storage system. The reserved block entries list is associated with a cache of the storage system configured to store data of the storage system. A portion of a memory of the storage system is reserved as the cache. Based on a criterion, a determination is made whether a cache entry is available for use in the cache of the storage system. Based on the determination, a block entry is selected for use from the reserved block entries list.

Abstract: A memory module secures data stored on the memory module. A request for the data from a computer system is received by the memory module. A verification key from the computer system is also received by the memory module. A reference key is retrieved by the memory module, the reference key is stored on the memory module. A comparison status is generated by the memory module by comparing the verification key with the reference key. A response is sent to the computer by the memory module that is dependent upon the comparison status.

Abstract: An embodiment includes at least one machine readable medium on which is stored code that, when executed enables a system to initialize a trusted loader enclave (TL) and a measurement and storage manager enclave (MSM) within a memory of the system, to receive by the MSM a TL measurement of the TL from a trusted processor of the system, to determine whether to establish a secure channel between the MSM and the TL based at least in part on the TL measurement, and responsive to a determination to establish the secure channel, to establish the secure channel and store particular code in the TL. Additional embodiments are described and claimed.

Abstract: A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the instruction to a binary translator. The binary translator includes logic to determine whether the instruction includes a control-flow instruction, identify a source address of the instruction, identify a target address of the instruction, determine whether the target address is a known destination based upon the source address, and determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address. The target address includes an address to which execution would indirectly branch upon execution of the instruction.

Abstract: A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.

Abstract: An external storage device includes a memory, a controller, a first interface, a second interface, a first switching module, and a second switching module. The controller is coupled to the memory. The first interface is used to connect to a first electronic device. The second interface used to connect to a second electronic device. The first switching module is coupled to the controller, the first interface, and the second interface. The second switching module is coupled to the controller, the first interface, the second interface, and the first switching module. When the first interface is electrically connected to a first electronic device and the second interface is electrically connected to the second electronic device, the first electronic device charges the controller and the second electronic device through the first switching module, and the first electronic device accesses the memory through the second switching module and the controller.

Abstract: A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory buffer through a first connection. The second memory buffer has a third high speed memory channel and a fourth high speed memory channel. The first connection connects the first high speed memory channel and the third high speed memory channel. A first memory controller is connected to the first memory buffer through the second high speed memory channel. A second memory controller is connected to the second memory buffer through a second connection. The second connection is connected to the second memory buffer through the fourth high speed memory channel. A first memory module set is connected to the first memory buffer and a second memory module set is connected to the second memory buffer.

Abstract: The access controller conducts arbitration between first nodes, each of which is attempting to transmit data to any of second nodes as destinations through a network of buses. The access controller includes: a buffer which receives the data that have been provided by the first nodes with mutually different required qualities and destinations, classifies the data according to their destinations and required qualities, and stores the classified data separately; an inter-class arbitrator which sequentially selects one of the required qualities of the data after another in the order of their severity; an inter-destination arbitrator which selects the destinations of the data to be transmitted and gets the transmission quantities of the data distributed among the destinations; and a transmission controller which controls transmission of the data based on the required qualities selected by the inter-class arbitrator and the destinations selected by the inter-destination arbitrator.

Abstract: A system, method, and computer readable medium for sharing bandwidth among executing application programs across a packetized bus for packets from multiple DMA channels includes receiving at a network traffic management device first and second network packets from respective first and second DMA channels. The received packets are segmented into respective one or more constituent CPU bus packets. The segmented constituent CPU bus packets are interleaved for transmission across a packetized CPU bus.

Abstract: Apparatus and methods for serial interfaces are provided. In one embodiment, an integrated circuit operable to communicate over a serial interface is provided. The integrated circuit includes analog circuitry, registers for controlling the operation of the analog circuitry, and a distributed slave device including a primary block and a secondary block. The registers are accessible over the serial interface using a shared register address space. Additionally, the primary block is electrically connected to the serial interface and to a first portion of the registers and the secondary block is electrically connected to the primary block and to a second portion of the registers.

Abstract: Structures and methods herein insert one or more parallel “recessive nulling” driver impedances across a controller area network (CAN) bus starting at the time of a dominant-to-recessive data bit transition and extending for a selected recessive nulling time period. Doing so increases a rate of decay of a CAN bus dominant-to-recessive differential signal waveform, permits a shortened recessive bit time period, and allows for increased CAN bus bandwidth. Various modes of operation are applicable to various CAN bus node topologies. Recessive nulling may be applied to only the beginning portion of a recessive bit following a dominant bit (“LRN mode”) or to the entire recessive bit time (“HRN mode”). And, some embodiments may apply LRN operations to some recessive CAN frame bits and HRN operations to others.

Abstract: A universal interconnection scheme enables system architecture modularization with a hot-pluggable external computing module, such as a PC-on-a-card device using USB type-C technology. With the flexibility to interchange the system computing module with an external module, system performance can be augmented to fulfill the essential needs of the user, whether the system is a portable low-power tablet device, a smartphone, a wearable device such as an Internet of Things device, or a high-performance PC.

Abstract: A verification environment enables verification of runtime switch-over—i.e., a switch-over without restarting the device under test—between multiple I/O protocols that share a same physical interface. The device under test can be a switch unit having multiple logical protocol processing units and a logical protocol multiplexor. The verification environment includes a switch-over detector which monitors the state of the device under test, and a switch-over controller that controls the switch-over sequence by pausing and re-starting traffic on all or specific protocol drivers of the verification environment.

Abstract: An interface controller, coupling a device main body of an external electronic device to a host, is disclosed, which transmits a termination-on signal to the host prior to a mechanically stable state of a device main body of the external electronic device. When the device main body has not reached the mechanically stable state yet, the interface controller responds to the host with default link information in a delayed manner. The default link information is contained in the interface controller. When the device main body reaches the mechanically stable state, the interface controller transmits specific link information retrieved from the device main body to the host.

Abstract: An audio system includes a docking cradle for receiving and supporting a portable device. The docking cradle includes an interface for providing a connection for receiving audio content from the portable device. The docking cradle is configured to be wirelessly coupled to a first speaker package for transmitting wireless signals containing audio content between the docking cradle and the first speaker package.

Abstract: Method, apparatus, and computer program product embodiments of the invention are disclosed for entering an accessory docking mode.

Abstract: Using relatively inexpensive, external resistor networks, an electronic device, such as an FPGA, can be configured to use non-MIPI interfaces to communicate with one or more MIPI-compliant devices, such as video sources (e.g., cameras) and sinks (e.g., displays). High-speed (HS) and low-power (LP) MIPI signaling for each MIPI clock/data lane is supported by a set of one or more non-MIPI interfaces, such as LVDS and/or LVCMOS receivers, transmitters, and/or transceivers, and an appropriate, corresponding, external resistor network. For configurations in which the resistor-configured electronic device can handle high-speed MIPI data from a MIPI-compliant device, the electronic device can detect transitions in the MIPI mode of the MIPI-compliant device. In some configurations, the resistor-configured electronic device can provide high-speed MIPI data to a MIPI-compliant device. In either case, the electronic device configures the non-MIPI interfaces to support the current MIPI HS/LP mode.

Abstract: Techniques for embedded high speed serial interface methods are described herein. The method includes issuing a single-ended one (SE1) signal on each of a pair of embedded high speed serial interface data lines, the SE1 indicating a register access protocol (RAP) message follows the SE1 signal. The method also includes accessing a register of an embedded high speed serial interface component based on the RAP message.

Abstract: A listing of data is displayed in a tablet swiping calculator function display with the listing of data including two or more numerical data entries. A capability to select at least one mathematical operation is provided through the tablet swiping calculator function display along with the capability to select at least two of the two or more numerical data entries through the tablet swiping calculator function display. When the at least two of the two or more numerical data entries are selected, the selected mathematical operation is automatically performed on the selected numerical data entries and the results are displayed on the tablet swiping calculator function display.

Abstract: A method of linking a task of an electronic device and the electronic device are provided. The method includes determining whether generation of an event satisfying a predetermined condition is detected; selecting another electronic device that is linkable to the electronic device when the generation of the event satisfying the predetermined condition is detected; and generating task environment information of an application and transmitting the task environment information to the other selected electronic device.

Abstract: A device supporting big data in a process plant includes an interface to a communications network, a cache configured to store data observed by the device, and a multi-processing element processor to cause the data to be cached and transmitted (e.g., streamed) for historization at a unitary, logical centralized data storage area. The data storage area stores multiple types of process control or plant data using a common format. The device time-stamps the cached data, and, in some cases, all data that is generated or created by or received at the device may be cached and/or streamed. The device may be a field device, a controller, an input/output device, a network management device, a user interface device, or a historian device, and the device may be a node of a network supporting big data in the process plant. Multiple devices in the network may support layered or leveled caching of data.

Abstract: Provided are a computer program product, system, and method for indicating a sending buffer and receiving buffer in a message to use to validate the message in the receiving buffer. A receiving node includes a receive buffer for each of a plurality of external adaptors in external nodes. The receive buffers store messages from the external adaptors. Each of the messages includes an indicated receiving adaptor to receive the message and an indicated sending adaptor that sends the message. A determination is made as to whether the sending adaptor that sent the message comprises the indicated sending adaptor and that a receiving adaptor that received the message comprises the indicated receiving adaptor. An error is indicated for the message in response to determining that at least one of the sending and receiving adaptors that sent and received the message, respectively do not comprise the indicated sending and receiving adaptors, respectively.

Abstract: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.

Abstract: Instructions and logic provide vector compress and rotate functionality. Some embodiments, responsive to an instruction specifying: a vector source, a mask, a vector destination and destination offset, read the mask, and copy corresponding unmasked vector elements from the vector source to adjacent sequential locations in the vector destination, starting at the vector destination offset location. In some embodiments, the unmasked vector elements from the vector source are copied to adjacent sequential element locations modulo the total number of element locations in the vector destination. In some alternative embodiments, copying stops whenever the vector destination is full, and upon copying an unmasked vector element from the vector source to an adjacent sequential element location in the vector destination, the value of a corresponding field in the mask is changed to a masked value. Alternative embodiments zero elements of the vector destination, in which no element from the vector source is copied.

Abstract: A method and device for dynamically altering the signal-space-to-physical-space mapping database of a set of access points for use in localizing of an object, by obtaining a location profile for the object and obtaining an estimated location of an object by measuring the signal parameter induced by at least one access point and using the signal-space-to-physical-space mapping database for deriving an estimated location from the measured signal parameter, and determining whether the obtained estimated location complies with the obtained location profile for the object. If the obtained estimated location does not comply with the location profile, the mapping database is dynamically adjusted to obtain an adjusted signal-space-to-physical-space mapping database based on a difference between the measured signal parameter and the signal parameter corresponding with the signal space for the location expected based on the location profile.

Abstract: A method for evaluating a trajectory function to be followed by a physical system includes providing the trajectory function; determining a set of sampling points by sampling a trajectory based on the trajectory function in the time domain; associating a cell to each of the sampling points; assessing at least one cell metric for each of the cells; aggregating the at least one cell metric of the cells to obtain an aggregated metric measure; and evaluating the trajectory as determined by the provided trajectory function depending on the one or more aggregated metric measures.

Abstract: Embodiments include methods, and computer program products of a visual modeler of mathematical optimization. Aspects include: analyzing requirements of a visual model of mathematical optimization, designing the visual model of mathematical optimization in graphical form using a visual interface, visualizing the visual model of mathematical optimization model, generating computer code for the solution of the optimization model, and providing output of the visual model of the mathematical optimization from the relevant solver. Designing may include: collecting required data in graphical form using the visual interface and from databases connected to the visual interface, designing objects manually using simple mathematical notation by an expert user, using descriptions in words for later implementation by an inexperienced user, and selecting from a list of standard object types.

Abstract: A semiconductor device includes a plurality of spin units individually including a memory cell configured to store values of spins in an Ising model, a memory cell configured to store an interaction coefficient from an adjacent spin that exerts an interaction on the spin, a memory cell configured to store an external magnetic field coefficient of the spin, and an interaction circuit configured to determine a subsequent state of the spin. The spin units individually include a random number generator configured to supply the random number to the plurality of the spin units and generate two-valued simulated coefficients of two values or simulated coefficients of three values in performing an interaction to determine a subsequent state of a spin of the spin units from a value of a spin from an adjacent spin unit, an interaction coefficient, and an external magnetic field coefficient.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for presenting text and figures on a display screen. Formatting, by a computer, text in a document into a single display line, scrolling the single display line on a first portion of the display screen, wherein the display screen remains active, and displaying, on a second portion of the display screen, figures in the document referenced by the scrolled text in the single display line on the display screen.

Abstract: A system and method for tracing an electronic document within a publication. A message is associated with the electronic document as an identification thereof. The binary representation of the message is encoded as a mark defining a drawing arrangement of geometrical shapes which encode the message in the glyph of the mark e.g. a simple text, a single character, a geometrical shape etc. or in the glyph of a single character then used as a mark. The mark is added to the electronic document to generate a traceable document having the message as identification within the publication. The mark is provided at a specific location with respect to the borders and/or center of the traceable document. The traceable document thus created is added to the publication. To track the document, the publication is sent to an electronic scanner module implementing a hook. The hook searches for the geometrical shapes representing the message in the mark.

Abstract: A computer implemented system provides intelligent formatting of footnotes in electronic documents. The system includes a display device that displays an electronic document in a graphical user interface, a user interface, and a processor. The processor controls the display device and the user interface to display, in response to user input, a footnote editing interface that allows a user to create new footnotes and edit existing footnotes. The system provides multi-user access to a single document in which individual sections of the document may be in active, inactive, and/or locked states, where users perform activities as permitted by a combination of user authorization rights and these states. The footnotes may reference multiple sections on one or more pages of a document, are formatted so that each footnote resides on only a single page, and may display an obscured or blank area for footnotes originating in other sections.

Abstract: A minimum font size to display for a specific user is received, for example as entered through a user interface. The retrieval of webpages by a web browser on a computer system is monitored. For each specific view of a retrieved webpage to be displayed, the text in the specific view is resized based on the minimum font size for the user. Text in the smallest font in the view is resized to the minimum font size for the specific user. Larger text is resized so that the proportionality between different font sizes in the view is maintained. The view of the retrieved webpage with the resized text is displayed to the user. As the user scrolls through a retrieved webpage, the text of each view is resized, and the current view of the retrieved webpage is displayed with the resized text.