Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the formation of a p-n junction in a conductive layer. The method may allow for the production of semiconductor memory devices of reduced size.

Abstract: A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.

Abstract: A multi-layered semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor layer, a first insulator layer, a second semiconductor layer, a second insulator layer, and a third semiconductor layer are formed over a substrate. A first transistor comprises the first semiconductor layer, the first insulator layer, and the second semiconductor layer, and a second transistor comprises the second semiconductor layer, the second insulator layer, and the third semiconductor layer.

Abstract: The present disclosure relates to the field of liquid crystal display, and provides a method for manufacturing a TFT and the TFT thereof. The TFT includes: a base substrate; a gate electrode with a three-dimensional structure formed on the base substrate; a gate insulating layer for completely covering a top face and two side faces of the gate electrode; a semiconductor layer for completely covering a top face and two side faces of the gate insulating layer; a buffer layer for covering a top face and two side faces of the semiconductor layer at two ends of the semiconductor layer; and source and drain electrodes for completely covering a top face and two side faces of the buffer layer, wherein the semiconductor layer of the TFT is of a three-dimensional structure.

Abstract: A gate all around (GAA) device structure, vertical gate all around (VGAA) device structure, horizontal gate all around (HGAA) device structure and fin field effect transistor (FinFET) device structure are provided. The VGAA device structure includes a substrate and an isolation structure formed in the substrate. The VGAA device structure also includes a first transistor structure formed on the substrate, and the first transistor structure includes a vertical structure. The vertical structure includes a source region, a channel region and a drain region, and the channel region is formed between the source region and the drain region. The channel region has a horizontal portion and a sloped portion sloping downward toward the isolation structure. The VGAA device structure further includes a gate stack structure wrapping around the channel region.

Abstract: An object is to use an electrode made of a less expensive material than gold (Au). A semiconductor device comprises: a first titanium layer that is formed to cover at least part of a semiconductor layer and is made of titanium; an aluminum layer that is formed on the first titanium layer on opposite side of the semiconductor layer and mainly consists of aluminum; a titanium nitride layer that is formed on the aluminum layer on opposite side of the first titanium layer and is made of titanium nitride; and an electrode layer that is formed on the titanium nitride layer on opposite side of the aluminum layer and is made of copper.

Abstract: A thin film transistor display panel according to an exemplary embodiment of the present invention includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed on the first insulating layer, a second insulating layer formed on the semiconductor layer, and a gate electrode formed on the second insulating layer, in which the first insulating layer includes a light blocking material, and a thickness of the first insulating layer is greater than or equal to a thickness of the second insulating layer.

Abstract: A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.

Abstract: An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10?5-10?7 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm?3 and less than approximately 10?8 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm?3.

Abstract: An integrated circuit device includes a first transistor structure formed in a memory region (e.g., an embedded memory region) of a die. The first transistor structure includes a substrate (e.g., a planar substrate of a planar FET or a fin of a FinFET) and a first gate. The first gate includes a dipole layer proximate to the substrate and a barrier layer proximate to the dipole layer. The integrated circuit device further includes a second transistor structure formed in a logic device region of the die. The second transistor structure includes a second gate that includes an interface layer, a dielectric layer, and a cap layer. The dielectric layer is formed between the cap layer and the interface layer.

Abstract: An organic light emitting display device includes a substrate, a first transistor disposed on the substrate in the opaque region, a second transistor disposed on the substrate in the opaque region, the second transistor being adjacent to the first transistor along a first direction, and a capacitor disposed on the substrate in the opaque region, the capacitor being adjacent to the first transistor along a second direction different from the first direction. Here, the capacitor may include a first capacitor electrode, a dielectric structure including silicon oxynitride and a second capacitor electrode.

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*ND*WN=q*NA*WP and a punch through condition of WP<2*WD*[ND/(NA+ND)] where ND and WN represent the doping concentration and the thickness of the N type layers 160, while NA and WP represent the doping concentration and thickness of the P type layers; WD represents the depletion width; and q represents an electron charge, which cancel out. This device allows for a near ideal rectangular electric field profile at breakdown voltage with sawtooth like ridges.

Abstract: An insulated gate bipolar transistor (IGBT) manufacturing method comprises the following steps: providing a semiconductor substrate of a first conducting type, the semiconductor substrate having a first major surface and a second major surface (100); forming a field-stop layer of a second conducting type on the first major surface of the semiconductor substrate (200); growing an oxide layer on the field-stop layer (300); removing the oxide layer from the field-stop layer (400); forming an epitaxial layer on the field-stop layer from which the oxide layer has been removed; and then manufacturing an IGBT on the epitaxial layer (600). Before regular manufacturing of an IGBT, the surface defects of a substrate material are eliminated as many as possible before epitaxy is formed, and the quality of an epitaxial layer is improved, thereby improving the quality of the whole IGBT.

Abstract: A method of manufacturing a semiconductor device includes laminating and forming an electron transit layer, an electron supplying layer, an etching stop layer, and a p-type film on a substrate sequentially, the p-type film being formed of a nitride semiconductor material that includes Al doped with an impurity element that attains p-type, the etching stop layer being formed of a material that includes GaN, removing the p-type film in an area except an area where a gate electrode is to be formed, by dry etching to form a p-type layer in the area where the gate electrode is to be formed, the dry etching being conducted while plasma emission in the dry etching is observed, the dry etching being stopped after the dry etching is started and plasma emission originating from Al is not observed, and forming the gate electrode on the p-type layer.

Abstract: A structure having improved electrical signal isolation and linearity is disclosed. The structure includes a buried oxide (“BOX”) layer over a bulk semiconductor layer, a device layer over the buried oxide layer, a compensation implant region near an interface of the buried oxide layer and the bulk semiconductor layer, wherein the compensation implant region is configured to substantially eliminate a parasitic conduction layer near the buried oxide layer. The compensation implant region has a doping concentration of at least one order of magnitude higher than a doping concentration of the bulk semiconductor layer. The structure includes a deep trench extending through the device layer and the buried oxide layer, and a damaged implant region in the bulk semiconductor layer near the deep trench. The structure also includes at least one transistor in the device layer.

Abstract: A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; forming a barrier layer between the channel layer and the substrate; forming a recess that extends into the barrier layer through the channel layer; and forming a source layer in the recess.

Abstract: A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.

Abstract: A method of preventing contact metal from protruding into neighboring gate devices to affect work functions of the neighboring gate devices is provided includes forming a gate structure. Forming the gate structure includes forming a work function layer, and forming a gate metal layer having a void, wherein the work function layer surrounds the gate metal layer. The method further includes forming a contact plug having a contact metal directly on the gate metal layer of the first gate stack, wherein the contact metal protrudes into the void, and the work function layer prevents the contact metal from protruding into a second gate stack.

Abstract: In some embodiments, an field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Abstract: A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.

Abstract: When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 1×1013 atoms/cm2 or lower.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device comprises forming a semiconductor layer on a substrate, forming a first insulating film on the semiconductor layer, forming a metal layer on the first insulating film, forming a first portion and a second portion in the metal layer, implanting an impurity into the semiconductor layer by using the first portion and the second portion as masks, forming a gate electrode by reducing the second portion in addition to removing the first portion, and implanting an impurity into the semiconductor layer by using the gate electrode as a mask.

Abstract: A method for manufacturing a submicron semiconductor structure on a substrate, including: forming at least one template layer over a support substrate; forming one or more template structures, including one or more recesses and/or mesas, in the template layer, the one or more template structures including one or more edges extending into or out of the top surface of the template layer; coating at least part of the one or more template structures with a liquid semiconductor precursor; and, annealing and/or exposing the liquid semiconductor precursor coated template structures to light, wherein during the annealing and/or light exposure a part of the liquid semiconductor precursor accumulates by capillary forces against at least part of the one or more edges, the annealing and/or light exposure transforming the accumulated liquid semiconductor precursor into a submicron semiconductor structure extending along at least part of the one or more edges.

Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.

Abstract: A field-effect transistor (FET) includes a black phosphorus (BP) layer over a substrate. The BP layer includes channel, source, and drain regions. The FET further includes a passivation layer over and in direct contact with the BP layer. The passivation layer provides first and second openings over the source and drain regions respectively. The FET further includes source and drain contacts in direct contact with the source and drain regions through the first and second openings. The FET further includes a gate electrode over the channel region. In an embodiment, the passivation layer further includes a third opening over the channel region and the FET further includes a gate dielectric layer in direct contact with the channel region through the third opening. Methods of making the FET are also disclosed.

Abstract: A method to fabricate a semiconductor device includes forming a semiconductor fin on a substrate; forming a dummy gate material layer over the semiconductor fin; forming a contact hole in the dummy gate material layer; forming a source/drain feature in the contact hole; forming a contact feature on the source/drain feature within the contact hole; and replacing a dummy gate that is formed of the dummy gate material layer with a metal gate.

Abstract: A semiconductor device including: a P-type base region provided; an N-type emitter region provided inside the P-type base region; a P-type collector region that is provided on the surface layer portion of the N-type semiconductor layer and is separated from the P-type base region; a gate insulating film that is provided on the surface of the N-type semiconductor layer, and that contacts the P-type base region and the N-type emitter region; a gate electrode on the gate insulating film; a pillar shaped structure provided inside the N-type semiconductor layer between the P-type base region and the P-type collector region, wherein one end of the pillar shaped structure is connected to an N-type semiconductor that extends to the surface layer portion of the N-type semiconductor layer, and the pillar shaped structure includes an insulator extending in a depth direction of the N-type semiconductor layer.

Abstract: Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type. A semiconductive first buffer layer of the first conductivity type formed above the substrate. A doping concentration of the first buffer layer is greater than a doping concentration of the substrate. A second buffer layer of the second conductivity type formed above the first buffer layer. An epitaxial layer of the second conductivity type formed above the second buffer layer. One or more heavily doped regions of the second conductivity type are formed through portions of the first buffer layer from the second buffer layer and into corresponding portions of the substrate. This abstract is provided with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a pair of conductive bodies, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type. The second semiconductor layer is provided on the first semiconductor layer on the first surface side. The pair of conductive bodies are provided via an insulating film in a pair of first trenches extending across the second semiconductor layer from a surface of the second semiconductor layer to the first semiconductor layer. The third semiconductor layer is selectively formed on the surface of the second semiconductor layer between the pair of conductive bodies and has a higher second conductivity type impurity concentration in a surface of the third semiconductor layer than the second semiconductor layer.

Abstract: A semiconductor device includes: a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode. In the semiconductor substrate, a body region, a pillar region, and a barrier region are formed. The pillar region has an n-type impurity, is formed on a lateral side of the body region, and extends along a depth from a top surface of the semiconductor substrate to a lower end of the body region. The barrier region has an n-type impurity and is formed on a lower side of the body region and the pillar region. The barrier region is formed on the lower side of the pillar region. An n-type impurity concentration distribution in a depth direction in the pillar region and the barrier region has a maximum value in the pillar region. The n-type impurity concentration distribution has a folding point on a side deeper than the maximum value.

Abstract: The present disclosure provides a quantum well fin field effect transistor (QWFinFET). The QWFinFET includes a semiconductor fin over a substrate and a combo quantum well (QW) structure over the semiconductor fin. The combo QW structure includes a QW structure over a top portion of the semiconductor fin and a middle portion of the semiconductor fin. The semiconductor fin and the QW comprise different semiconductor materials. The QWFinFET also includes a gate stack over the combo QW structure.

Abstract: The invention is a field-effect transistor with a channel consisting of a thin sheet of one or more atomic layers of lateral heterostructures based on hybridized graphene. The role of lateral heterostructures is to modify the energy gap in the channel so as to enable the effective operation of the transistor in all bias regions. This solution solves the problem of the missing bandgap in single-layer and multi-layer graphene, which does not allow the fabrication of transistors that can be efficiently switched off. The possibility of fabricating lateral heterostructures, with patterns of domains with different energy dispersion relations, enables the realization of field-effect transistors with additional functionalities with respect to common transistors.

Abstract: An apparatus comprises a buried layer over a substrate, an epitaxial layer over the buried layer, a first trench extending through the epitaxial layer and partially through the buried layer, a second trench extending through the epitaxial layer and partially through the buried layer, a dielectric layer in a bottom portion of the first trench, a first gate region in an upper portion of the first trench, a second gate region in the second trench, wherein the second gate region is electrically coupled to the first gate region, a drain region in the epitaxial layer and a source region on an opposite side of the first trench from the drain region.

Abstract: A semiconductor device includes field electrode structures regularly arranged in lines in a cell area and forming a first portion of a regular pattern. Termination structures are formed in an inner edge area surrounding the cell area, wherein at least portions of the termination structures form a second portion of the regular pattern. Cell mesas separate neighboring ones of the field electrode structures from each other in the cell area and include first portions of a drift zone, wherein a voltage applied to a gate electrode controls a current flow through the cell mesas. At least one doped region forms a homojunction with the drift zone in the inner edge area.

Abstract: A semiconductor device formed in a semiconductor substrate includes a source region, a drain region, a gate electrode, and a body region disposed between the source region and the drain region. The gate electrode is disposed adjacent at least two sides of the body region, and the source region and the gate electrode are coupled to a source terminal. A width of the body region between the two sides of the body region is selected so that the body region is configured to be fully depleted.

Abstract: A tri-gate laterally-diffused metal oxide semiconductor (LDMOS), including a substrate, a P-type semiconductor region, a P-type contact region, an N-type source region, a gate dielectric layer, an N-type drift region, a first isolation dielectric layer, an N-type drain region, and a second isolation dielectric layer. The P-type semiconductor region is disposed on one end of an upper surface of the substrate, and the N-type drift region is disposed on another end of the upper surface. The P-type semiconductor region contacts with the N-type drift region. The P-type contact region and the N-type source region are disposed on one side of the P-type semiconductor region which is away from the N-type drift region, and compared with the P-type contact region, the N-type source region is in the vicinity of the N-type drift region.

Abstract: An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface. The electronic device can further include first conductive structures within each of a first trench and a second trench, a gate electrode within the first trench and electrically insulated from the first conductive structure, a first insulating member disposed between the gate electrode and the first conductive structure within the first trench, and a second conductive structure within the second trench. The second conductive structure can be electrically connected to the first conductive structures and is electrically insulated from the gate electrode. The electronic device can further include a second insulating member disposed between the second conductive structure and the first conductive structure within the second trench. Processing sequences can be used that simplify formation of the features within the electronic device.

Abstract: The invention provides a body-contact metal-oxide-semiconductor field effect transistor (MOSFET) device. The body-contact MOSFET device includes a substrate. An active region is disposed on the substrate. A gate strip is extended along a first direction disposed on a first portion of the active region. A source doped region and a drain doped region are disposed on a second portion and a third portion of the active region, adjacent to opposite sides of the gate strip. The opposite sides of the gate strip are extended along the first direction. A body-contact doped region is disposed on a fourth portion of the active region. The body-contact doped region is separated from the gate strip by a fifth portion of the active region. The fifth portion is not covered by any silicide features.

Abstract: A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a device region. A fin is formed in the device region. The fin includes top and bottom portions. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving an upper fin portion exposed. At least one isolation buffer is formed in the bottom fin portion, leaving the top fin portion crystalline, the top fin portion serves as a body of a fin type transistor. Source/drain (S/D) regions are formed in the top portions of the fin and a gate wrapping around the fin is provided.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. The method can include providing a substrate. The method can include forming a fin on the substrate. The method can include forming a dummy gate on the fin and the substrate. The method can include etching portions of the fin not located below the dummy gate. The method can include epitaxially forming doped source and drain regions on the exposed sides of the fin. The method can include forming an insulative spacer on exposed sides of the dummy gate. The method can include forming one or more metal regions adjacent to the doped source and drain regions.

Abstract: A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure. The epitaxial semiconductor material includes a first portion having a substantially conformal thickness on a lower portion of the fin structure sidewall and a second portion having a substantially diamond shape that is present on an upper surface of the source portion and drain portion of the fin structure. A spacer present on first portion of the epitaxial semiconductor material.

Abstract: A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an oxide layer formed over a substrate and a fin structure formed over the oxide layer. The fin structure is made of a semiconductor layer, and the semiconductor layer includes a first portion, a second portion and a third portion. The second portion is between the first portion and the third portion. The first portion, the second portion and the third portion construct a U-shaped trench, and the second portion is below the U-shaped trench. The FinFET device structure further includes a gate structure formed in the U-shaped trench.

Abstract: Embodiments of the present invention relate to an array substrate, a manufacturing method thereof and a display device. The manufacturing method of the array substrate comprises: preparing a base substrate; forming a gate electrode pattern on the base substrate; forming a gate insulating layer pattern on the base substrate with the gate electrode pattern formed thereon; and forming an active layer pattern, a pixel electrode pattern and source and drain patterns above the gate insulating layer pattern through a three-gray-tone mask process in one patterning process, wherein the gate electrode pattern, the active layer pattern, the source pattern and the drain pattern constitute a thin film transistor.

Abstract: The disclosure is related to a thin film transistor and a method of manufacturing the thin film transistor. The thin film transistor comprises a substrate, a gate, a gate insulation layer, a first semiconductor layer, an etch stop layer and a second semiconductor layer sequentially stacked on a surface of the substrate, and a source and a drain formed separating from each other and the source and the drain overlapping two ends of the second semiconductor layer respectively. A first via and a second via are formed on the etch stop layer corresponding to the source and the drain respectively. The source connects the first semiconductor layer through the first via; the drain connects the first semiconductor layer through the second via. The thin film transistor of the disclosure can effectively increase the on-state current of the thin film transistor and have a faster switching speed.

Abstract: The invention provides a thin film transistor, an array substrate and a display device. The thin film transistor comprises a conductive oxygen vacancy reducing layer for reducing oxygen vacancies in an active layer. The oxygen vacancy reducing layer is disposed between the active layer and a source and/or the active layer and a drain. With the oxygen vacancy reducing layer, the number of the oxygen vacancies in the active layer is decreased greatly, which improves transmission rate of carriers and simultaneously reduces value of subthreshold swing of the thin film transistor.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes an oxide semiconductor protrusion, a source, a drain, an oxide semiconductor layer, a first O-barrier layer, a gate electrode, a second O-barrier layer, and an H-barrier layer. The oxide semiconductor protrusion is disposed on an oxide substrate. The source and the drain are respectively disposed on opposite ends of the oxide semiconductor protrusion. The oxide semiconductor layer is disposed on the oxide substrate and covers the oxide semiconductor protrusion, the source, and the drain. The first O-barrier layer is disposed on the oxide semiconductor layer. The gate electrode is disposed on the first O-barrier layer and across the oxide semiconductor protrusion. The second O-barrier layer is disposed on the gate electrode. The H-barrier layer is disposed on the oxide substrate and covers the second O-barrier layer.

Abstract: The present invention provides a transistor having electrically stable characteristics. In addition, the reliability of a semiconductor device including such a transistor is increased. The semiconductor device includes a gate electrode layer, a gate insulating film over the gate electrode layer, an oxide semiconductor stacked film overlapping with the gate electrode layer with the gate insulating film provided therebetween, and a pair of electrode layers in contact with the oxide semiconductor stacked film. In the semiconductor device, the oxide semiconductor stacked film includes at least indium and includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked.

Abstract: A thin film transistor, a manufacturing method thereof and an array substrate are provided. The thin film transistor includes a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode provided on a base substrate, and along a direction perpendicular to the base substrate, the source electrode and the drain electrode are respectively provided at opposite both sides of the active layer, and the source electrode and the drain electrode contacts the active layer.

Abstract: The present invention provides a TFT and a manufacturing method thereof, an array substrate and a display device. The TFT comprises a gate, an active layer located on the gate, an ohmic contact layer located on the active layer, and a first electrode and a second electrode located on the ohmic contact layer, wherein the first electrode and the second electrode are partially overlapped with the active layer, the ohmic contact layer is located within a region where the first electrode and the second electrode are overlapped with the active layer; the active layer is partially overlapped with the gate, the active layer comprises at least one opening region partially overlapped with the gate; and the first electrode and/or the second electrode extends beyond the active layer through the at least one opening region.