Patents Issued in April 11, 2017
  • Patent number: 9620447
    Abstract: To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: April 11, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Shuuichi Kariyazaki, Ryuichi Oikawa
  • Patent number: 9620448
    Abstract: A power module is disclosed. The power module includes a magnetic assembly, a switching device, a first upper conductive element and a first sidewall conductive element. The magnetic assembly has a first magnetic core, a second magnetic core and a receiving space. The first magnetic core has a first top surface, a first bottom surface and at least one first sidewall through-hole. The second magnetic core is coupled with the first magnetic core. The receiving space is formed between the first magnetic core and the second magnetic core. The switching device is disposed on the first top surface and accommodated in the receiving space. The first upper conductive element is disposed on the first top surface of the first magnetic core and electrically connected to the switch component. The first sidewall conductive element is disposed in the first sidewall through-hole and electrically connected to the first upper conductive element.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: April 11, 2017
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Jianhong Zeng, Shouyu Hong, Min Zhou
  • Patent number: 9620449
    Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: April 11, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Patent number: 9620451
    Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: April 11, 2017
    Assignee: SK Hynix Inc.
    Inventors: Chang-Youn Hwang, Sang-Kil Kang, Ill-Hee Joe, Dae-Sik Park, Hae-Jung Park, Se-Han Kwon
  • Patent number: 9620452
    Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: April 11, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xiongfei Meng, Joon Hyung Chung, Yuancheng Christopher Pan
  • Patent number: 9620453
    Abstract: A method includes providing a semiconductor structure including a recess. The recess includes at least one of a contact via and a trench. A layer of a first metal is deposited over the semiconductor structure. An electroless deposition process is performed. The electroless deposition process removes a first portion of the layer of first metal from the semiconductor structure and deposits a first layer of a second metal over the semiconductor structure. An electroplating process is performed. The electroplating process deposits a second layer of the second metal over the first layer of second metal. A second portion of the layer of first metal remains in the semiconductor structure.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: April 11, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Axel Preusse, Romy Liske, Marcus Wislicenus, Robert Krause, Lukas Gerlich, Benjamin Uhlig, Sascha Bott
  • Patent number: 9620454
    Abstract: Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via are disclosed. Related methods are also disclosed. In particular, different metal lines in a metal layer may need to be electrically interconnected during a MOL process for an IC. In this regard, to allow for metal lines to be interconnected without providing such interconnections above the metal lines that may be difficult to provide in a printing process for example, in an exemplary aspect, an elongated or expanded via(s) is provided in a MOL layer in an IC. The elongated via is provided in the MOL layer below the metal layer in the MOL layer and extended across two or more adjacent metal layers in the metal layer of the MOL layer. Moving the interconnections above the MOL layer can simplify the manufacturing of ICs, particularly at low nanometer (nm) node sizes.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: April 11, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: John Jianhong Zhu, Kern Rim, Stanley Seungchul Song, Jeffrey Junhao Xu, Da Yang
  • Patent number: 9620455
    Abstract: A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. An ACF is deposited over the bumps and active surface of the wafer. An insulating layer can be formed between the ACF and semiconductor die. The semiconductor wafer is singulated to separate the die. The semiconductor die is mounted to a temporary carrier with the ACF oriented to the carrier. The semiconductor die is forced against the carrier to compress the ACF under the bumps and form a low resistance electrical interconnect to the bumps. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected through the compressed ACF to the bumps. The ACF reduces shifting of the semiconductor die during encapsulation.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: April 11, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 9620456
    Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a plurality of integrated circuits (Ia, Ib, Ic) formed on the wafer substrate (2). Each integrated circuit (Ia, Ib, Ic) comprises an electric circuit (24) and some of the integrated circuits (Ib, Ic) comprise, in addition to their electric circuits (24), process control modules (3) as integral parts. The process control modules (3) are employed during dicing and pick-and-place to align the dicing/pick-and-place devices.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: April 11, 2017
    Assignee: NXP B.V.
    Inventor: Heimo Scheucher
  • Patent number: 9620457
    Abstract: A method of manufacturing a semiconductor device package includes encapsulating at least partially a plurality of semiconductor chips with encapsulating material to form an encapsulation body. The encapsulation body has a first main surface and a second main surface. At least one of a metal layer and an organic layer is formed over the first main surface of the encapsulation body. At least one trace of the at least one of the metal layer and the organic layer is removed by laser ablation. The encapsulation body is then separated into a plurality of semiconductor device packages along the at least one trace.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Eva Wagner, Gottfried Beer
  • Patent number: 9620458
    Abstract: A method is provided for fabricating a photolithography alignment mark structure. The method includes providing a substrate; thrilling a first grating, a second grating, a third grating and a fourth grating in the substrate; forming a photoresist layer on a surface of the substrate; obtaining a first alignment center along a first direction and a second alignment center along a second direction based on the first grating and the fourth grating, respectively; providing a mask plate having a fifth grating pattern and a sixth grating pattern; aligning the mask plate with the substrate by using the first alignment center as an alignment center along the first direction and the second alignment center as an alignment center along the second direction; reproducing the fifth grating pattern and the sixth grating pattern in the photoresist layer; and forming a fifth grating and a sixth grating on the substrate by removing a portion of photoresist layer.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: April 11, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Boxiu Cai, Yi Huang
  • Patent number: 9620459
    Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
  • Patent number: 9620460
    Abstract: Provided are a semiconductor chip, a semiconductor package and a fabricating method thereof, which can reduce or prevent cracks from being generated or propagated due to an external pressure. The semiconductor chip includes a semiconductor substrate including a first region and a second region, a plurality of interlayer insulation layers formed on the semiconductor substrate, a first crack stopper formed in the plurality of interlayer insulation layers of the first region, an interconnector formed in the plurality of interlayer insulation layers of the second region, a pad wire formed on the plurality of interlayer insulation layers, electrically connected to the interconnector in the second region and extending to the first region, a bonding pad on the plurality of interlayer insulation layers of the first region, electrically connected to the pad wire, and a protection layer covering the pad wire and exposing the bonding pad.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 11, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Pil Noh, Jeong-Woon Kim, Seok-Ha Lee
  • Patent number: 9620461
    Abstract: A laminar structure of semiconductors comprises a silicon substrate, an epitaxial layer, a protective layer, a first layer and a second layer. The epitaxial layer is arranged above the silicon substrate and the protective layer is arranged below the silicon substrate. Thermal expansion coefficients of the epitaxial layer and the protective layer are both either greater than or less than that of the silicon substrate. The first layer is arranged between the silicon substrate and the protective layer; and the second layer is arranged between the silicon substrate and the epitaxial layer, wherein the band gap of the first layer and the second layer are both greater than 3 eV. By arranging the protective layer below the silicon substrate, stress generated between the silicon substrate and the epitaxial layer can be reduced to prevent occurrence of bending or crack. Therefore, yield can be promoted and costs can be reduced.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: April 11, 2017
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Wen-Ching Hsu, Chia-Wen Ko, Chiou-Mei Luo
  • Patent number: 9620462
    Abstract: A first cavity-down ball grid array (BGA) package includes a substrate member and an array of bond balls. The array of bond balls includes a pair of parallel extending rows of outer mesh bond balls and a row of inner signal bond balls that is parallel to the pair of rows of outer mesh bond balls. A surface-mount blocking element is disposed between the row of inner signal bond balls and the pair of rows of outer mesh bond balls. The surface-mount blocking element is either a passive or an active component of the BGA package. In one example, the first cavity-down BGA package is surface-mounted to a second cavity-down BGA package to form a package-on-package (POP) security module. The surface-mount blocking element provides additional physical barrier against the probing of the inner signal bond balls. Sensitive data is therefore protected from unauthorized access.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 11, 2017
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Ruben C. Zeta, Edgardo L. Chua Ching Chua
  • Patent number: 9620463
    Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a fan-out wafer level package (FOWLP) module or device. Intra-module shielding between individual chips within the FOWLP module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a FOWLP to ensure reliable grounding.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: April 11, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, David Francis Berdy, Mario Francisco Velez, Changhan Hobie Yun, Chengjie Zuo, Jonghae Kim, Matthew Michael Nowak
  • Patent number: 9620464
    Abstract: Antenna package structures are provided to implement wireless communications packages. For example, an antenna package includes a package carrier and a package cover. The package carrier includes an antenna ground plane and an antenna feed line. The package cover includes a planar lid having a planar antenna element formed on a first surface of the planar lid. The package cover is bonded to a first surface of the package carrier with the first surface of the planar lid facing the first surface of the package carrier, and with the planar antenna element aligned to the antenna ground plane and the antenna feed line of the package carrier, wherein the first surface of the planar lid is disposed at a distance from the first surface of the package carrier to provide an air space between the planar antenna element and the package carrier.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: April 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Christian Wilhelmus Baks, Xiaoxiong Gu, Duixian Liu, Alberto Valdes-Garcia
  • Patent number: 9620465
    Abstract: A method for forming through vias comprises the steps of forming a dielectric layer over a package and forming an RDL over the dielectric layer, wherein forming the RDL includes the steps of forming a seed layer, forming a first patterned mask over the seed layer, and performing a first metal plating. The method further includes forming through vias on top of a first portion of the RDL, wherein forming the through vias includes forming a second patterned mask over the seed layer and the RDL, and performing a second metal plating. The method further includes attaching a chip to a second portion of the RDL, and encapsulating the chip and the through vias in an encapsulating material.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo Lung Pan, Wei Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 9620466
    Abstract: A method of manufacturing an electronic device may include: forming at least one electronic component in a substrate; forming a contact pad in electrical contact with the at least one electronic component; wherein forming the contact pad includes: forming a first layer over the substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface, wherein the second layer has a lower porosity than the first layer.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 11, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Martin Mischitz, Markus Heinrici, Barbara Eichinger, Manfred Schneegans, Stefan Krivec
  • Patent number: 9620467
    Abstract: In an embodiment, a semiconductor device includes a lateral transistor device having an upper metallization layer. The upper metallization layer includes n elongated pad regions. Adjacent ones of the n elongated pad regions are coupled to different current electrodes of the lateral transistor device. The n elongated pad regions bound n?1 active regions of the lateral transistor where n?3.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Ralf Otremba, Gerhard Prechtl, Klaus Schiess
  • Patent number: 9620468
    Abstract: Various embodiments provide semiconductor packaging structures and methods for forming the same. In an exemplary method, a chip having a metal interconnect structure thereon can be provided. An insulating layer can be formed on the chip to expose the metal interconnect structure. A columnar electrode can be formed on the metal interconnect structure. A portion of the metal interconnect structure surrounding a bottom of the columnar electrode can be exposed. A diffusion barrier layer can be formed on sidewalls and a top surface of the columnar electrode, and on the exposed portion of the metal interconnect structure surrounding the bottom of the columnar electrode. A solder ball can then be formed on the diffusion barrier layer. The solder ball can wrap at least the sidewalls and the top surface of the columnar electrode.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: April 11, 2017
    Assignee: TONGFU MICROELECTRONICS CO., LTD.
    Inventors: Chang-Ming Lin, Yu-Juan Tao
  • Patent number: 9620469
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 9620470
    Abstract: A method of manufacturing a semiconductor device includes forming a barrier metal film on a surface of at least one of a first electrode of a wiring board and a second electrode of a semiconductor element, providing a connection terminal between the first and second electrodes, the connection terminal being made of solder containing tin, bismuth and zinc, and bonding the connection terminal to the barrier metal film by heating the connection terminal and maintaining the temperature of the connection terminal at a constant temperature not lower than a melting point of the solder for a certain period of time.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: April 11, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Shimizu, Seiki Sakuyama, Toyoo Miyajima
  • Patent number: 9620471
    Abstract: A power semiconductor package that includes a semiconductor die having at least two power electrodes and a conductive clip electrically and mechanically coupled to each power electrode.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Martin Standing, Robert J. Clarke
  • Patent number: 9620472
    Abstract: A method of manufacturing an electronic component includes applying solder paste to at least one electrically conductive portion of a package, applying a high-voltage depletion-mode transistor onto the solder paste, applying a low-voltage enhancement-mode transistor onto the solder paste, applying solder paste onto the high-voltage depletion-mode transistor, applying solder paste onto the low-voltage enhancement-mode transistor, applying an electrically conductive member onto the solder paste on the high-voltage depletion-mode transistor and onto the solder paste on the low-voltage enhancement-mode transistor to form an assembly, and heat treating the assembly to produce an electrical connection between the high-voltage depletion-mode transistor and the low-voltage enhancement-mode transistor via the electrically conductive member.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess, Oliver Häberlen
  • Patent number: 9620473
    Abstract: First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface of the second integrated device is positioned contiguous to the first edge surface of the first integrated device. The interconnect structures disposed on the first integrated device are in physical contact with the interconnect structures disposed on the edge surface of the second integrated device so as to provide alignment for conveying at least one signal between the optical components on the first and second integrated devices.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: April 11, 2017
    Assignee: University of Notre Dame du Lac
    Inventors: Douglas C. Hall, Scott Howard, Anthony Hoffman, Gary H. Bernstein, Jason M. Kulick
  • Patent number: 9620475
    Abstract: In one implementation, a method of fabricating a power semiconductor package is disclosed. The method includes providing a conductive carrier array including a plurality of power modules held together with connecting bars, where each of the plurality of power modules includes a control transistor, a sync transistor, and a driver IC. The method further includes overlying on the conductive carrier array a heat spreader array including a plurality of power electrode heat spreaders such that each of the plurality of power electrode heat spreaders couples a drain of the sync transistor to a source of the control transistor in each power module.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies Americas Corp
    Inventor: Eung San Cho
  • Patent number: 9620476
    Abstract: A bonding head and a die bonding apparatus having the same are disclosed. The bonding head includes a body connected to a driving section for transferring the die, a plate heater mounted to a lower surface of the body and a collet mounted to a lower surface of the plate heater and configured to hold the die using a vacuum pressure. A cooling channel is formed at the lower surface of the body, and cooling passages are formed through the body and connected with the cooling channel to supply a cooling fluid into the cooling channel and to recover the cooling fluid from the cooling channel thereby cooling the plate heater.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 11, 2017
    Assignees: SEMES CO., LTD., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hang Lim Lee, Jong Jin Weon, Soon Hyun Kim, Seung Dae Seok
  • Patent number: 9620477
    Abstract: Disclosed is a wire bonder comprising: a processor; a bond head coupled to the processor, the processor being configured to control motion of the bond head; a bonding tool mounted to the bond head, the bonding tool being drivable by the bond head to form an electrical interconnection between a semiconductor die and a substrate to which the semiconductor die is mounted using a bonding wire; and a measuring device coupled to the bond head, the measuring device being operable to measure a deformation of a bonding portion of the bonding wire as the bonding tool is driven by the bond head to connect the bonding wire to the semiconductor die via the bonding portion.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: April 11, 2017
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Keng Yew Song, Wai Wah Lee, Yi Bin Wang
  • Patent number: 9620478
    Abstract: A micro device transfer head and head array are disclosed. In an embodiment, the micro device transfer head includes a base substrate, a mesa structure with sidewalls, an electrode formed over the mesa structure, and a dielectric layer covering the electrode. A voltage can be applied to the micro device transfer head and head array to pick up a micro device from a carrier substrate and release the micro device onto a receiving substrate.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: April 11, 2017
    Assignee: Apple Inc.
    Inventors: Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law, Hsin-Hua Hu
  • Patent number: 9620479
    Abstract: A first semiconductor structure including a first bonding oxide layer having a metal resistor structure embedded therein and a second semiconductor structure including a second bonding oxide layer having a metallic bonding structure embedded therein are provided. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. Each nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layer and nitridized metallic regions located in an upper portion of either the metal resistor structure or the metallic bonding structure. The nitrogen within the nitridized metallic region located in the upper portion of the metallic bonding structure is then selectively removed to restore the upper portion of the metallic bonding structure to its original composition. Bonding is then performed to form a dielectric bonding interface and a metallic bonding interface between.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 9620480
    Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing an unplated leadframe having a contact protrusion; forming a contact pad and traces by etching the unplated leadframe; applying a trace protection layer on the contact pad and the traces; forming a recess in the trace protection layer by etching a top surface of the contact pad to a recess distance below a top surface of the trace protection layer; and depositing an external connector directly on the top surface of the contact pad.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 11, 2017
    Assignee: STATS ChipPAC Pte. Ltd
    Inventors: Garret Dimaculangan, Linda Pei Ee Chua, Byung Tai Do, Arnel Senosa Trasporto
  • Patent number: 9620481
    Abstract: A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: April 11, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel C. Edelstein, Douglas C. La Tulipe, Jr., Wei Lin, Deepika Priyadarshini, Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel
  • Patent number: 9620482
    Abstract: A semiconductor device includes a plurality of semiconductor dies stacked vertically to have a vertical height and a dielectric surrounding the stacked semiconductor dies. The semiconductor device further has a conductive post external to the stacked semiconductor dies and extending through the dielectric. In the semiconductor device, a height of the conductive post is greater than the vertical height.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: April 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Jen Chen, Hsien-Wei Chen, Der-Chyang Yeh
  • Patent number: 9620483
    Abstract: A semiconductor device including power TSVs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: April 11, 2017
    Assignee: SK hynix Inc.
    Inventors: Young Hee Yoon, Ga Young Lee
  • Patent number: 9620484
    Abstract: A semiconductor package device includes a lower package, an interposer disposed on the lower package and including a ground layer and at least one opening, and an upper package on the interposer. The lower package includes a first package substrate, a first semiconductor chip on the first package substrate, and a first molding compound layer on the first package substrate. The upper package includes a second package substrate and at least one upper semiconductor chip on the second package substrate. A heat transfer member includes a first portion disposed between the interposer and the upper package, a second portion disposed in the at least one opening of the interposer, and a third portion disposed between the interposer and the lower package.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: April 11, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Uk Kim
  • Patent number: 9620485
    Abstract: Embodiments of the invention provides a light emitting device, which comprises a backplane, an encapsulating structure, and a light emitting structure and a scattering layer disposed between the backplane and the encapsulating structure; the scattering layer is located on the light exiting side of the light emitting structure; the light emitting structure is isolated into a plurality of light emitting units, the scattering layer is isolated into a plurality of scattering units, and the plurality of light emitting units correspond to the plurality of scattering units one to one; wherein each of the light emitting units comprises a first light emitting sub-unit, a second light emitting sub-unit and a third light emitting sub-unit. The embodiments of the invention may be used for a display device and a lighting lamp, thereby increasing the light emitting area and achieving uniform mixed emergent light.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: April 11, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shang Wang, Qiuxiang Li
  • Patent number: 9620486
    Abstract: A light-emitting diode module for emitting white light includes a first light emitting diode chip for generating radiation in the blue spectral range having a first peak wavelength, a second light emitting diode chip for generating radiation in the blue spectral range having a second peak wavelength, a third light emitting diode chip for generating radiation in the red spectral range having a third peak wavelength, a first and a second phosphors disposed downstream of the first and the second light emitting diode chips, respectively. The first light emitting diode chip with the first phosphor generates a first mixed radiation and the second light emitting diode chip with the second phosphor generates a second mixed radiation. The first phosphor exhibits a first absorption maximum at a wavelength greater than the first peak wavelength. The second phosphor exhibits a second absorption maximum at a wavelength less than the second peak wavelength.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: April 11, 2017
    Assignee: OSRAM GMBH
    Inventors: Reiner Windisch, Krister Bergenek
  • Patent number: 9620487
    Abstract: Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the substrate, and an array of bank openings in the insulating layer with each bank opening including a bottom surface and sidewalls. A reflective layer spans sidewalls of each of the bank openings in the insulating layer.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: April 11, 2017
    Assignee: Apple Inc.
    Inventors: Kapil V. Sakariya, Andreas Bibl, Hsin-Hua Hu
  • Patent number: 9620488
    Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first chip, a second chip and at least one through substrate via (TSV). The first chip is electrically connected to the second chip with a first bonding pad of the first chip and a second bonding pad of the second chip. The TSV extends from a first backside of the first chip to a metallization element of the first chip. At least one conductive via is electrically connected between the TSV and the first bonding pad, and at least one elongated slot or closed space is within the at least one conductive via.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen
  • Patent number: 9620489
    Abstract: Techniques, systems, and devices are disclosed to provide multilayer platforms for integrating semiconductor integrated circuit dies, optical waveguides and photonic devices to provide intra-die or inter-die optical connectivity.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: April 11, 2017
    Assignee: CORNELL UNIVERSITY
    Inventors: Michal Lipson, Yoon Ho Lee
  • Patent number: 9620490
    Abstract: A fuse package may include a first lead frame, a second lead frame spaced apart from the first lead frame, a package body configured to cover at least a portion of the first lead frame and at least a portion of the second lead frame, a wire fuse mounted on the first lead frame and the second lead frame, and configured to electrically connect the two lead frames, and an encapsulator configured to cover the wire fuse.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 11, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seung Hwan Choi
  • Patent number: 9620491
    Abstract: An organic light emitting diode (OLED) display includes: a substrate including a plurality of organic light emitting elements; an adhesive member on at least a portion of an upper surface of the substrate; a flexible circuit board adhered to the upper surface of the adhesive member and having a portion bent to be mounted to a lower surface of the substrate; and a light blocking member at the upper surface of the substrate, wherein the light blocking member is laterally offset from the adhesive member.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: April 11, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young-Min You, Dae-Kil Park
  • Patent number: 9620492
    Abstract: A bottom package having a first semiconductor chip and first connection members; and a top package disposed over the bottom package, and having a second semiconductor chip and second connection members electrically coupled with the first connection members. The bottom package includes an interposer having electrodes arranged along edges; first bond fingers arranged by being separated from the edges of the interposer; a first semiconductor chip disposed over the interposer to expose the electrodes, and having first bonding pads; first bonding wires electrically coupling the first bonding pads and the electrodes; second bonding wires electrically coupling the electrodes and the first bond fingers; and a first encapsulation member formed to cover the first bond fingers, the upper and side surfaces of the interposer and the first semiconductor chip, and the first and second bonding wires, and having via holes which expose portions of the second bonding wires.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: April 11, 2017
    Assignee: SK HYNIX INC.
    Inventor: Jung Tae Jeong
  • Patent number: 9620493
    Abstract: A method of manufacturing a three-dimensional (3D) semiconductor includes dividing each of a plurality of wafers into a plurality of multi-dies each including a plurality of dies; checking whether each of the dies has a defect; storing a result of checking whether each of the dies has a defect and information regarding each of the multi-dies; forming virtual combined structures by combining and stacking all the multi-dies in a predetermined number of layers; forming 3D semiconductor groups by calculating yields of the combined structures based on the result of checking whether each of the dies has a defect and the information regarding each of the multi-dies, selecting a combined structure having a highest yield from among the combined structures, and stacking the multi-dies to have the same structure as the selected combined structure; and forming a 3D semiconductor chip by dividing the 3D semiconductor groups in units of dies.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: April 11, 2017
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Joonsung Yang, Soonkwan Kwon
  • Patent number: 9620494
    Abstract: Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: April 11, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daewoo Son, Chulwoo Kim
  • Patent number: 9620495
    Abstract: A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 11, 2017
    Assignee: NXP USA, Inc.
    Inventors: Patrice Besse, Alexis Huot-Marchand, Jean-Philippe Laine, Alain Salles
  • Patent number: 9620496
    Abstract: Protection circuits, device structures and related fabrication methods are provided. An exemplary protection circuit includes a first protection arrangement and a second protection arrangement. The first protection arrangement includes a first transistor having a first collector, a first emitter, and a first base coupled to the first emitter at a first node, and a second transistor having a second collector, a second emitter, and a second base coupled to the second emitter at a second node, the second collector being coupled to the first collector at a third node. The second protection arrangement is coupled electrically in series between the second node and a fourth node. The protection circuit further includes a first diode coupled between the third node and the fourth node.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: April 11, 2017
    Assignee: NXP USA, INC.
    Inventors: Weize Chen, Hubert M. Bode, Andreas Laudenbach, Kurt U. Neugebauer, Patrice M. Parris
  • Patent number: 9620497
    Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: April 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Nathan D. Jack, JunJun Li, Souvick Mitra
  • Patent number: 9620498
    Abstract: A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped-well that is disposed below and engulfing the U-shaped bend.
    Type: Grant
    Filed: July 26, 2014
    Date of Patent: April 11, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yi Su, Anup Bhalla, Daniel Ng