Patents Issued in April 11, 2017
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Patent number: 9620552Abstract: A solid-state imaging device includes a photoelectric conversion unit, a transistor, and an element separation region separating the photoelectric conversion unit and the transistor. The photoelectric conversion unit and the transistor constitute a pixel. The element separation region is formed of a semiconductor region of a conductivity type opposite to that of a source region and a drain region of the transistor. A part of a gate electrode of the transistor protrudes toward the element separation region side beyond an active region of the transistor. An insulating film having a thickness substantially the same as that of a gate insulating film of the gate electrode of the transistor is formed on the element separation region continuing from a part thereof under the gate electrode of the transistor to a part thereof continuing from the part under the gate electrode of the transistor.Type: GrantFiled: May 12, 2016Date of Patent: April 11, 2017Assignee: Sony Semiconductor Solutions CorporationInventor: Kazuichiro Itonaga
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Patent number: 9620553Abstract: A semiconductor device includes a substrate, a semiconductor layer, light-sensing devices, a transparent dielectric layer and a grid shielding layer. The semiconductor layer overlies the substrate, and has a first surface and a second surface opposite to the first surface. The semiconductor layer includes microstructures disposed on the second surface of the semiconductor layer. The light-sensing devices are disposed on the first surface of the semiconductor layer. The transparent dielectric layer is disposed on the second surface of the semiconductor layer, and covers the microstructures. The grid shielding layer extends from the first surface of the semiconductor layer toward the second surface of the semiconductor layer, and surrounds each of the light-sensing devices to separate the light-sensing devices from each other, in which a depth of the grid shielding layer is greater than two-thirds of a thickness of the semiconductor layer.Type: GrantFiled: June 15, 2016Date of Patent: April 11, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Chang Huang, Hsing-Chih Lin, Chien-Nan Tu, Yu-Lung Yeh
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Patent number: 9620554Abstract: A solid-state image pickup unit includes substrate; a red pixel including a red charge storage section; a blue pixel including a blue charge storage section; and a green pixel including a plurality of green charge storage sections, the red charge storage section and the blue charge storage section being provided in the substrate. Then, the plurality of green charge storage sections are arranged in the substrate along a thickness direction of the substrate.Type: GrantFiled: August 20, 2015Date of Patent: April 11, 2017Assignee: SONY CORPORATIONInventor: Hiroaki Ishiwata
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Patent number: 9620555Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.Type: GrantFiled: December 28, 2015Date of Patent: April 11, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
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Patent number: 9620556Abstract: A method for forming an image-sensor device is provided. The method includes providing a first semiconductor substrate having a first surface and a second surface opposite to the first surface. The method includes forming a device layer over the first surface of the first semiconductor substrate. The method includes bonding the first semiconductor substrate to a second semiconductor substrate after the formation of the device layer. The second surface faces the second semiconductor substrate. The method includes forming a diffusion layer between the first semiconductor substrate and the second semiconductor substrate. The diffusion layer has a dopant concentration gradient that increases in a direction from the first semiconductor substrate toward the second semiconductor substrate.Type: GrantFiled: November 10, 2015Date of Patent: April 11, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Nan Tu, Yu-Lung Yeh, Ming-Hsien Wu
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Patent number: 9620557Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.Type: GrantFiled: December 18, 2015Date of Patent: April 11, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xu Sheng Bao, Ma Phoo Pwint Hlaing
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Patent number: 9620558Abstract: A solid-state image sensor includes: a pixel array that includes first pixels, each having first and second photoelectric conversion units, and second pixels, each having third and fourth photoelectric conversion units; first to fourth transfer gates via which a signal charge respectively generated in the first to fourth photoelectric conversion units is respectively transferred to first to fourth charge voltage conversion units. At least one of a gate width, a gate length and an installation position of at least one transfer gate among the first to fourth transfer gates is altered to achieve uniformity in voltage conversion efficiency at the first to fourth charge voltage conversion units.Type: GrantFiled: October 21, 2013Date of Patent: April 11, 2017Assignee: NIKON CORPORATIONInventor: Satoshi Suzuki
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Patent number: 9620559Abstract: A set of light emitting devices can be formed on a substrate. A growth mask having a first aperture in a first area and a second aperture in a second area is formed on a substrate. A first nanowire and a second nanowire are formed in the first and second apertures, respectively. The first nanowire includes a first active region having a first band gap and a second active region having a second band gap. The first band gap is greater than the second band gap. The second nanowire includes an active region having the first band gap and does not include, or is adjoined to, any material having the second band gap.Type: GrantFiled: September 25, 2015Date of Patent: April 11, 2017Assignee: GLO ABInventors: Martin Schubert, Daniel Bryce Thompson, Michael Grundmann, Nathan Gardner
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Patent number: 9620560Abstract: An EL display device of the present invention includes a plurality of pixel electrodes, wiring, a common electrode, a plurality of light-emitting layer portions, and a protective layer. The pixel electrodes are formed in one-to-one correspondence with a plurality of pixels. The wiring is formed in at least one of a plurality of intervals between the pixels. The common electrode is formed above each of the pixel electrodes and is in electrical connection with the wiring. The common electrode is made of alkali metal or alkaline earth metal. The light-emitting layer portions are each located between a corresponding one of the pixel electrodes and the common electrode. The protective layer is located on the common electrode, preventing oxidization thereof. The EL display device suppresses voltage drop in the common electrode, while also suppressing reduction in a property of electron injection to the light-emitting layer portions.Type: GrantFiled: August 24, 2012Date of Patent: April 11, 2017Assignee: JOLED INC.Inventor: Takashi Isobe
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Patent number: 9620561Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes an underlayer containing aluminum (Al), nitrogen (N) and X. The X is an element other than Al and N. A first magnetic layer is provided on the underlayer. A nonmagnetic layer is provided on the first magnetic layer. A second magnetic layer is provided on the nonmagnetic layer.Type: GrantFiled: February 20, 2015Date of Patent: April 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Toshihiko Nagase, Daisuke Watanabe, Youngmin Eeh, Koji Ueda, Kazuya Sawada, Makoto Nagamine
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Voltage-controlled magnetic anisotropy switching device using an external ferromagnetic biasing film
Patent number: 9620562Abstract: Aspects of the present disclose related to a voltage-controlled magnetic anisotropy (VCMA) switching device using an external ferromagnetic biasing film. Aspects of the present disclose provide for a magnetoresistive random access memory (MRAM) device. The MRAM device generally includes a substrate, at least one magnetic tunnel junction (MTJ) stack disposed on the substrate, wherein the MTJ stack comprises a tunnel barrier layer between a first ferromagnetic layer having a fixed magnetization and a second ferromagnetic layer having unfixed magnetization, and a magnet disposed adjacent to the second ferromagnetic layer.Type: GrantFiled: June 2, 2015Date of Patent: April 11, 2017Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventor: Jordan A. Katine -
Patent number: 9620564Abstract: A semiconductor device includes four or more first memory cells arranged on a row, the first memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film formed around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film, and a first magnetic tunnel junction storage element formed on the first pillar-shaped semiconductor layer. The semiconductor device further includes a first source line that connects lower portions of the first pillar-shaped semiconductor layers to each other, a first bit line that extends in a direction perpendicular to a direction in which the first gate line extends and that is connected to an upper portion of the first magnetic tunnel junction storage element, and a second source line that extends in a direction perpendicular to a direction in which the first source line extends.Type: GrantFiled: April 8, 2016Date of Patent: April 11, 2017Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 9620565Abstract: A semiconductor memory device includes a plurality of memory cells arranged in rows and columns; a source line electrically connected to one terminal of each of the memory cells; a bit line electrically connected to the other terminal of each of the memory cells; a plurality of first word lines, each electrically connected to memory cells included in corresponding one of the rows; and a plurality of second word lines, each electrically connected to memory cells included in corresponding one of the columns.Type: GrantFiled: June 30, 2016Date of Patent: April 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Keisuke Nakatsuka
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Patent number: 9620566Abstract: A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.Type: GrantFiled: March 18, 2016Date of Patent: April 11, 2017Assignee: SK Hynix Inc.Inventor: Nam Kyun Park
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Patent number: 9620567Abstract: The present disclosure relates to a technical field of OLED display and discloses an OLED backboard, a method of manufacturing the same, an alignment system and an alignment method thereof, which aims to solve a problem of low efficiency in forming an organic light-emitting material layer on the OLED backboard.Type: GrantFiled: February 27, 2015Date of Patent: April 11, 2017Assignees: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd.Inventor: Jinzhong Zhang
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Patent number: 9620568Abstract: The present invention provide a display substrate, a fabricating method thereof, and a display apparatus, and belongs to the field of display technology. The display substrate comprises a plurality of pixels, each of the pixels is divided into a plurality of light emitting units, each of the light emitting units comprises an anode, a cathode, a carrier transport layer, and a light emitting layer, wherein at least one of the plurality of light emitting units comprises a light emitting layer and at least one process auxiliary layer; the process auxiliary layer and the light emitting layer in other light emitting units are formed into an integral portion from a same material in a film forming process. Display resolution can be improved in the present invention.Type: GrantFiled: July 20, 2015Date of Patent: April 11, 2017Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Guang Yan, Changyen Wu, Li Sun
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Patent number: 9620569Abstract: A light-emitting device includes a first pixel, a second pixel, and a third pixel. The first pixel includes a first light-emitting element that emits light in a first wavelength range. The second pixel includes a second light-emitting element that emits light in a fourth wavelength range that is different from the first wavelength range and that includes a second wavelength range and a third wavelength range and a first color filter that transmits light in the second wavelength range emitted from the second light-emitting element. The third pixel includes a third light-emitting element that emits light in the fourth wavelength range and a second color filter that transmits light in the third wavelength range emitted from the third light-emitting element.Type: GrantFiled: April 20, 2015Date of Patent: April 11, 2017Assignee: SEIKO EPSON CORPORATIONInventor: Koya Shiratori
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Patent number: 9620570Abstract: Provided are an organic light emitting display device and a method for manufacturing the same. A color filter is disposed on a substrate. An overcoating layer is disposed on the color filter and includes a plurality of protrusions or a plurality of recesses. The plurality of protrusions and the plurality of recesses are disposed on the color filter to be overlapped with the color filter. A buffer layer for reducing step difference is disposed on the overcoating layer. The buffer layer has a higher refractive index than the overcoating layer and reduces a step difference caused by the plurality of protrusions and the plurality of recesses. An organic light emitting element including an anode, an organic light emitting layer, and a cathode is disposed on the buffer layer. Since the buffer layer has a higher refractive index than the overcoating layer, light extraction efficiency can be increased.Type: GrantFiled: June 29, 2015Date of Patent: April 11, 2017Assignee: LG Display Co., Ltd.Inventors: Wonhoe Koo, BongChul Kim, KangJu Lee, Sookang Kim, Jihyang Jang, Hyunsoo Lim
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Patent number: 9620571Abstract: An electronic device is provided with a display and a light sensor that receives light that passes through the display. The display includes features that increase the amount of light that passes through the display. The features may be translucency enhancement features that allow light to pass directly through the display onto a light sensor mounted behind the display or may include a light-guiding layer that guides light through the display onto a light sensor mounted along an edge of the display. The translucency enhancement features may be formed in a reflector layer or an electrode layer for the display. The translucency enhancement features may include microperforations in a reflector layer of the display, a light-filtering reflector layer of the display, or a reflector layer of the display that passes a portion of the light and reflects an additional portion of the light.Type: GrantFiled: March 31, 2016Date of Patent: April 11, 2017Assignee: Apple Inc.Inventors: Anna-Katrina Shedletsky, Paul S. Drzaic, Erik G. de Jong, Fletcher R. Rothkopf
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Patent number: 9620572Abstract: Disclosed are OLED display panel and method for manufacturing the same, as well as display device including the OLED display panel. The present disclosure belongs to the field of an organic light emitting diode. The OLED display panel includes a light emitting structure, a TFT backplane, and an insulating layer. The insulating layer locates between the light emitting structure and the TFT backplane. A refractive index of the insulating layer gradually decreases in a direction of an emergent ray of the light emitting structure. The technical solution of the present disclosure may decrease influences of the emergent ray of the light emitting structure on TFT performance.Type: GrantFiled: June 17, 2014Date of Patent: April 11, 2017Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Wei Huang
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Patent number: 9620573Abstract: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.Type: GrantFiled: May 12, 2015Date of Patent: April 11, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masaya Kadono, Shunpei Yamazaki, Yukio Yamauchi, Hidehito Kitakado
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Patent number: 9620574Abstract: An organic light emitting diode display includes a substrate, a semiconductor disposed on the substrate that includes a channel for each of a plurality of transistors and doping regions formed at both sides of each channel; a gate insulating layer disposed on the semiconductor that includes an insulating layer opening through which the doping regions of two different transistors are exposed; a gate electrode disposed on the gate insulating layer that overlaps each channel; an interlayer insulating layer disposed on the gate electrode that includes a first and second contact holes through which the doping regions exposed within the insulating layer opening are each exposed; and data wirings disposed on the interlayer insulating layer that are each connected to the doping regions. The interlayer insulating layer includes an organic layer, and the first and second contact holes each include a first side wall positioned within the insulating layer opening.Type: GrantFiled: December 11, 2015Date of Patent: April 11, 2017Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Wang Woo Lee, Young Woo Park, Se Wan Son, Min Woo Woo
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Patent number: 9620575Abstract: A double-sided display and a method for controlling the same are provided. The double-sided display includes a plurality of pixel units and a plurality of circuits. The pixel units are disposed on each of a front side and a back side of the double-sided display, and the pixel units on the front side are opposite to the pixel units on the back side in a one-to-one manner. A pixel unit on the front side and a pixel unit on the back side opposite to the pixel unit on the front side are controlled by an identical circuit. Each of the circuits includes a switching transistor. The switching transistor includes a first input terminal connected to a scan line, a second input terminal connected to a data line, and an output terminal connected to the opposite pixel units on the front side and the back side.Type: GrantFiled: April 27, 2015Date of Patent: April 11, 2017Assignee: Shenzhen Royole Technologies Co., Ltd.Inventors: Zihong Liu, Xiaojun Yu
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Patent number: 9620576Abstract: Embodiments may disclose an organic light-emitting display device including a first substrate including a pixel area emitting light in a first direction, and a transmittance area that is adjacent to the pixel area and transmits external light; a second substrate facing the first substrate and encapsulating a pixel on the first substrate; an optical pattern array on the first substrate or the second substrate to correspond to the transmittance area, the optical pattern array being configured to transmit or block external light depending on the transmittance area according to a coded pattern; and a sensor array corresponding to the optical pattern array, the sensor array being arranged in a second direction that is opposite to the first direction in which the light is emitted, the second array receiving the external light passing through the optical pattern array.Type: GrantFiled: October 10, 2014Date of Patent: April 11, 2017Assignee: Samsung Display Co., Ltd.Inventors: Jin-Koo Chung, Sang-Hoon Yim, Chan-Young Park, Jun-Ho Choi, Seong-Min Kim
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Patent number: 9620577Abstract: An organic light emitting display device includes a substrate including a light-emitting region and a transparent region, a transistor disposed in the light-emitting region and including a gate electrode, a source electrode and a drain electrode overlapping the gate electrode, a capacitor disposed in the light-emitting region and disposed adjacent to the transistor and including a first capacitor electrode and a second capacitor electrode overlapping the first capacitor electrode, and a plurality of light-blocking patterns partially overlapping the gate electrode, the source electrode or the drain electrode and disposed on a different layer as a layer the gate electrode, the source electrode or the drain electrode are disposed.Type: GrantFiled: November 16, 2015Date of Patent: April 11, 2017Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Kwang-Young Choi, Sang-Ho Park
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Patent number: 9620578Abstract: An array substrate, a manufacture method of the array substrate, and a display panel are configured to achieve a combination of solar energy technology and the OLED display technology. The array substrate includes substrate, scanning lines, data lines, a thin film transistor (TFT), a common electrode and a pixel electrode. The array substrate further includes a light-emitting structure configured to provide a backlight source, a solar cell structure and a power output line. The light-emitting structure is provided between the common electrode and the pixel electrode. The solar cell structure is provided between the substrate and the common electrode. The power output line is provided in a same layer as the common electrode and is electrically connected to the solar cell structure so as to transmit electric energy generated by the solar cell structure to an external circuit.Type: GrantFiled: August 29, 2014Date of Patent: April 11, 2017Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.Inventors: Jiaxiang Zhang, Jian Guo, Xu Chen
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Patent number: 9620579Abstract: An organic light-emitting display apparatus includes a substrate; an active layer; a gate electrode, source and drain electrodes; a first insulating layer disposed between the active layer and the gate electrode; a second insulating layer disposed between the gate electrode and the source and drain electrodes; a third insulating layer disposed over the source and drain electrodes; conductive layers disposed over the third insulating layer and electrically connected to the source and drain electrodes through the third insulating layer; a first line disposed over the second insulating layer and formed of the same material as the source and drain electrodes; a second line overlapping the first line, disposed over the third insulating layer, and formed of the same material as the conductive layer; a fourth insulating layer disposed over the third insulating layer to cover the conductive layer; and an organic light-emitting diode disposed over the fourth insulating layer.Type: GrantFiled: August 25, 2015Date of Patent: April 11, 2017Assignee: Samsung Display Co., Ltd.Inventors: Nayoung Kim, Jungbae Kim
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Patent number: 9620580Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A passive device is disposed on the conductive pad, passing through the second passivation layer. An organic solderability preservative film covers the passive device.Type: GrantFiled: May 21, 2014Date of Patent: April 11, 2017Assignee: MEDIATEK INC.Inventors: Tzu-Hung Lin, Cheng-Chou Hung
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Patent number: 9620581Abstract: A method and an electrical device with superimposed layers in an alternation of conductive layers and insulating layers. A mesa-type structure is formed, leaving for at least one conductive layer, an uncovered peripheral portion accessible for connection. In this portion, an electrically insulating pattern is configured in order to mark out an electrically insulated area located in the peripheral portion of said at least one of the electrically conductive layers. Application to electrical capacitances and redistribution layers for microelectronic devices.Type: GrantFiled: June 10, 2015Date of Patent: April 11, 2017Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Sylvain Pelloquin, Christel Dieppedale, Gwenael Le Rhun, Henri Sibuet
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Patent number: 9620582Abstract: The present disclosure relates a metal-insulator-metal (MIM) capacitor. In some embodiments, the MIM capacitor has a capacitor bottom metal (CBM) electrode arranged over a semiconductor substrate. The MIM capacitor has a high-k dielectric disposed over the CBM electrode and a capacitor top metal (CTM) electrode arranged over the high-k dielectric layer. The MIM capacitor has a dummy structure that is disposed vertically over the high-k dielectric layer and laterally apart from the CTM electrode. The dummy structure includes a conductive body having a same material as the CTM electrode.Type: GrantFiled: January 27, 2015Date of Patent: April 11, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Pei Hsieh, Chern-Yow Hsu, Shih-Chang Liu
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Patent number: 9620583Abstract: A power semiconductor device is disclosed. The power semiconductor device includes a source region in a body region, a gate trench adjacent to the source region, and a source trench electrically coupled to the source region. The source trench includes a source trench conductive filler surrounded by a source trench dielectric liner, and extends into a drift region. The power semiconductor device includes a source trench implant below the source trench and a drain region below the drift region, where the source trench implant has a conductivity type opposite that of the drift region. The power semiconductor device may also include a termination trench adjacent to the source trench, where the termination trench includes a termination trench conductive filler surrounded by a termination trench dielectric liner. The power semiconductor device may also include a termination trench implant below the termination trench.Type: GrantFiled: September 16, 2015Date of Patent: April 11, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Kapil Kelkar, Timothy D. Henson, Ling Ma, Mary Bigglestone, Adam Amali, Hugo Burke, Robert Haase
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Patent number: 9620584Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.Type: GrantFiled: August 7, 2014Date of Patent: April 11, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Lingpeng Guan, Anup Bhalla, Madhur Bobde, Tinggang Zhu
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Patent number: 9620585Abstract: At least some illustrative device embodiments include a highly-doped n-type semiconductor substrate having a first epitaxial layer of a lightly-doped n-type semiconductor; and a second epitaxial layer of a lightly-doped p-type semiconductor to form a vertical diode with the first epitaxial layer. A termination structure near the outer edges of the device includes a termination well in the second epitaxial layer, the termination well being a moderately-doped n-type semiconductor so as to form a horizontal diode with the second epitaxial layer. The structure further includes an electric field barrier. The electric field barrier includes at least one vertical trench extending through the termination well into the first epitaxial layer and exposing a sidewall region. The sidewall region is doped via the sidewalls to be a moderately-doped p-type semiconductor. Also provided are sidewall layers of a moderately-doped n-type semiconductor, the sidewalls electrically coupling the termination well to the substrate.Type: GrantFiled: July 8, 2016Date of Patent: April 11, 2017Assignee: Semiconductor Components Industries, LLCInventors: Gary H. Loechelt, Gordon M. Grivna
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Patent number: 9620586Abstract: Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a Bird's Beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the Bird's Beak region and terminating at the inner edge of the Bird's Beak region, a gate included in the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the Bird's Beak and guard regions. A variation of minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.Type: GrantFiled: January 28, 2016Date of Patent: April 11, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: James Fred Salzman
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Patent number: 9620587Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.Type: GrantFiled: September 30, 2015Date of Patent: April 11, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Jagar Singh, Andy Wei, Mahadeva Iyer Natarajan
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Patent number: 9620588Abstract: A semiconductor device includes a semiconductor chip formed with an SiC-IGBT including an SiC semiconductor layer, a first conductive-type collector region formed such that the collector region is exposed on a second surface of the SiC semiconductor layer, a second conductive-type base region formed such that the base region contacts the collector region, a first conductive-type channel region formed such that the channel region contacts the base region, a second conductive-type emitter region formed such that the emitter region contacts the channel region to define a portion of a first surface of the SiC semiconductor layer, a collector electrode connected to the collector region, and an emitter electrode connected to the emitter region. A MOSFET of the device is connected in parallel to the SiC-IGBT, and includes a second conductive-type source region electrically connected to the emitter electrode and a second conductive-type drain region electrically connected to the collector electrode.Type: GrantFiled: August 2, 2016Date of Patent: April 11, 2017Assignee: ROHM CO., LTD.Inventors: Masatoshi Aketa, Yuki Nakano
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Patent number: 9620589Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side.Type: GrantFiled: April 7, 2014Date of Patent: April 11, 2017Assignee: GLOBALFOUNDRIES, INC.Inventors: Nicolas Sassiat, Ran Yan, Kun-Hsien Lin, Jan Hoentschel
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Patent number: 9620590Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.Type: GrantFiled: September 20, 2016Date of Patent: April 11, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
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Patent number: 9620591Abstract: A semiconductor device with multi-level work function and multi-valued channel doping is provided. The semiconductor device comprises a nanowire structure and a gate region. The nanowire structure is formed as a channel between a source region and a drain region. The nanowire structure has a first doped channel section joined with a second doped channel section. The first doped channel section is coupled to the source region and has a doping concentration greater than the doping concentration of the second doped channel section. The second doped channel section is coupled to the drain region. The gate region is formed around the junction at which the first doped section and the second doped section are joined. The gate region has a first work function gate section joined with a second work function gate section. The first work function gate section is located adjacent to the source region and has a work function greater than the work function of the second work function gate section.Type: GrantFiled: February 19, 2014Date of Patent: April 11, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tsung-Hsing Yu, Yeh Hsu, Chia-Wen Liu, Jean-Pierre Colinge
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Patent number: 9620592Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-doped layer is formed on the p-doped layer, the n-doped layer including a doped III-V material. A contact interface layer is formed on the n-doped layer. The contact interface layer includes a II-VI material. A contact metal is formed on the contact interface layer to form an electronic device.Type: GrantFiled: February 12, 2015Date of Patent: April 11, 2017Assignee: International Business Machines CorporationInventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Siegfried L. Maurer, Devendra K. Sadana
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Patent number: 9620593Abstract: A semiconductor device includes a semiconductor layer made of a wide bandgap semiconductor and including a gate trench; a gate insulating film formed on the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film. The semiconductor layer includes a first conductivity type source region; a second conductivity type body region; a first conductivity type drift region; a second conductivity type first breakdown voltage holding region; a source trench passing through the first conductivity type source region and the second conductivity type body region from the front surface and reaching a drain region; and a second conductivity type second breakdown voltage region selectively formed on an edge portion of the source trench where the sidewall and the bottom wall thereof intersect with each other in a parallel region of the source trench.Type: GrantFiled: August 7, 2015Date of Patent: April 11, 2017Assignee: ROHM CO., LTD.Inventors: Yuki Nakano, Ryota Nakamura
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Patent number: 9620594Abstract: A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.Type: GrantFiled: September 29, 2014Date of Patent: April 11, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hsien Chen, Liang-Tai Kuo, Hau-Yan Lu, Chun-Yao Ko
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Patent number: 9620595Abstract: A gate pad electrode and a source electrode are disposed, separately from one another, on the front surface of a super junction semiconductor substrate. A MOS gate structure formed of n source regions, p channel regions, p contact regions, a gate oxide film, and polysilicon gate electrodes is formed immediately below the source electrode. The p well regions are formed immediately below the gate pad electrode. The p channel regions are linked to the p well regions via extension portions. By making the width of the p well regions wider than the width of the p channel regions, it is possible to reduce a voltage drop caused by a reverse recovery current generated in a reverse recovery process of a body diode.Type: GrantFiled: January 8, 2016Date of Patent: April 11, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takayuki Shimatou
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Patent number: 9620596Abstract: A method including forming a diamond material on the surface of a substrate; forming a first contact and a separate second contact; and patterning the diamond material to form a nanowire between the first contact and the second contact. An apparatus including a first contact and a separate second contact on a substrate; and a nanowire including a single crystalline or polycrystalline diamond material on the substrate and connected to each of the first contact and the second contact.Type: GrantFiled: September 18, 2014Date of Patent: April 11, 2017Assignee: Sandia CorporationInventors: Alfredo M. Morales, Richard J. Anderson, Nancy Y. C. Yang, Jack L. Skinner, Michael J. Rye
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Patent number: 9620597Abstract: A graphene optoelectronic detector is disclosed, which comprises: an insulating substrate with a graphene layer disposed thereon; a first electrode disposed on the graphene layer or between the graphene layer and the insulating substrate; and a second electrode disposed on the graphene layer or between the graphene layer and the insulating substrate, wherein there is a predetermined distance between the first electrode and the second electrode, and the first electrode and the second electrode are at different electrical potentials, wherein a high-drift carrier moving region is disposed between the first electrode and the second electrode, and a low-drift carrier moving region is disposed outside the high-drift carrier moving region. In addition, the present invention further provides a method for detecting photons and electromagnetic energy using the aforementioned graphene detector.Type: GrantFiled: June 26, 2015Date of Patent: April 11, 2017Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Yon-Hua Tzeng, Chun-Cheng Chang, Pin-Yi Li, Yueh-Chieh Chu
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Patent number: 9620598Abstract: An electronic device can transistor having a channel layer that includes a compound semiconductor material. In an embodiment, the channel layer overlies a semiconductor layer that includes a carrier barrier region and a carrier accumulation region. The charge barrier region can help to reduce the likelihood that de-trapped carriers from the channel layer will enter the charge barrier region, and the charge accumulation region can help to repel carriers in the channel layer away from the charge barrier layer. In another embodiment, a barrier layer overlies the channel layer. Embodiments described herein may help to produce lower dynamic on-resistance, lower leakage current, another beneficial effect, or any combination thereof.Type: GrantFiled: June 17, 2015Date of Patent: April 11, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chun-Li Liu, Ali Salih
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Patent number: 9620599Abstract: A semiconductor device according an embodiment includes a GaN layer, a GaN-based semiconductor layer provided on the GaN layer and having a wider band gap than the GaN layer, a source electrode electrically connected to the GaN-based semiconductor layer, a drain electrode electrically connected to the GaN-based semiconductor layer, a gate electrode provided in the GaN-based semiconductor layer between the source electrode and the drain electrode, and a gate insulating film provided at least between the GaN layer and the gate electrode, the gate insulating film including a first insulating film and a second insulating film, the first insulating film provided on the GaN layer, the first insulating film having a thickness equal to or greater than 0.2 nm and less than 2 nm, the first insulating film including nitrogen, the second insulating film provided between the first insulating film and the gate electrode, the second insulating film including oxygen.Type: GrantFiled: December 16, 2015Date of Patent: April 11, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Hisashi Saito, Miki Yumoto
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Patent number: 9620600Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes an element region and a termination region provided around the element region. The termination region has a first semiconductor region of a first conductivity type provided at the first surface of the semiconductor substrate and a second semiconductor region of a second conductivity type provided between the first semiconductor region and the second surface. The semiconductor device further includes a first insulating film provided on the first semiconductor region, a second insulating film provided on the first semiconductor region and having a portion interposed between the first insulating films, a first electrode provided on the first surface of the element region and electrically connected to the first semiconductor region, and a second electrode provided at the second surface of the semiconductor substrate.Type: GrantFiled: September 15, 2015Date of Patent: April 11, 2017Assignee: Kabushiki kaisha ToshibaInventors: Ryoichi Ohara, Takao Noda
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Patent number: 9620601Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.Type: GrantFiled: July 1, 2014Date of Patent: April 11, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
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Patent number: 9620602Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.Type: GrantFiled: August 10, 2015Date of Patent: April 11, 2017Assignee: Renesas Electronics CorporationInventors: Tetsuya Watanabe, Mitsuru Miyamori, Katsumi Tsuneno, Takashi Shimizu