Patents Issued in April 11, 2017
  • Patent number: 9620653
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
  • Patent number: 9620654
    Abstract: A voltage switchable coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A chrome oxide layer is formed on the cobalt by MBE at room at UHV at room temperature. There was thin cobalt oxide interface between the chrome oxide and the cobalt. Other magnetic materials may be employed. A few ML field of graphene is deposited on the chrome oxide by molecular beam epitaxy, and a source and drain are deposited of base material. The resulting device is scalable, provides high on/off rates, is stable and operable at room temperature and easily fabricated with existing technology.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: April 11, 2017
    Assignee: QUANTUM DEVICES, LLC
    Inventors: Jeffry Kelber, Peter Dowben
  • Patent number: 9620655
    Abstract: Laser foil trim approaches for foil-based metallization of solar cells, and the resulting solar cells, are described. For example, a method of fabricating a solar cell includes attaching a metal foil sheet to a surface of a wafer to provide a unified pairing of the metal foil sheet and the wafer, wherein the wafer has a perimeter and the metal foil sheet has a portion overhanging the perimeter. The method also includes laser scribing the metal foil sheet along the perimeter of the wafer using a laser beam that overlaps the metal foil sheet outside of the perimeter of the wafer and at the same time overlaps a portion of the unified pairing of the metal foil sheet and the wafer inside the perimeter of the wafer to remove the portion of the metal foil sheet overhanging the perimeter and to provide a metal foil piece coupled to the surface of the wafer.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: April 11, 2017
    Assignees: SunPower Corporation, Total Marketing Services
    Inventors: Robert Woehl, Richard Hamilton Sewell, Mohamed A. Elbandrawy, Taeseok Kim, Thomas P. Pass, Benjamin Ian Hsia, David Fredric Joel Kavulak, Nils-Peter Harder
  • Patent number: 9620656
    Abstract: Method of encapsulating a semiconductor structure comprising providing a semiconductor structure comprising an opto-electric element located in a cavity formed between a substrate and a cap layer, the cap layer being made of a material transparent to light, and having a flat upper surface; forming at least one protrusion on the cap layer; bringing the at least one protrusion of the cap layer in contact with a tool having a flat surface region, and applying a opaque material to the semiconductor structure where it is not in contact with the tool; and removing the tool thereby providing an encapsulated optical semiconductor device having a transparent window integrally formed with the cap layer.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: April 11, 2017
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventors: Carl Van Buggenhout, Jian Chen
  • Patent number: 9620657
    Abstract: An image sensor includes a semiconductor substrate integrated with at least one first photo-sensing device sensing light in a first wavelength region and at least one second photo-sensing device sensing light in a second wavelength region shorter than the first wavelength region, a photoelectric device including a pair of electrodes facing each other and a light absorption layer between the electrodes, the photoelectric device selectively absorbing light in a third wavelength region between the first wavelength region and the second wavelength region, and a nanostructural body between the semiconductor substrate and the photoelectric device, the nanostructural body including at least two parts having different optical paths.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: April 11, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gae Hwang Lee, Kyu Sik Kim, Yong Wan Jin
  • Patent number: 9620658
    Abstract: A modular, lightweight, high-survivable, photovoltaic flexible blanket assembly for a space solar array is disclosed. The modular blanket is an accordion foldable or rollable flexible photovoltaic solar panel blanket assembly comprising a plurality of common photovoltaic modules spaced in an orthogonal pattern. Each module is mechanically attached with multiple low profile fasteners on their backside to an open weave mesh tensioned backplane structure. The backplane forms a tensioned dimensionally stable planar surface in the deployed configuration onto which the modules are suspended. Each module is common and comprised of a rectangular substrate that includes solar cell assemblies, circuitry, exposed electrical contacts for integration of blanket-level harnessing, and frontside and rearside shielding and coatings as required for the mission application.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: April 11, 2017
    Assignee: Deployable Space Systems, Inc.
    Inventors: Brian R Spence, Stephen F White, Mark V Douglas, Kevin B Schmid, Ron S Takeda
  • Patent number: 9620659
    Abstract: A preparation method of a glass film, a photoelectric device and a packaging method thereof, and a display device are provided, and the preparation method of a glass film includes: forming a sacrificial layer on a base substrate; forming a glass frit film on the sacrificial layer; solidifying the glass frit film; and removing the sacrificial layer, so as to obtain a glass film. The method can bring an individual glass film, which is helpful to a narrow-bezel design of a photoelectric device.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: April 11, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Dan Wang
  • Patent number: 9620660
    Abstract: An interconnect assembly. The interconnect assembly includes a trace that includes a plurality of electrically conductive portions. The plurality of electrically conductive portions is configured both to collect current from a first solar cell and to interconnect electrically to a second solar cell. In addition, the plurality of electrically conductive portions is configured such that solar-cell efficiency is substantially undiminished in an event that any one of the plurality of electrically conductive portions is conductively impaired.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: April 11, 2017
    Assignee: Beijing Apollo Ding Rong Solar Technology Co., Ltd.
    Inventors: Mulugeta Zerfu Wudu, Jason Stephen Corneille, Steven Thomas Croft, Steven Douglas Flanders, William James McColl
  • Patent number: 9620661
    Abstract: Approaches for foil-based metallization of solar cells and the resulting solar cells are described. For example, a method of fabricating a solar cell involves locating a metal foil above a plurality of alternating N-type and P-type semiconductor regions disposed in or above a substrate. The method also involves laser welding the metal foil to the alternating N-type and P-type semiconductor regions. The method also involves patterning the metal foil by laser ablating through at least a portion of the metal foil at regions in alignment with locations between the alternating N-type and P-type semiconductor regions. The laser welding and the patterning are performed at the same time.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: April 11, 2017
    Assignees: SunPower Corporation, Total Marketing Services
    Inventors: Taeseok Kim, Gabriel Harley, John Wade Viatella, Perine Jaffrennou
  • Patent number: 9620662
    Abstract: An ultraviolet sensor includes a silicon photodiode array having a plurality of first pixel regions and a plurality of second pixel regions. A filter film is disposed on each of the first pixel regions so as to cover each first pixel region, except on each second pixel region. The filter film lowers transmittance in a detection target wavelength range in the ultraviolet region. Each of each first pixel region and each second pixel region includes at least one pixel having an avalanche photodiode to operate in Geiger mode, and a quenching resistor connected in series to the avalanche photodiode. Each of the quenching resistors in the plurality of first pixel regions is connected through a first signal line to a first output terminal. Each of the quenching resistors in the plurality of second pixel regions is connected through a second signal line to a second output terminal.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: April 11, 2017
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Koei Yamamoto, Kenzo Hayatsu, Terumasa Nagano, Yuki Okuwa, Ryuta Yamada
  • Patent number: 9620663
    Abstract: A system for detecting an optimal timing for cleaning duty solar panels is provided herein. The system includes: a simulation sensor and a reference sensor which include photovoltaic cells identical to the photovoltaic cells of the duty solar panels, wherein the simulation sensor is configured to generate a simulation electrical signal which simulates electricity signal generated by the duty solar panels; and wherein the reference sensor is configured to generate a reference electrical signal which simulates electricity signal generated by the duty solar panels in a clean condition; and protection means configured to selectively expose the reference sensor for a specified period of time, wherein the system is configured to compare the simulation signal and the reference signal when the reference sensor is uncovered and provide an indication that the duty solar panels should be cleaned if a difference between the simulation and the reference signals exceeds a predefined level.
    Type: Grant
    Filed: November 4, 2012
    Date of Patent: April 11, 2017
    Inventors: Jack Dror, Avraham Shay Balouka
  • Patent number: 9620664
    Abstract: A tool useful in the manufacture of a semiconductor is disclosed. A mold is providing having an interior defining a planar capillary space. A coating substantially covers at least the planar capillary space of the graphite member. The coating is substantially non-reactive to silicon at temperatures greater than approximately 1420 degrees Centigrade.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: April 11, 2017
    Assignee: Mossey Creek Technologies, Inc.
    Inventor: John Carberry
  • Patent number: 9620665
    Abstract: Processes for controlling the growth and thickness of two-dimensional transition metal dichalcogenides are provided. The process modifies an insulator substrate surface with an electron or ion beam to create charged areas on the substrate surface. The treated surface allows for hydroxylation of the charged species which serves as nucleation sites for the seed particles during chemical vapor deposition that promotes growth of thin layers of transition metal dichalcogenides.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: April 11, 2017
    Assignee: The United States of America as Represented by the Secretary of the Army
    Inventors: Stephen F. Bartolucci, Daniel B. Kaplan
  • Patent number: 9620666
    Abstract: A diffusing agent composition including a condensation product and an impurity diffusion component. The condensation product is a reaction product resulting from hydrolysis of an alkoxysilane. The impurity diffusion component is a monoester or diester of phosphoric acid, or a mixture thereof.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: April 11, 2017
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Toshiro Morita, Takashi Kamizono
  • Patent number: 9620667
    Abstract: A method is disclosed for doping a semiconductor material comprising the steps of providing a semiconductor material having a first and a second surface. A dopant precursor is applied on the first surface of the semiconductor material. A thermal energy beam is directed onto the second surface of the semiconductor material to pass through the semiconductor material and impinge upon the dopant precursor to dope the semiconductor material thereby.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: April 11, 2017
    Assignee: AppliCote Associates LLC
    Inventors: Nathaniel R Quick, Michael C Murray
  • Patent number: 9620668
    Abstract: A composition for manufacturing an electrode of a solar cell, comprising metal nanoparticles dispersed in a dispersive medium, wherein the metal nanoparticles contain silver nanoparticles of 75 weight % or more, the metal nanoparticles are chemically modified by a protective agent having a main chain of organic molecule comprising a carbon backbone of carbon number of 1 to 3, and the metal nanoparticles contains 70% or more in number-average of metal nanoparticles having a primary grain size within a range of 10 to 50 nm.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: April 11, 2017
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Toshiharu Hayashi, Yoshiaki Takata, Kazuhiko Yamasaki
  • Patent number: 9620669
    Abstract: According to one embodiment, a semiconductor light emitting device includes a light emitting chip and a fluorescent material layer. The light emitting chip includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, and a resin layer. The semiconductor layer includes a light emitting layer, a first major surface, and a second major surface formed on a side opposite to the first major surface. The fluorescent material layer is provided on the first major surface and has a larger planer size than the light emitting chip.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: April 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Sugizaki, Hideki Shibata, Akihiro Kojima, Masayuki Ishikawa, Hideo Tamura, Tetsuro Komatsu
  • Patent number: 9620670
    Abstract: Solid state lighting dies and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting die includes a substrate material, a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials. The second semiconductor material has a surface facing away from the substrate material. The solid state lighting die also includes a plurality of openings extending from the surface of the second semiconductor material toward the substrate material.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: April 11, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Casey Kurth, Thomas Gehrke, Kevin Tetz
  • Patent number: 9620671
    Abstract: A nitride semiconductor light emitting element is provided with: a substrate; a buffer layer that is provided on the substrate; a base layer that is provided on the buffer layer; an n-side nitride semiconductor layer that is provided on the base layer; an MQW light emitting layer that is provided on the n-side nitride semiconductor layer; and a p-side nitride semiconductor layer that is provided on the MQW light emitting layer. An x-ray rocking curve half-value width ? (004) with respect to a (004) plane, i.e., the crystal plane of the nitride semiconductor, is 40 arcsec or less, or the x-ray rocking curve half-value width ? (102) with respect to a (102) plane is 130 arcsec or less, and the rate P (80)/P (25) between light output P (25) at 25° C. and light output P (80) at 80° C. with a same operating current is 95% or more.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: April 11, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hiroshi Nakatsu, Tomoya Inoue, Kentaro Nonaka, Toshiaki Asai, Tadashi Takeoka, Yoshihiko Tani
  • Patent number: 9620673
    Abstract: An optoelectronic device includes a carrier on which a semiconductor layer sequence is applied, said semiconductor layer sequence including an n-doped semiconductor layer and a p-doped semiconductor layer such that a p-n junction is formed which includes an active zone that generates electromagnetic radiation, wherein at least one of the n-doped semiconductor layer and the p-doped semiconductor layer includes a doped region having a first doping concentration greater than a second doping concentration in a surrounding area of the region in the semiconductor layer including the region.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: April 11, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Tobias Meyer, Christian Leirer, Lorenzo Zini, Jürgen Off, Andreas Löffler, Adam Bauer
  • Patent number: 9620674
    Abstract: A method for producing an optoelectronic component includes creating a first layer of a polymer material. The method also includes applying crystals to a surface of the first layer. The method also includes creating a second layer of a polymer material on the surface of the first layer. The crystals can be between the first and second layers.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: April 11, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Georg Dirscherl
  • Patent number: 9620675
    Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“HSG”) structures on the substrate surface of the substrate material. The solid state lighting device also includes a semiconductor material on the substrate material, at least a portion of which is between the plurality of HSG structures.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: April 11, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Thomas Gehrke
  • Patent number: 9620676
    Abstract: In various embodiments, light-emitting devices incorporate smooth contact layers and polarization doping (i.e., underlying layers substantially free of dopant impurities) and exhibit high photon extraction efficiencies.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 11, 2017
    Assignee: CRYSTAL IS, INC.
    Inventors: James R. Grandusky, Leo J. Schowalter, Muhammad Jamil, Mark C. Mendrick, Shawn R. Gibb
  • Patent number: 9620677
    Abstract: A light emitting diode includes a conductive layer, an n-GaN layer on the conductive layer, an active layer on the n-GaN layer, a p-GaN layer on the active layer, and a p-electrode on the p-GaN layer. The conductive layer is an n-electrode.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: April 11, 2017
    Assignee: LG Innotek Co., Ltd.
    Inventor: Myung Cheol Yoo
  • Patent number: 9620678
    Abstract: An electrode structure of a light emitting device includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes electrically contact with the light emitting device and are separated from one other. The second electrodes electrically contact with the light emitting device and are located at the same side with the first electrodes. The second electrodes are separated from one other, and the second electrodes have at least two different profiles when viewing from atop.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: April 11, 2017
    Assignee: PlayNitride Inc.
    Inventors: Shao-Hua Huang, Yun-Li Li
  • Patent number: 9620679
    Abstract: A light-emitting device comprises a light-emitting semiconductor stack comprising a plurality of recesses and a mesa, each of the plurality of recesses comprising a bottom surface, and the mesa comprising an upper surface; a first electrode formed on the upper surface of the mesa; a plurality of second electrodes respectively formed on the bottom surface of the plurality of recesses; a first electrode pad formed on the light-emitting semiconductor stack and contacting with the first electrode; a second electrode pad formed on the light-emitting semiconductor stack and contacting with the plurality of second electrode; a first insulating layer comprising a plurality of passages to expose the plurality of second electrodes; and a second insulating layer comprising a plurality of spaces and formed on the first insulating layer, wherein the plurality of spaces is covered by the first electrode pad.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 11, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Hong-Che Chen, Chien-Fu Shen, Chao-Hsing Chen, Yu-Chen Yang, Jia-Kuen Wang, Chih-Nan Lin
  • Patent number: 9620680
    Abstract: An optoelectronic semiconductor body for emitting electromagnetic radiation from the front side with a semiconductor layer sequence and a first electrical contact layer, wherein the semiconductor layer sequence comprises at least one opening that penetrates fully through the semiconductor layer sequence in the direction from the front side to the rear side that is opposite the front side, the first electrical contact layer is arranged at the rear of the semiconductor body, a section of the first electrical contact layer extends from the rear side through the opening to the front side and covers a first sub-region of a front-side main face of the semiconductor layer sequence, and a second sub-region of the front-side main face is not covered by the first electrical contact layer.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: April 11, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Karl Engl, Matthias Sabathil
  • Patent number: 9620681
    Abstract: A semiconductor device including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer which are sequentially stacked; a first conductivity type upper electrode portion and a first conductivity type lower electrode portion disposed to correspond to each other with the first conductivity type semiconductor layer interposed therebetween; a second conductivity type upper electrode portion and a second conductivity type lower electrode portion disposed to correspond to each other with the first and second conductivity type semiconductor layers interposed therebetween; and a second conductivity type electrode connection portion electrically connecting the second conductivity type upper electrode portion and the second conductivity type lower electrode portion.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: April 11, 2017
    Assignee: LG ELECTRONICS INC.
    Inventor: Hwankuk Yuh
  • Patent number: 9620682
    Abstract: A light emitting device includes a light emitting structure having a plurality of light emitting regions including a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode in one of the light emitting regions, a second electrode in another of the light emitting regions, and at least one connection electrode to sequentially connect the light emitting regions in series. The light emitting regions connected in series are divided into 1st to ith light emitting region groups. Areas of light emitting regions that belong to different groups are different. An area of a light emitting region which is more frequently used among the plurality of light emitting regions is larger than an area of a light emitting region which is less frequently used among the plurality of light emitting regions.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: April 11, 2017
    Assignee: LG Innotek Co., Ltd.
    Inventors: Sung Kyoon Kim, Yun Kyung Oh, Sung Ho Choo
  • Patent number: 9620683
    Abstract: A light emitting device is provided that may include a light emitting structure including a first conductivity-type semiconductor layer, an active layer provided on the first conductivity-type semiconductor layer, and a second conductivity-type semiconductor layer provided on the active layer, a first electrode that conductively contacts the first conductivity-type semiconductor layer, an insulating layer provided on a portion of the light emitting structure and the first electrode, and a second electrode that conductively contacts the second conductivity-type semiconductor layer, the first electrode including a first portion protruding from a side surface of the first conductivity-type semiconductor layer.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 11, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Keon Hwa Lee, Kwang Ki Choi
  • Patent number: 9620684
    Abstract: To provide an LED lighting apparatus and a method for manufacturing the same that can improve the bonding strength between an aluminum substrate and a printed wiring substrate. An LED lighting apparatus and a method for manufacturing the same, the LED lighting apparatus includes an aluminum substrate, a plurality of reflectivity-enhanced layers formed on the aluminum substrate, an LED device bonded on said plurality of reflectivity-enhanced layers, a printed wiring substrate bonded onto a region on the aluminum substrate other than a region where the plurality of reflectivity-enhanced layers are formed, a wire for connecting between the printed wiring substrate and the LED device, a frame member formed so as to surround said LED device, and a phosphor resin deposited over a region inside the frame member.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: April 11, 2017
    Assignees: CITIZEN ELECTRONICS CO., LTD., CITIZEN WATCH CO., LTD.
    Inventors: Tatsuya Katoh, Sadato Imai
  • Patent number: 9620685
    Abstract: A surface mount light-emitting device of side view and lead frame type can include a casing having a cavity, a first lead frame having a first mounting surface exposed from the cavity, and a second lead frame having a second mounting surface exposed from the cavity. A light-emitting chip can be mounted on one of the first and the second mounting surfaces, which extend in a substantially same level and balanced shapes with respect to each other to be used as external electrodes. An encapsulating resin including at least one phosphor can also encapsulate the light-emitting chip in the cavity. Thus, the disclosed subject matter can provide reliable surface mount light-emitting devices that can be easily mounted on a mounting board with high positional accuracy and can emit various color lights having a high light-emitting intensity using a high brightness chip in a substantially parallel direction to the mounting board.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: April 11, 2017
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Kazuyuki Yoshimizu, Masayuki Hasegawa
  • Patent number: 9620686
    Abstract: A display may be provided with light sources. The light sources may include light-emitting diodes. The light sources may have packages formed from package bodies to which the light-emitting diodes are mounted. Layers such as quantum dot layers, light-scattering layers, spacer layers, and diffusion barrier layers may be formed over the package bodies and light-emitting diodes. Quantum dots of different colors may be stacked on top of each other. A getter may be incorporated into one or more of the layers to getter oxygen and water. Quantum dots may be formed from semiconductor layers that are doped with n-type and p-type dopant to adjust the locations of their conduction and valance bands and thereby enhanced quantum dot performance.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: April 11, 2017
    Assignee: Apple Inc.
    Inventors: Jonathan S. Steckel, Sajjad A. Khan, Jean-Jacques P. Drolet
  • Patent number: 9620687
    Abstract: Provided are a light emitting diode, a method of manufacturing the same, and a use thereof. The light emitting diode having excellent initial light flux and excellent color uniformity and dispersion, the method of manufacturing the same, and the use thereof may be provided.
    Type: Grant
    Filed: November 28, 2013
    Date of Patent: April 11, 2017
    Assignee: LG CHEM, LTD.
    Inventor: Min Jin Ko
  • Patent number: 9620688
    Abstract: A display device includes a micro-lens film which has a high fill-factor and a high luminance ratio and prevents generation of moiré. The display device includes a display panel configured to display an image, a plurality of Light Emitting Diodes (LEDs) configured to generate light to supply light to the display panel, a light guide panel configured to guide light to the display panel, and a micro-lens film including a base film that concentrates and diffuses light emitted from the light guide panel, a lens unit at an upper surface of the base film, and a back-coating film at a lower surface of the base film. The lens unit includes unit block groups randomly arranged at the upper surface of the base film, each unit block group containing randomly arranged fixed-shape lenses having different sizes, and micro-beads randomly formed on surfaces of the fixed-shape lenses.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 11, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Sang-Hyun Lee, Won-Taek Moon, Sun-Woong Kim, Bo-Ra Kim, Sang-Dae Han, Su-Jin Chang
  • Patent number: 9620689
    Abstract: A semiconductor light emitting device that achieves miniaturization and high brightness is provided. The semiconductor light emitting device has a light extraction surface (6) parallel to a lamination direction of a semiconductor layer (2). The semiconductor light emitting device includes a light guide member (3) placed on the semiconductor layer (2) and having a sloped surface (7) with a side surface opposite to the light extraction surface (6) sloped to the light extraction surface and a light-reflecting member (4) placed on a surface of the light guide member including at least the sloped surface of the light guide member.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: April 11, 2017
    Assignee: NICHIA CORPORATION
    Inventors: Daisuke Sanga, Yuta Oka
  • Patent number: 9620690
    Abstract: Disclosed is a lighting system including: a board; a wiring pattern that is provided on a surface of the board and has a wiring pad; a light emitting element that is provided on the wiring pattern and includes an electrode on a surface thereof opposite to a surface thereof provided on the wiring pattern; a surrounding wall member that is provided to surround the light emitting element; a wiring that connects the wiring pad and the electrode; and a sealing portion that is provided inside the surrounding wall member and covers the light emitting element and the wiring. Here, an angle that is formed by a segment that connects a central position of a portion of the board surrounded by the surrounding wall member and a position where the wiring is connected to the wiring pad, and the wiring is 0° to 45°, or 135° to 180°.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: April 11, 2017
    Assignee: Toshiba Lighting & Technology Corporation
    Inventor: Kiyokazu Hino
  • Patent number: 9620691
    Abstract: Embodiments provide a light emitting device package including a first lead frame including a first contact area and a first exposed area, a second lead frame spaced apart from the first lead frame, the second lead frame including a second contact area and a second exposed area, a bottom portion located between the first contact area and the first exposed area, between the second contact area and the second exposed area, and between the first contact area and the second contact area, a light emitting device electrically connected to the first and second contact areas, and a package body having a cavity configured to expose the first and second contact areas, the first and second exposed areas, and the bottom portion, wherein the bottom portion has a thermal expansion coefficient greater than a thermal expansion coefficient of the first and second lead frames.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: April 11, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sung Joo Oh, Keal Doo Moon, Gyu Hyeong Bak
  • Patent number: 9620692
    Abstract: An exemplary lead frame includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes a first connecting surface and a second connecting surface spaced from the first connecting surface. Top surfaces of the bonding electrode, the first connecting electrode and the second connecting electrode are exposed out of the substrate to support and electrically connect with light emitting chips. Light emitting chips can be mounted on the lead frame and electrically connect with each other in parallel or in series; thus, the light emitting chips can be connected with each in a versatile way.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: April 11, 2017
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: Yau-Tzu Jang, Yu-Liang Huang, Wen-Liang Tseng, Pin-Chuan Chen, Lung-Hsin Chen, Hsing-Fen Lo, Chao-Hsiung Chang, Che-Hsang Huang, Yu-Lun Hsieh
  • Patent number: 9620693
    Abstract: Disclosed are a light emitting device and a lighting system having the same. The light emitting device includes a body including first and second lateral side parts, third and fourth lateral side parts, and a cavity, a first lead frame extending in a direction of the first lateral side part of the body, a second lead frame extending in a direction of the second lateral side part of the body, a light emitting chip disposed on the first lead frame in the cavity, and a gap part between the first and second lead frames. The first lead frame includes a first recess part having a first depth, and a second recess part recessed at a second depth, and the first recess part and the second recess part have a step structure with a curved surface.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 11, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Yeo Chan Yoon, Jae Hwan Jung, Yun Shick Eom, Ki Rok Hur, Jin Seong Kim
  • Patent number: 9620694
    Abstract: An optoelectronic component includes a leadframe, a molded body connected to the leadframe, and an optoelectronic semiconductor chip arranged on the leadframe, wherein the leadframe includes an alignment opening, and wherein the molded body includes a recess via which the leadframe is exposed in the area of the alignment opening.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: April 11, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Michael Zitzlsperger, Matthias Goldbach
  • Patent number: 9620695
    Abstract: A method and structure for stabilizing an array of micro devices is disclosed. A stabilization layer includes an array of stabilization cavities and array of stabilization posts. Each stabilization cavity includes sidewalls surrounding a stabilization post. The array of micro devices is on the array of stabilization posts. Each micro device in the array of micro devices includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 11, 2017
    Assignee: Apple Inc.
    Inventors: Hsin-Hua Hu, Kevin K. C. Chang, Andreas Bibl
  • Patent number: 9620696
    Abstract: Compound semiconductors, expressed by the following formula: Bi1-xMxCuwOa-yQ1yTeb-zQ2z. Here, M is at least one element selected from the group consisting of Ba, Sr, Ca, Mg, Cs, K, Na, Cd, Hg, Sn, Pb, Eu, Sm, Mn, Ga, In, Tl, As and Sb; Q1 and Q2 are at least one element selected from the group consisting of S, Se, As and Sb; x, y, z, w, a, and b are 0?x<1, 0<w?1, 0.2<a<4, 0?y<4, 0.2<b<4 and 0?z<4. These compound semiconductors may be used for various applications such as solar cells or thermoelectric conversion elements, where they may replace compound semiconductors in common use, or be used along with compound semiconductors in common use.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: April 11, 2017
    Assignee: LG CHEM, LTD.
    Inventors: Cheol-Hee Park, Se-Hui Sohn, Seung-Tae Hong, Won-Jong Kwon, Tae-Hoon Kim
  • Patent number: 9620697
    Abstract: The present invention provides a thermoelectric conversion material of which the structure is controlled to have nano-order microscopic pores and which has a low thermal conductivity and has an improved thermoelectric performance index. In the thermoelectric conversion material having a thermoelectric semiconductor layer formed on a block copolymer substrate that comprises a block copolymer having microscopic pores, wherein the block copolymer comprises a polymer unit (A) formed of a monomer capable of forming a homopolymer having a glass transition temperature of 50° C. or higher, and a polymer unit (B) formed of a conjugated dienic polymer.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: April 11, 2017
    Assignees: KYUSHU INSTITUTE OF TECHNOLOGY, LINTEC CORPORATION
    Inventors: Tsuyoshi Mutou, Koji Miyazaki, Yoshika Hatasako, Kunihisa Kato
  • Patent number: 9620698
    Abstract: An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer. The p-type thermoelectric elements and the n-type thermoelectric elements may be connected in series while alternating between the p-type and the n-type thermoelectric elements.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: April 11, 2017
    Assignee: Analog Devices, Inc.
    Inventors: William Allan Lane, Baoxing Chen
  • Patent number: 9620699
    Abstract: An insulating substrate is prepared. In this substrate, plural via holes penetrating in a thickness direction are filled with a conductive paste. This paste is produced by adding an organic solvent to a powder of an, and by processing the power of the alloy to a paste. The substrate is then pressed from a front surface and a back surface of the substrate, while being heated. The conductive paste is solid-phase sintered and interlayer connecting members are formed. A front surface protective member is disposed on a front surface of the substrate and a back surface protective member is disposed on a back surface of the substrate, and a laminate is formed. The laminate is integrated by a lower pressure being applied while heating at a lower temperature, compared to the temperature and pressure in the process of forming the interlayer connecting members.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: April 11, 2017
    Assignee: DENSO CORPORATION
    Inventors: Eijirou Miyagawa, Keita Saitou, Yoshihiko Shiraishi, Yoshitaro Yazaki, Toshihisa Taniguchi, Atusi Sakaida
  • Patent number: 9620700
    Abstract: An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer. The p-type thermoelectric elements and the n-type thermoelectric elements may be connected in series while alternating between the p-type and the n-type thermoelectric elements.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: April 11, 2017
    Assignee: Analog Devices, Inc.
    Inventor: Baoxing Chen
  • Patent number: 9620701
    Abstract: The present application relates to a pulse generator for energizing an ultrasonic transducer, a method of operating thereof and an ultrasonic distance sensing system comprising the pulse generator. The pulse generator is arranged to generate an excitation pulse sequence comprising a first number of pulses; to generate a cancellation pulse sequence comprising at least a fractional pulse, wherein the cancellation pulse sequence has a phase shift of about 180° in relation to the excitation pulse sequence; and to output at an output of the generator the excitation pulse sequence and the cancellation pulse sequence forming an energizing pulse sequence to the ultrasonic transducer.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: April 11, 2017
    Assignee: NXP USA, Inc.
    Inventors: Josef Maria Joachim Kruecken, Andreas Laudenbach
  • Patent number: 9620702
    Abstract: The present invention relates to an electronic component package, an electronic component package sealing member, and a method for producing the electronic component package sealing member. A through hole 49 is formed in a base 4 so as to pass through between both main surfaces 42 and 43 of a base material of the base 4. An inner side surface 491 of the through hole 49 includes a curved surface 495 that expands outward in a width direction of the through hole 49.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: April 11, 2017
    Assignee: DAISHINKU CORPORATION
    Inventor: Naoki Kohda
  • Patent number: 9620703
    Abstract: A piezoelectric thin-film element includes a substrate, a lower electrode layer formed on the substrate, a piezoelectric thin-film layer that is formed on the lower electrode layer and includes potassium sodium niobate having a perovskite structure represented by the composition formula of (K1-xNax)NbO3 (0.4?x?0.7), and an upper electrode layer formed on the piezoelectric thin-film layer. The piezoelectric thin-film layer is formed such that a value of (Ec?+Ec+)/2 is not less than 10.8 kV/cm and a value of (Pr?+Pr+)/2 is not more than ?2.4 ?C/cm2 where Ec? and Ec+ are intersection points of a polarization-electric field hysteresis loop and the x-axis indicating an electric field and Pr? and Pr+ are intersection points of the polarization-electric field hysteresis loop and the y-axis indicating polarization.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: April 11, 2017
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Kenji Shibata, Masaki Noguchi, Kazufumi Suenaga, Kazutoshi Watanabe, Fumimasa Horikiri