Abstract: A device for processing audio data obtains data representing quantized versions of a set of one or more spatial vectors. Each respective spatial vector of the set of spatial vectors corresponds to a respective audio signal of the set of audio signals. Each of the spatial vectors is in a Higher-Order Ambisonics (HOA) domain and is computed based on a set of loudspeaker locations. The device inverse quantizes the quantized versions of the spatial vectors.

Abstract: Embodiments of the present invention relate to audiovisual stream processing in videoconferences. For each audiovisual stream in a videoconference, a sound level of the audiovisual stream is detected. If the sound level exceeds a predefined threshold level, the audiovisual stream is processed with a first configuration. If the sound level is below the predefined threshold level, the audiovisual stream is processed with a second configuration. The second configuration is more resource-effective than the first configuration.

Abstract: An audio encoding method and an apparatus are provided. The method includes: determining sparseness of distribution, on spectrums, of energy of N input audio frames (101), where the N audio frames include a current audio frame, and N is a positive integer; and determining, according to the sparseness of distribution, on the spectrums, of the energy of the N audio frames, whether to use a first encoding method or a second encoding method to encode the current audio frame (102), where the first encoding method is an encoding method that is based on time-frequency transform and transform coefficient quantization and that is not based on linear prediction, and the second encoding method is a linear-predication-based encoding method. The method can reduce encoding complexity and ensure that encoding is of relatively high accuracy.

Abstract: It is disclosed inter alia a method for forming an audio payload frame, wherein the audio payload frame comprises: an encoded audio data frame with a first marker bit at the front of the encoded audio data frame, wherein the first marker is set to a first value, and wherein the first value denotes a type of encoded audio data in the encoded audio data frame; an extension encoded audio data frame; and a second marker bit in front of the first marker bit, wherein the second marker bit is set to a second value; and wherein the second value denotes a type of encoded audio data other than the type of encoded audio data in the encoded audio data frame.

Abstract: In a method of providing a backward and forward compatible speech codec payload format, performing the steps of providing a RTP package. Subsequently, including payload according to a first codec into the provided RTP package, and appending payload according to a second codec into the provided RTP package. In addition, locating at least one unused bit in the included first codec payload, and designating the located at least one unused bit as a codec compatibility bit. Finally, utilizing the designated at least one codec compatibility bit to provide an indication of the presence of the appended second codec payload.

Abstract: Example embodiments disclosed herein relate to noise level estimation. A method for noise level estimation is disclosed. The method includes, responsive to an increase of a signal level of a noise signal, calculating an impulsive noise probability of the noise signal, the impulsive noise probability indicating a likelihood that the noise signal is an impulsive noise. The method also includes determining a variable smoothing factor for noise level estimation based on the impulsive noise probability, the variable smoothing factor being associated with a previous estimated level of the noise signal. The method further includes smoothing the noise signal with the variable smoothing factor so as to determine a current estimated level of the noise signal. Corresponding system and computer program products are also disclosed.

Abstract: During high-frequency interpolation, a harmonic generation unit first generates a harmonic signal for an input compressed audio signal. An HPF unit, having a cutoff frequency, extracts a high frequency component from the compressed audio signal in parallel with the generation of the harmonic signal. An HPF unit, having a cutoff frequency, extracts a high frequency component from the compressed audio signal. An estimation unit estimates a missing band in the compressed audio signal on the basis of a ratio of the signal level of a difference signal to the signal level of an output signal, the difference signal being obtained by subtracting the output signal of the HPF unit from the output signal of the HPF unit. The estimation unit controls the cutoff frequency of a variable HPF unit that extracts a signal component for high-frequency interpolation from the harmonic signal on the basis of the estimated missing band.

Abstract: Methods and systems for controlling audio communications between occupants of a vehicle are provided. In accordance with one embodiment, a system includes an interface and a processor. The interface is configured to at least facilitate receiving a request for sound transmission from a first occupant inside a vehicle to a second occupant inside the vehicle. The processor is coupled to the interface, and is configured to at least facilitate identifying respective locations of the first occupant and the second occupant, and performing the sound transmission with an adjustment for a phase difference based at least in part on the respective locations of the first occupant and the second occupant.

Abstract: An estimated system gain spectrum of an acoustic system is generated, and updated in real-time to respond to changes in the acoustic system. Peak gains in the estimated system gain spectrum are tracked as the estimated system gain spectrum is updated. Based on the tracking, at least one frequency at which the estimated system gain spectrum is currently exhibiting a peak gain is identified. Based on the identification of the at least one frequency, an audio equalizer is controlled to apply, to a first speech containing signal to be played out via an audio output device of the audio device and/or to a second speech containing signal received via an audio input device of the audio device, an equalization filter to reduce the level of that signal at the identified frequency. The equalization filter is applied continuously throughout intervals of both speech activity and speech inactivity in that signal.

Abstract: A sound processing circuit comprises a first input for receiving a first input signal, and a second input for receiving a second input signal. A first adaptive filter receives the first input signal, and an error calculation block calculates an error between the second input signal and the output of the first adaptive filter, and outputting an error signal. A second adaptive filter receives the error signal, and an output calculation block subtracts an output of the second adaptive filter from the first input signal to generate an output signal. The adaptation of first and second adaptive filters is controlled based on a magnitude coherence between the first and second input signals.

Abstract: A method of detecting a particular abnormal sound in an environment with background noise is provided. The method includes acquiring a sound from a microphone, separating abnormal sounds from the input sound based on non-negative matrix factorization (NMF), extracting Mel-frequency cepstral coefficient (MFCC) parameters according to the separated abnormal sounds, calculating hidden Markov model (HMM) likelihoods according to the separated abnormal sounds, and comparing the likelihoods of the separated abnormal sounds with a reference value to determine whether or not an abnormal sound has occurred. According to the method, based on NMF, a sound to be detected is compared with ambient noise in a one-to-one basis and classified so that the sound may be stably detected even in an actual environment with multiple noises.

Abstract: A substrate for suspension comprises a metallic substrate, an insulating layer formed on the metallic substrate, a conductor layer formed on the insulating layer, and a cover layer covering the conductor layer. The insulating layer and the cover layer are formed from different materials, whose coefficients of hygroscopic expansion are in the range between 3×10?6/% RH and 30×10?6/% RH. The difference between the coefficients of hygroscopic expansion of the two materials is 5×10?6/% RH or less.

Abstract: A magnetic write head is positioned based on position signals generated by a read head as the read head crosses a plurality of reference spirals. The spiral gate for monitoring a particular reference spiral is timed to begin at a time based on the radial position of the magnetic head when crossing the preceding reference spiral. In this way, the spiral crossing time for the particular reference spiral can be estimated with sufficient accuracy that the spiral gate coincides with the magnetic head crossing the particular reference spiral. Consequently, spiral detection is assured, even in the presence of large non-repeatable runout.

Abstract: The present technology relates to a recording control apparatus, a recording control method, a drive controlling controller, a drive controlling method, a recording medium, and a program capable of reading information more reliably. A manager generates DMSs as management information for managing user data areas and spare areas of an optical disc. Further, the manager records the generated DMS in a DMA area of DS0 of the optical disc, and, in addition, records the generated DMS in a DMA mirror area of the DS1 surface of the optical disc. As described above, since DMSs as management information are recorded in the different areas of the optical disc, even if DMS cannot be read from one area, DMS can be read from the other area. The present technology is applicable to a recording and reproducing apparatus.

Abstract: There are provided an optical disk and an optical disk recording method which are capable of stable data reading in a case where a recording linear density is increased. According to an optical disk of the present disclosure, a run-in pattern recorded in a groove track and a run-in pattern recorded in a land track are made different patterns so that no great change is caused in the amplitude of an acquired signal due to interference between adjacent recording patterns, and thus, data may be stably read.

Abstract: First and second signal patterns are used to write corresponding portions of first and second adjacent tracks to a magnetic storage medium. A characteristic of the first signal pattern is changed based on the second signal pattern, the changing of the characteristic reducing an adjacent track interference affecting the second track.

Abstract: One or more processors determine wear for a robotic device. The one or more processors divide a direction of travel of a robotic device into zones. Each zone has an associated counter that counts how many times the robotic device has entered a given zone. The one or more processors update a count for a zone in response to the robotic device entering that zone. The one or more processors determine a level of wear for a component associated with the robotic device. The level of wear is based, at least in part, on a total of counts for the zones.

Abstract: A processing device provides, on a mobile device, a storyline content user interface (UI) for adding video content to a storyline, the storyline content UI having a first area including a media player, a second area including visual representations of video clips from the storyline, and a third area including a first UI element to record video content, and a second UI element to add the recorded video content to the storyline. In response to a user activation of the first UI element, the processing device initiates recording of a new video clip using the first area, creating, by a processing device, a visual representation of the new video clip, and adding the visual representation of the new video clip to the second area. In response to a user activation of the second UI element, the processing device causes the new video clip to be associated with the storyline.

Abstract: A content reproduction screen displays a plurality of content items. A video reproduction processing section reproduces substantially simultaneously videos of a plurality of content items on a screen. An audio reproduction processing section reproduces substantially simultaneously audio signals of a plurality of content items. During reproduction of a plurality of content items, a comparison is made between a current reproduction position of the audio signal in an audio reproduction processing section and a current reproduction position of each video in the video reproduction processing section, and, if a discrepancy between the compared current reproduction positions is equal to or greater than a threshold value, the current reproduction position of the video is corrected on the basis of the current reproduction position of the audio signal. In this way, the current reproduction position of each video is synchronized with the reproduction position of the audio signal.

Abstract: Certain exemplary aspects of the present disclosure are directed towards an apparatus including a base deck forming a sealed cavity. A filter coupled to a surface of the base deck within the cavity filters particulate from a flow of gas in the cavity. The recirculation filter including a protrusion extending over a surface of a storage medium within the cavity that diverts gas from a surface of the storage medium toward the filter. A bypass channel, defined by a portion of the cavity and a portion of the filter, in conjunction with the protrusion forms a pressure differential that draws a first portion of the diverted gas through the filter by bypassing the filter with a second portion of the diverted gas.

Abstract: A multi-chip package (MCP) includes semiconductor chips integrated therein. Each semiconductor chip includes: pad groups which extend in a first: direction and are arranged in a second direction, and each of which includes a first metal line and a second metal line that are stacked in a third direction with an interlayer dielectric layer interposed therebetween; receivers which one-to-one correspond to the respective pad groups, and each of which includes a first input terminal coupled with the first metal line of a corresponding pad group, and an output terminal coupled with the second metal line of the corresponding pad group; and selectors, each of which selects one of a feedback signal transferred from the output terminal of a corresponding receiver and a reference voltage, and provides the selected one to a second input terminal of the corresponding receiver, in response to a chip select signal.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a power supply voltage and first data. The second semiconductor device generates a control voltage whose level is adjusted in response to the power supply voltage. The second semiconductor device also receives the first data to generate second data having a swing width different from a swing width of the first data. The second data being driven is controlled by the control voltage.

Abstract: A memory device having: a cross-point memory array; a current supply circuit adapted to supply a programming current to a selected row line of the array during a programming operation to change the resistive state of a selected memory cell coupled between the selected row line and a selected column line of the array; a leakage current detection circuit coupled to the column lines except the selected column line and adapted to detect leakage currents during the programming operation; and a current limit generation circuit adapted to generate a current limit based on the sum of the leakage currents and on a reference current, and to supply the current limit to the current supply circuit to limit the programming current.

Abstract: Embodiments include circuits, apparatuses, and systems for programmable memory device sense amplifiers. In embodiments, an electronic circuit may include a programmable memory device having a first resistance in a first state and a second resistance in a second state, a reference element, an amplifier to generate a first output signal based at least in part on the resistance of the programmable memory device and a second output signal based at least in part on a current from the reference element, and a comparator to determine a state of the programmable memory device based on the first and second output signals from the amplifier. Other embodiments may be described and claimed.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus, the apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal, and is configured to generate a first value on a lag bus that indicates the time.

Abstract: A rotating magnetic physical unclonable function (PUF) is disclosed. Rotating the PUF enables robust low cost PUF readers. PUF may be incorporated into a user-replaceable supply item for an imaging device. A PUF reader may be incorporated into an imaging device to read the PUF. Other systems and methods are disclosed.

Abstract: A nonvolatile memory of an embodiment includes: first through fifth wirings; and a memory cell including: a first circuit including a first magnetoresistive element and a first select transistor, the first magnetoresistive element and the first select transistor being electrically connected in series, the first magnetoresistive element including a first reference layer, a first storage layer, and a first nonmagnetic layer between the first reference layer and the first storage layer; a second circuit including a second magnetoresistive element and a second select transistor, the second magnetoresistive element and the second select transistor being electrically connected in series, the second magnetoresistive element including a second reference layer, a second storage layer, and a second nonmagnetic layer between the second reference layer and the second storage layer; a third circuit including first and second transistors; and a fourth circuit including third and fourth transistors.

Abstract: At least one magnetic nanowire including multiple cells; a write-read head combined with a first contact of the magnetic nanowire; and a read-only head combined with a second contact of the magnetic nanowire. Data stored through a write head included in the write-read head are read in sequence through a read head included in the write-read head in response to a last in first out (LIFO) method.

Abstract: An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (IREAD) through the STT memory cell and to set a pulse to write the STT memory cell using IREAD. Additional embodiments are disclosed.

Abstract: Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.

Abstract: A Dual In-Line Memory Module (DIMM) Solid State Drive (SSD) System-on-a-Chip (SoC) (345) is disclosed. The DIMM SSD SoC (345) can interoperate with a host memory controller (335) as though it were a traditional Dynamic Random Access Memory (DRAM) DIMM (105, 130) with system interconnect skew and on-DIMM skew, even though the DIMM SSD SoC (345) does not have on-DIMM skew. The DIMM SSD SoC (345) can include variable delay elements (422, 424, 426, 428, 430, 432, 434, 436, 438) that can replicate the delay a traditional DRAM DIMM (105, 130) experiences and that the host memory controller (335) expects, or a superior delay that minimizes system signal integrity issues, thereby increasing maximum system speed.

Abstract: A calibration method and a calibration device for dynamic random access memory are provided. The calibration method for the dynamic random access memory includes: performing a calibration on the dynamic random access memory; and storing a calibration result generated during the calibration into a data structure so that the calibration result can be read from the data structure; wherein the data structure includes: a calibration result data region, recording the calibration result generated by performing the calibration on the dynamic random access memory. In the calibration method, the boot time of the present invention can be greatly saved.

Abstract: The present invention is provided with; subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK1 or VKK2 to the subword drivers SWD, and memory cells MC that are selected in the case when the subword line SWL is set to an active potential VPP and are not selected in the case when the subword line SWL is either a negative potential VKK1 or VKK2.

Abstract: A circuit for driving a sense amplifier of a semiconductor memory device is provided. The circuit includes a first driving circuit configured to supply a current from a power node to a first driving node of the sense amplifier based on a first driving control signal, a source control circuit configured to generate a control signal based on a second driving control signal and a voltage of the drain node, and a second driving circuit configured to draw current from a second driving node of the sense amplifier to a ground node based on the control signal.

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable, and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

Abstract: Embodiments include apparatuses, methods, and systems including a circuit which may increase a speed of removal of data stored in a memory cell. In embodiments, the circuit may include a control logic to detect a signal and a boost circuit coupled to the control logic to allow the control logic to disable an operation of the boost circuit in response to detection of the signal. A discharge device may be coupled to the boost circuit to accelerate leakage of a leakage current in response to the detection of the signal. In the embodiment, the leakage current is a leakage current of a memory cell coupled to the discharge device and acceleration of the leakage of the leakage current and the disablement of the operation of the boost circuit may increase a speed of erasure of data in the memory cell. Other embodiments may also be described and claimed.

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Abstract: A semiconductor device including a first N-type well and a second N-type well includes: a memory circuit to be coupled with first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line and electrically decouples the first power source line from the second power source line. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The first and second switches each include a first PMOS transistor arranged in the first N-type well.

Abstract: There is provided a nonvolatile memory device having a writing error preventing function with high noise resistance. This structure includes a switch and a noise filter circuit connected in parallel to a clock terminal, wherein a clock pulse monitoring circuit compares the number of clocks input from the clock terminal with a prescribed number, and when detecting abnormality in the number of clocks, switches to a noise countermeasure mode in which the switch is turned off to validate the noise filter circuit.

Abstract: In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.

Abstract: A data writing method for a solid state storage device includes following steps. A step (a) is performed to judge whether a shutdown command is issued from a host. In a step (b), if the solid state storage device confirms that the shutdown command is not issued from the host, plural program procedures are performed. Consequently, plural write data in a buffer are stored to a triple-level cell flash memory according to a program order. In a step (c), if the solid state storage device confirms that the shutdown command is issued from the host, plural redundant data are added to the plural write data, the write data are stored into the buffer, and the plural program procedures are performed. Consequently, the plural write data in the buffer are stored to the triple-level cell flash memory according to the program order.

Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.

Abstract: An example memory device includes a planar semiconductor substrate layer; a planar variable resistance layer disposed above the planar semiconductor substrate layer; a planar channel layer disposed above the planar variable resistance layer; and one or more gates positioned along a length of the memory device and above the planar channel layer, wherein each respective gate of the one or more gates is configured to direct at least a portion of a current flowing through a respective region of the planar channel layer positioned below the respective gate into a respective region of the variable resistance layer positioned below the respective gate in response to a voltage applied to the respective gate being greater than a threshold voltage.

Abstract: Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in series may be placed in complementary memory states any one of multiple memory states in write cycles by controlling a current and a voltage applied to terminals of the non-volatile memory device.

Abstract: Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. In some examples, the multi-storage state non-volatile random access memory device has two or more memory cells. Each memory cell may include a pair of programmable resistive devices that may be dynamically programmed to configure the memory cell in a particular logic state.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, connecting circuits including pass transistors coupled between global word lines and the plurality of memory cells, an address decoder coupled to block word lines coupled to gates of the pass transistors and the global word lines, and a control logic controlling the address decoder and applying a voltage pulse to the global word lines and the block word lines according to an operation state of the semiconductor memory device.

Abstract: A semiconductor memory device includes a plurality of memory blocks. The semiconductor memory device also includes a block decoder configured to output a block select signal for selecting at least one memory block of the plurality of memory blocks to at least one block word line of a plurality of word lines, and a connecting circuit including a plurality of pass transistors configured to electrically connect global lines to local lines of a plurality of memory cells included in the plurality of memory blocks in response to the block select signal. The semiconductor device may also include a control logic configured to apply a voltage pulse to global word lines and a ground voltage to global select lines of the global lines, and the voltage pulse to at least the one block word line while the semiconductor memory device is in a ready state.

Abstract: Disclosed is an effective programming method for non-volatile flash memory including memory cells, each formed of a select transistor and a floating transistor. The method includes imposing a positive voltage onto a control gate of the floating transistor as a word line, supplying a zero voltage to a triple well, a deep N well, and a select gate of the select transistor to turn off the select transistor, and finally providing a moderate positive voltage to a drain of the control transistor. Owing to the junction band-to-band tunneling effect, the electron of the hole-electron pair generated between the junction of the bit line and the triple well leaps to the floating gate of the floating transistor driven by the positive electric field to form a higher threshold voltage for the memory cell such that the process of programming is accomplished.

Abstract: Provided herein is a semiconductor memory device including a memory cell array including a drain select transistor and a plurality of memory cells, a voltage generator configured to apply a program voltage, first and second pass voltages, and a drain control voltage to the memory cell array, a control logic configured to control the voltage generator so that during a program operation, after the program voltage is applied to a selected one of the plurality of memory cells, the program voltage applied to the selected memory cell is discharged while the first pass voltage or the second pass voltage is applied to memory cells adjacent to the selected memory cell.

Abstract: A data storage device including a flash memory and a controller. The flash memory includes a plurality of pages and a plurality of word lines, wherein each of the word lines controls at least two of the pages. The controller reads a first page of the pages in response to a read command, wherein the first page is controlled by a first word line of the word lines, and the controller further writes dummy data into the pages controlled by the first word line other than the first page when a predetermined condition is satisfied, wherein the predetermined condition includes that the first word line is not close.