Patents Issued in April 13, 2017
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Publication number: 20170103916Abstract: A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.Type: ApplicationFiled: June 14, 2016Publication date: April 13, 2017Inventors: Yong-Ho JEON, Sang-Su KIM, Cheol KIM, Yong-Suk TAK, Myung-Geun SONG, Gi-Gwan PARK
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Publication number: 20170103917Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.Type: ApplicationFiled: July 28, 2016Publication date: April 13, 2017Inventors: XIUYU CAI, CHUN-CHEN YEH, QING LIU, RUILONG XIE
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Publication number: 20170103918Abstract: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Inventors: Audrey Hsiao-Chiu Hsu, Fu-Kai Yang, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Hsin-Ying Lin
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Publication number: 20170103919Abstract: A fabrication method for a semiconductor device is provided. The fabrication method for a semiconductor device includes a semiconductor chip arraying step of arraying a plurality of semiconductor chips at given distances on a first face of a substrate that serves as a supporting body, a substrate thinning step of grinding a second face of the substrate at the side opposite to the first face to thin the substrate to a given thickness, a through electrode formation step of forming a through-hole that extends from the second face side to the semiconductor chip at a given position of the thinned substrate and embedding metal into the through-hole to form a through electrode, and a wiring layer formation step of forming a wiring layer at the second face side of the substrate.Type: ApplicationFiled: September 30, 2016Publication date: April 13, 2017Inventor: Youngsuk Kim
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Publication number: 20170103920Abstract: A wafer processing method including a protective plate attaching step of attaching a protective plate to the front side of a wafer, a support member providing step of providing a support member on the back side of the wafer, a protective plate cutting step of cutting the protective plate along an area corresponding to each division line formed on the front side of the wafer, thereby exposing each division line, and a plasma etching step of performing plasma etching through the protective plate to each division line of the wafer, thereby etching each division line to divide the wafer into individual device chips.Type: ApplicationFiled: October 5, 2016Publication date: April 13, 2017Inventor: Kazuma Sekiya
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Publication number: 20170103921Abstract: A processing method for optical device wafers includes a shielded tunnel forming step and a dividing step. In the shielded tunnel forming step, a sapphire substrate is irradiated with a pulse laser beam having such a wavelength as to be transmitted through the sapphire substrate along regions corresponding to planned dividing lines. The light focus point of the beam is positioned inside the substrate from the back surface side of the substrate. Fine pores and amorphous regions that shield the fine pores form shielded tunnels along the planned dividing lines. In the dividing step, an external force is applied to the optical device wafer, and the optical device wafer is divided into individual optical device chips along the planned dividing lines. In the shielded tunnel forming step, a spherical aberration is generated by causing the laser beam to be incident on a condensing lens with a divergence angle.Type: ApplicationFiled: October 12, 2016Publication date: April 13, 2017Inventors: Takumi Shotokuji, Noboru Takeda, Naotoshi Kirihara
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Publication number: 20170103922Abstract: De are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a plate structure to apply a pressure to the wafer to separate the back layer in the singulation lines. The pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Gordon M. GRIVNA
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Publication number: 20170103923Abstract: An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, a drain region having a drain width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the apparatus includes at least one of (a) the channel region width being wider than the source region width, and (b) the gate dielectric including a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location, the first and second locations located at an equivalent height on the sidewall and the first and second gate dielectrics thicknesses being unequal to one another. Other embodiments are described herein.Type: ApplicationFiled: June 27, 2014Publication date: April 13, 2017Inventors: NIDHI NIDHI, CHIA-HONG JAN, ROMAN W. OLAC-VAW, HSU-YU CHANG, NEVILLE L. DIAS, WALID M. HAFEZ, RAHUL RAMASWAMY
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Publication number: 20170103924Abstract: Example embodiments of inventive concepts provide a method for inspecting and/or observing photoresist patterns. The inspecting and/or observing methods may include forming at least an anti-reflective layer on a substrate, forming a fluorescent photoresist pattern on the anti-reflective layer, the fluorescent photoresist pattern having fluorescence, and observing and/or inspecting a shape of the fluorescent photoresist pattern using a fluorescence microscope.Type: ApplicationFiled: August 31, 2016Publication date: April 13, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Kyung Jae Park, Wooseok SHIM
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Publication number: 20170103925Abstract: A method for measuring a substrate is provided. The method comprises irradiating a measurement beam into a site box of an identifiable pattern of a substrate, detecting a center position of the irradiated measurement beam, calculating an amount of shift of the center position of the measurement beam from the center position of the site box, and correcting the center position of the measurement beam to the center position of the site box by compensating the calculated amount of shift.Type: ApplicationFiled: July 24, 2016Publication date: April 13, 2017Inventors: Chol-Min JHON, Seok PARK, Ho-Hyung JUNG, Yang-Kyu KIM, Jae-Young LEE
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Publication number: 20170103926Abstract: A mounting substrate according to an embodiment of the present technology includes: a wiring substrate (30); a plurality of light-emitting elements (12) arranged in a matrix on the wiring substrate; and a plurality of drive ICs (13) that are arranged in a matrix on the wiring substrate, and control light emission of the light-emitting elements. The light-emitting elements and the drive ICs are mounted on a same surface. The wiring substrate includes a plurality of first wiring lines (16) on a mounting surface whre the light-emitting elements and the dive ICs are mounted. The first wiring lines electrically couple the light-emitting elements to the drive ICs.Type: ApplicationFiled: March 17, 2015Publication date: April 13, 2017Applicant: Sony CorporationInventors: Akiyoshi Aoyagi, Ken Kikuchi, Katsuhiro Tomoda
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Publication number: 20170103927Abstract: A method of making a semiconductor device can include forming an embedded die panel by encapsulating a first semiconductor die and a second semiconductor die with conductive interconnects in a single step. An actual position of the first semiconductor die and second semiconductor die can be measured within the embedded die panel. The first semiconductor die and the second semiconductor die can be interconnected by a build-up interconnect structure comprising a first unit specific alignment portion aligned with the first semiconductor die, a second unit specific alignment portion aligned with the second semiconductor die, unit specific routing connecting the first unit specific alignment portion and the second unit specific alignment portion, and a fixed portion aligned with outline of embedded die panel and coupled to the unit specific routing.Type: ApplicationFiled: October 11, 2016Publication date: April 13, 2017Inventor: Craig Bishop
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Publication number: 20170103928Abstract: A polishing method capable of obtaining an accurate thickness of a silicon layer during polishing of a substrate and determining an accurate polishing end point of the substrate based on the thickness of the silicon layer obtained. The method includes: calculating relative reflectance by dividing the measured intensity of the infrared ray by predetermined reference intensity; producing spectral waveform representing relationship between the relative reflectance and wavelength of the infrared ray; performing a Fourier transform process on the spectral waveform to determine a thickness of the silicon layer and a corresponding strength of frequency component; and determining a polishing end point of the substrate based on a point of time when the determined thickness of the silicon layer has reached a predetermined target value.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Inventor: Toshifumi KIMBA
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Publication number: 20170103929Abstract: A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.Type: ApplicationFiled: July 5, 2016Publication date: April 13, 2017Inventors: Bo-Ra LEE, Jae-Ho JEONG, Nam-Gyu BAEK, Hyo-Seok WOO, Hyun-Sook YOON, Kwang-Yong LEE
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Publication number: 20170103930Abstract: A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips includes a delay chain. Each of the plurality of stacked chips comprises a plurality of Through-Vias, wherein one of the plurality of Through-Vias formed in a first one of the plurality of stacked chips and electrically coupled to a predetermined location of a first delay chain on the first one of the plurality of stacked chips and one of the plurality of Through-Vias formed in a neighboring one of the plurality of stacked chips and electrically coupled to a predetermined location of a delay chain on the neighboring one of the plurality of stacked chips are configured to electrically couple the first one of the plurality of stacked chips to the neighboring one of the plurality of stacked chips. A signal transmitted from a first one of the plurality of stacked chips generates a feedback signal to the first one of the plurality of stacked chips through one or more of the plurality of Through-Vias.Type: ApplicationFiled: December 15, 2016Publication date: April 13, 2017Inventor: Sang Ho LEE
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Publication number: 20170103931Abstract: The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Inventor: Lee D. Whetsel
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Publication number: 20170103932Abstract: A semiconductor apparatus includes a semiconductor device, on-semiconductor-device metal pad and metal interconnect each electrically connected to the semiconductor device, a through electrode and a solder bump each electrically connected to the metal interconnect, a first insulating layer on which the semiconductor device is placed, a second insulating layer formed on the semiconductor device, a third insulating layer formed on the second layer. The metal interconnect is electrically connected to the semiconductor device via the on-semiconductor-device metal pad at an upper surface of the second layer, penetrates the second layer from its upper surface, and is electrically connected to the through electrode at an lower surface of the second layer, and an under-semiconductor-device metal interconnect is between the first layer and the semiconductor device, and the under-semiconductor-device metal interconnect is electrically connected to the metal interconnect at the lower surface of the second layer.Type: ApplicationFiled: March 12, 2015Publication date: April 13, 2017Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Katsuya TAKEMURA, Kyoko SOGA, Satoshi ASAI, Kazunori KONDO, Michihiro SUGO, Hideto KATO
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Publication number: 20170103933Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.Type: ApplicationFiled: December 22, 2016Publication date: April 13, 2017Inventors: Chih-Horng Chang, Tin-Hao Kuo, Tsung-Fu Tsai, Min-Feng Ku
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Publication number: 20170103934Abstract: A heat sink for a semiconductor chip device includes cavities in a lower surface thereof for receiving electrical components on a top surface of the semiconductor chip, and a pedestal extending through an opening in the semiconductor chip for contacting electrical components on a bottom surface of the semiconductor chip. A lid may also be provided on the bottom surface of the semiconductor chip for protecting the electrical components and for heat sinking the electrical components to an adjacent device or printed circuit board.Type: ApplicationFiled: December 6, 2016Publication date: April 13, 2017Inventor: Nathan A. Nuttall
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Publication number: 20170103935Abstract: A flow passage member includes a wall formed of ceramics, a space surrounded by the wall being a flow passage through which a fluid flows, a ratio of an area occupied by a grain boundary phase in an inner surface of a wall part of the wall in which wall part heat exchange is conducted being smaller than a ratio of an area occupied by a grain boundary phase in an outer surface of the wall part.Type: ApplicationFiled: March 25, 2015Publication date: April 13, 2017Inventors: Yuusaku ISHIMINE, Kenji KOMATSUBARA
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Publication number: 20170103936Abstract: DBC type structure, comprising an insulating support (22) coated with at least one conductive zone (20a) able to receive an electronic device, the conductive zone (20a) being in contact with the support (22), the insulating support incorporating means for thermal smoothing of the heat peak released by the component, these means comprising a cavity filled with a phase change material (FIG. 1).Type: ApplicationFiled: October 3, 2016Publication date: April 13, 2017Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Ulrich SOUPREMANIEN, Emmanuel OLLIER, Sebastien QUENARD, Maryline ROUMANIE, Helga SZAMBOLICS
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Publication number: 20170103937Abstract: Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.Type: ApplicationFiled: October 9, 2015Publication date: April 13, 2017Inventors: Cheng-Chieh Hsieh, Chi-Hsi Wu, Shin-Puu Jeng, Tsung-Yu Chen, Wensen Hung
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Publication number: 20170103938Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Inventor: Masamichi Ishihara
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Publication number: 20170103939Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device. The method comprises providing a lead frame, the lead frame having I/O terminals surrounding a die attach region, the lead frame defined onto a temporary carrier. A device die is attached onto the die-attach region. The device die is wire bonded to the I/O terminals, the I/O terminals located in a first position. In a molding compound the wire-bonded device die and lead frame are encapsulated. The temporary carrier is removed from the lead frame, underside surfaces of the device die and I/O terminals are exposed. Applying a non-conductive layer to the exposed underside surfaces of the device die and I/O terminals, thereby defines features in which conductive traces may be defined from the I/O terminals in the first position to customized I/O terminals located in a second position.Type: ApplicationFiled: October 9, 2015Publication date: April 13, 2017Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert, Tonny Kamphuis
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Publication number: 20170103940Abstract: On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Inventors: Akira MUTO, Koji BANDO, Yukihiro SATO, Kazuhiro MITAMURA
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Publication number: 20170103941Abstract: Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer and a dielectric loss tangent greater than a dielectric loss tangent of the second layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: May 13, 2015Publication date: April 13, 2017Inventors: Zheng Zhou, Mihir K. Roy, Chong Zhang, Kyu-Oh Lee, Amanda E. Schuckman
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Publication number: 20170103942Abstract: A wiring substrate includes a first connection terminal and a protective insulation layer. The first connection terminal is electrically connected to a wiring layer by a via wiring and projects upward from an upper surface of an insulation layer. The protective insulation layer is located on the upper surface of the insulation layer to contact and cover a portion of a side surface of the first connection terminal. The first connection terminal includes a lower portion that is continuous with the via wiring and an upper portion that is continuous with the lower portion. The lower portion is smaller in crystal grain size than the upper portion. The lower portion and the upper portion are formed from the same metal material. The side surface of the lower portion has a higher roughness degree than the side surface of the upper portion.Type: ApplicationFiled: October 4, 2016Publication date: April 13, 2017Inventors: KIYOSHI OI, TOMOTAKE MINEMURA
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Publication number: 20170103943Abstract: A package substrate for chip/chips package wrapped by a molding compound is disclosed. The molding compound functions as a stiffener for the thin film package substrate. One embodiment discloses at least one redistribution layer (RDL) is prepared and the RDL is wrapped by a molding compound. The molding compound wraps four lateral sides and bottom side of the RDL. A top side of the RDL is made for a chip to mount and a bottom side of the RDL is planted a plurality of solder balls so that the bottom side of the chip package is adaptive to mount onto a system board in a later process.Type: ApplicationFiled: October 8, 2015Publication date: April 13, 2017Inventor: Dyi-Chung HU
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Publication number: 20170103944Abstract: A wiring substrate includes a laminated sheet including a first conductor pattern, an inorganic dielectric layer, and a second conductor pattern. The first conductor pattern, the inorganic dielectric layer, and the second conductor pattern are laminated in this order. Also, the first conductor pattern is divided into a plurality of regions.Type: ApplicationFiled: September 28, 2016Publication date: April 13, 2017Applicants: FUJITSU LIMITED, SONY CORPORATIONInventors: Kei FUKUI, Kazuya Arai, Koji Komemura, Kazuhiko Iijima, Kenichiro Abe, Shinji Rokuhara, Shuichi Oka
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Publication number: 20170103945Abstract: A wiring substrate used for improvement in manufacturing efficiency of a semiconductor device includes a support body having transparency; an adhesive layer disposed on a main surface of the support body, the adhesive layer including a peeling layer which contains a third resin which is decomposed by light irradiation and a protective layer which is disposed on the peeling layer and contains a fourth resin; and a laminate disposed on the adhesive layer, the laminate including a first resin layer, a second resin layer disposed on the first resin layer, and a wiring pattern disposed at least between the first resin layer and the second resin layer. Accordingly, the semiconductor chip and the wiring substrate which is the external connection member can be separately manufactured, thereby improving manufacturing efficiency of the semiconductor device.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Applicant: TOPPAN PRINTING CO., LTD.Inventors: Akane KOBAYASHI, Yoshito AKUTAGAWA
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Publication number: 20170103946Abstract: A semiconductor device includes a substrate, at least one integrated passive device, a first redistribution layer, a second redistribution layer, and conductive vias. The at least one integrated passive device includes at least one capacitor disposed adjacent to a first surface of the substrate. The first redistribution layer is disposed adjacent to the first surface of the substrate. The second redistribution layer is disposed adjacent to a second surface of the substrate. The conductive vias extend through the substrate, and electrically connect the first redistribution layer and the second redistribution layer.Type: ApplicationFiled: June 10, 2016Publication date: April 13, 2017Inventors: Yung-Shun Chang, Chien-Hua Chen, Teck-Chong Lee
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Publication number: 20170103947Abstract: An eFuse device on a substrate is formed on a substrate used for an integrated circuit. A semiconductor structure is created from a semiconductor layer deposited over the substrate. A mask layer is patterned over the semiconductor structure such that a first region of the semiconductor structure is exposed and a second region of the semiconductor structure is protected by the mask layer. Next, a self-limiting etch is performed on the exposed areas in the first region of the semiconductor structure, producing a first faceted region of the semiconductor structure in the first region. The semiconductor in the first faceted region has a minimum, nonzero thickness at a point where two semiconductor facet planes meet which is thinner than a thickness of semiconductor in the second region of the semiconductor structure is protected by the mask layer. The first faceted region is used as a link structure in the eFuse device.Type: ApplicationFiled: October 12, 2015Publication date: April 13, 2017Inventors: Kangguo Cheng, Ali Khakifirooz, Juntao Li, Werner A Rausch
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Publication number: 20170103948Abstract: An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first direction, a gate line extending on the at least one fin-shaped active region in a second direction, the second direction intersecting with the first direction, a conductive region on a portion of the at least one fin-shaped active region at one side of the gate line, and a contact plug extending from the conductive region in a third direction, the third direction being perpendicular to a main plane of the substrate, may be provided. The contact plug may include a metal plug, a conductive barrier film on the conductive region, the conductive barrier film surrounding a sidewall and a bottom surface of the metal plug, the conductive barrier film including an N-rich metal nitride film, and a metal silicide film between the conductive region and the conductive barrier film.Type: ApplicationFiled: June 20, 2016Publication date: April 13, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Do-sun LEE, Do-hyun LEE, Chul-sung KIM, Sang-jin HYUN, Joon-gon LEE
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Publication number: 20170103949Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.Type: ApplicationFiled: October 9, 2015Publication date: April 13, 2017Inventors: Chi-Lin Teng, Jung-Hsun Tsai, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao
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Publication number: 20170103950Abstract: In a resin structure including a resin molded body and a plurality of electronic components embedded in the resin molded body, (i) the resin molded body has a plurality of exposed surfaces on which electrodes of the plurality of electronic components are exposed, (ii) the resin molded body has a recess formed therein, and (iii) the recess has a bottom surface which is at least one of the plurality of exposed surfaces.Type: ApplicationFiled: March 26, 2015Publication date: April 13, 2017Applicant: OMRON CORPORATIONInventor: Wakahiro KAWAI
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Publication number: 20170103951Abstract: A fan-out semiconductor package may include: a first connection member having a through hole; a semiconductor chip disposed in the through hole and having an active surface on which a connection pad is disposed and a non-active surface opposing the active surface; an encapsulant at least partially encapsulating the first connection member and the non-active surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad, wherein the first connection member includes a first insulating layer, a first redistribution layer embedded in the first insulating layer while contacting the second connection member, and a second redistribution layer disposed on the other side of the first insulating layer opposing one side thereof in which the first redistribution layer is embedded.Type: ApplicationFiled: October 5, 2016Publication date: April 13, 2017Inventors: Doo Hwan LEE, Kyung Seob OH, Jong Rip KIM, Hyoung Joon KIM
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Publication number: 20170103952Abstract: A device having an integrated noise shield is disclosed. The device includes a plurality of vertical shielding structures substantially surrounding a semiconductor device. The device further includes an opening above the semiconductor device substantially filled with a conductive fluid, wherein the plurality of vertical shielding structures and the conductive fluid shield the semiconductor device from ambient radiation. In some embodiments, the device further includes a conductive bottom shield below the semiconductor device shielding the semiconductor device from ambient radiation. In some embodiments, the opening is configured to allow a biological sample to be introduced into the semiconductor device. In some embodiments, the vertical shielding structures comprise a plurality of vias, wherein each of the plurality of vias connects more than one conductive layers together.Type: ApplicationFiled: August 18, 2016Publication date: April 13, 2017Inventor: Roger J.A. Chen
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Publication number: 20170103953Abstract: A package structure includes a carrier, an electronic component disposed on the carrier, an encapsulant formed on the carrier for encapsulating the electronic component, a first shielding layer formed on the encapsulant, and a second shielding layer formed on the first shielding layer. The first and second shielding layers are made of different materials. With the multiple shielding layers formed on the encapsulating layer, the electronic component is protected from electromagnetic interferences. The present invention also provides a method for fabricating the package structure.Type: ApplicationFiled: October 20, 2016Publication date: April 13, 2017Inventors: Chih-Hsien Chiu, Hsin-Lung Chung, Cho-Hsin Chang, Chia-Yang Chen, Chao-Ya Yang
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Publication number: 20170103954Abstract: Some embodiments of the present disclosure relate to a three dimensional integrated circuit (3DIC) structure. The 3DIC structure has a first die and a second die that is bonded to the first die by one or more bonding structures. The one or more bonding structures respectively have a first metal pad arranged on the first die and a second metal pad arranged on the second die. A first plurality of support structures are disposed between the first die and the second die. The first plurality of support structures include polymers and are laterally spaced apart from a closest one of the one or more bonding structures. The first plurality of support structures extend below an upper surface of the second metal pad.Type: ApplicationFiled: December 23, 2016Publication date: April 13, 2017Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin
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Publication number: 20170103955Abstract: A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Inventors: YUNG-PING CHIANG, CHAO-WEN SHIH, HAO-YI TSAI, MIRNG-JI LII
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Publication number: 20170103956Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.Type: ApplicationFiled: October 14, 2016Publication date: April 13, 2017Inventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
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Publication number: 20170103957Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.Type: ApplicationFiled: October 7, 2015Publication date: April 13, 2017Applicant: Invensas CorporationInventors: Xuan Li, Rajesh Katkar, Long Huynh, Laura Wills Mirkarimi, Bongsub Lee, Gabriel Z. Guevara, Tu Tam Vu, Kyong-Mo Bang, Akash Agrawal
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Publication number: 20170103958Abstract: A semiconductor package includes a semiconductor chip mounted on a substrate that has a top surface and a bottom surface opposite to each other, and connection members that connect the substrate and the semiconductor chip to each other. The connection members include first connection members disposed on a central region of the semiconductor chip and that have heights equal to each other, and second connection members disposed on an edge region of the semiconductor chip and that have heights equal to each other. The heights of the first connection members differ from the heights of the second connection members.Type: ApplicationFiled: July 19, 2016Publication date: April 13, 2017Inventors: CHANHO LEE, MYEONG SOON PARK, HYUNSOO CHUNG
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Publication number: 20170103959Abstract: An anisotropic conductive film that can be produced in high productivity and can reduce a short circuit occurrence ratio has a first conductive particle layer in which conductive particles are dispersed at a predetermined depth in a film thickness direction, and a second conductive particle layer in which conductive particles are dispersed at a depth different from that in the first conductive particle layer. In the respective conductive particle layers, the closest distances between the adjacent conductive particles are 2 times or more the average particle diameters of the conductive particles.Type: ApplicationFiled: March 20, 2015Publication date: April 13, 2017Applicant: DEXERIALS CORPORATIONInventors: Yasushi AKUTSU, Yuta ARAKI
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Publication number: 20170103960Abstract: A semiconductor device includes: an insulating substrate; an aluminum pattern made of a pure aluminum or alloy aluminum material and formed on the insulating substrate; a plating formed on a surface of the aluminum pattern; and a semiconductor element joined to the plating, wherein a thickness of the plating is 10 ?m or more.Type: ApplicationFiled: June 6, 2016Publication date: April 13, 2017Applicant: Mitsubishi Electric CorporationInventors: Daisuke MURATA, Yuji IMOTO
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Publication number: 20170103961Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.Type: ApplicationFiled: December 22, 2016Publication date: April 13, 2017Inventors: Choon Kuan Lee, Chin Hui Chong, David J. Corisis
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Publication number: 20170103962Abstract: A lead frame has a first sink, an island, and a control terminal The lead frame is bent, and at a rear surface, the island is positioned closer to one surface of a resin molded body than the first sink and a passive component mounting portion of the control terminal. A passive component is mounted on the passive component mounting portion of the control terminal through a bonding material, the passive component mounting portion being a part of one surface.Type: ApplicationFiled: March 23, 2015Publication date: April 13, 2017Applicant: DENSO CORPORATIONInventors: Syoichirou OOMAE, Akira IWABUCHI
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Publication number: 20170103963Abstract: A fluxless bonding process is provided. An array of micro solder bumps of a first semiconductor structure is aligned to an array of bonding pads of a second semiconductor structure under an applied bonding force. An environment is provided to prevent oxides from forming on the solder bump structures and bonding pads during the bonding process. A scrubbing process is performed at a given scrubbing frequency and amplitude to scrub the micro solder bumps against the bonding pads in a direction perpendicular to the bonding. Heat is applied to at least the first semiconductor structure to melt and bond the micro solder bumps to the bonding pads. The first semiconductor structure is cooled down to solidify the molten solder. Coplanarity is maintained between the bonding surfaces of the semiconductor structures within a given tolerance during the scrubbing and cooling steps until solidification of the micro solder bumps.Type: ApplicationFiled: February 25, 2016Publication date: April 13, 2017Inventors: Katsuyuki Sakuma, Thomas Weiss
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Publication number: 20170103964Abstract: In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Inventors: Christopher Andrew Bower, Matthew Meitl, David Gomez, Salvatore Bonafede, David Kneeburg
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Publication number: 20170103965Abstract: A data storage device may include a package substrate, and an upper semiconductor chip disposed above a top surface of the package substrate. At least one lower bump is disposed on a bottom surface of the package substrate. A lower semiconductor chip is disposed on the bottom surface of the package substrate and spaced apart from the at least one lower bump. The lower semiconductor chip is thinner than the at least one lower bump.Type: ApplicationFiled: September 27, 2016Publication date: April 13, 2017Inventor: KILSOO KIM