Abstract: A tunable resonator includes at least one tunable capacitor coupled with at least one tunable inductor. The tunable resonator includes a mechanical tuning mechanism coupled with a connecting bridge and with first and second electrodes of the tunable inductor. The mechanical tuning mechanism also moves the first and second electrodes of the tunable inductor relative to an electrode of the tunable capacitor, and providing a force down onto or to pull up a connecting bridge to tune the tunable inductor.

Abstract: A system and method for powering and communicating with wireless sensors are provided. One system includes a radio-frequency (RF) transmitter configured to transmit at least one of RF power signals or RF communication signals and a coupling circuit configured to couple the RF transmitter to electrical wiring to allow transmission of the RF power signals or the RF communication signals through the electrical wiring. The system also includes a connector configured to couple the RF transmitter to a power outlet of the electrical wiring.

Abstract: A near field communication (NFC) or Radio Frequency Identification (RFID) reader device for contact-less communication includes a transmitter block connected to an antenna via a matching circuitry. An electromagnetic carrier signal and modulated data information are emitted via this main antenna. Any secondary object brought into the vicinity of the main antenna influences the primary resonant circuit resulting in a load change seen by the transmitter. This detuning can cause increased power consumption, RF (Radio Frequency) standard incompliance, and device damage. The present disclosure describes devices and methods on how to detect detuning and how to regulate the transmitter's output.

Abstract: In one embodiment, a switching circuit includes a first switch comprising one or more transistors operably coupled in series with a first terminal, wherein each of the one or more transistors has a corresponding diode, a drain of each of the one or more transistors being operably coupled to a cathode of the corresponding diode; and a second switch comprising one or more transistors operably coupled in series with a second terminal, wherein each of the one or more transistors has a corresponding diode, a drain of each of the one or more transistors being operably coupled to a cathode of the corresponding diode; wherein a source of the one or more transistors of the first switch is operably coupled to a source of the one or more transistors of the second switch.

Abstract: A surface acoustic wave (SAW) device includes: a substrate, an interdigitated transducer including a plurality of interdigitated fingers disposed on a first surface of the substrate, and a reflector including a plurality of gratings also disposed on the first surface. At least one of: (1) a first group of the interdigitated fingers has a first finger pitch and a first finger metal pitch ratio, and a second group of the interdigitated fingers has a second finger pitch different from the first metal pitch and a second metal pitch ratio different from the first metal pitch ratio; and (2) a first group of the gratings has a first grating pitch and a first grating metal pitch ratio, and a second group of the gratings has a second grating metal pitch different from the first grating metal pitch and a second grating metal pitch ratio different from the first grating metal pitch ratio.

Abstract: Multi-state radio frequency (RF) attenuator configurations that include bridged-T type, pi-type, and T-type structures each having a programmable throughput section and a coupled programmable shunt section. The throughput sections and shunt sections may be configured in various combinations of parallel and serial fixed or selectable resistance elements such that multiple resistance states and impedance matching states can be programmatically selected, and may include stacked switch elements to withstand applied voltages to a specified design level.

Abstract: A master-slave flip-flop includes a master latch, a slave latch, a first logic gate and a signal transition detector. The first logic gate is receiving a reference clock and a first control clock, and outputting a first trigger signal to control one of the master latch and the slave latch, which are connected with a logic circuit, to switch to an opaque state or a transparent state, wherein the other one of the master latch and the slave latch is switched to an opaque state or a transparent state according to the reference clock. The above-mentioned master-slave flip-flop can correct sampling when a timing error occurs.

Abstract: A oscillator includes a substrate having a first surface and a second surface, a first wiring layer and a second wiring layer disposed respectively on the first and second surfaces, and a plurality of through holes electrically connecting the first and second wiring layers to each other, a resonator disposed above the first surface of the substrate, and having a resonator element, a pair of electrodes sandwiching the resonator element, and a pair of terminals adapted to electrically connect the pair of electrodes to the first electrode layer, and at least one semiconductor device disposed on the second surface of the substrate, adapted to generate an oscillation signal, and having first and second terminals electrically connected respectively to the pair of terminals of the resonator via the second wiring layer and the first wiring layer, and a third terminal supplied with a digital control signal, wherein a distance between each of the first and second terminals and the pair of terminals of the resonator is

Abstract: A driver integrated circuit includes a bootstrap circuit (BSC) configured to output a boot power supply voltage (VB) based on a first power supply voltage, the boot power supply voltage being higher than the first power supply voltage; a level shift circuit (LSC) configured to output an output pulse signal based on an input pulse signal and the boot power supply voltage; a high side driving circuit (HSU) configured to output a high side driving voltage based on the boot power supply voltage and the output pulse signal, wherein the bootstrap circuit includes a sense metal oxide semiconductor (MOS) transistor and a boot MOS transistor, wherein the sense MOS transistor includes a depression-type transistor.

Abstract: According to embodiments of the present invention, an oscillator is provided. The oscillator includes a switched capacitor circuit arrangement configured to generate a predetermined voltage, a transconductance-capacitor filter configured to receive the predetermined voltage and a reference voltage, and to generate an output filter voltage based on a differential result between the predetermined voltage and the reference voltage, wherein a value of the output filter voltage is variable in response to the differential result, and a period control circuit arrangement configured to receive the output filter voltage, and further configured to generate an oscillator signal, wherein a period of the oscillator signal is variable in response to the value of the output filter voltage, wherein the oscillator is configured to control the switched capacitor circuit arrangement based on the oscillator signal to generate the predetermined voltage to be matched to the reference voltage.

Abstract: A semiconductor device includes a skew sensing block configured to generate a first output signal according to a driving force for driving a first internal node and generate a second output signal according to a driving force for driving a second internal node, in response to an input signal; and a skew control signal generation block configured to generate skew control signals for controlling a skew of an internal circuit, by the first and second output signals.

Abstract: A half bridge circuit includes a sapphire substrate, a GaN upper switch on the sapphire substrate, a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch, a first conductor coupled to the upper switch, a second conductor coupled to the lower switch, and a capacitor. A portion of the first conductor and a portion of the second conductor are on a plane vertically separated from the upper switch and the lower switch by a height, and the capacitor is coupled between the portion of the first conductor and the portion of the second conductor.

Abstract: Methods and systems for operating a double-base bidirectional power bipolar transistor. Two timing phases are used to transition into turn-off: one where each base is shorted to its nearest emitter/collector region, and a second one where negative drive is applied to the emitter-side base to reduce the minority carrier population in the bulk substrate. A diode prevents reverse turn-on while negative base drive is being applied.

Abstract: A drive device for controlling a power switching element to turn on and off includes: an on-side circuit performing an on operation of the power switching element; an off-side circuit performing an off operation of the power switching element; and a temperature detector detecting a temperature. At least one of the on-side and off-side circuits includes a current path for supplying or drawing a gate current of the power switching element and a switch circuit for switching the gate current. The switch circuit transitionally changes the gate current based on the temperature of the power switching element when the switching circuit switches the gate current.

Abstract: A sample-and-hold circuit having an error correction circuit portion that compensates for charge injection and noise. The error correction circuit portion includes an error-current-accumulating capacitor and a feedback circuit. The error-correction circuit performs error correction during a sampling operation by accumulating, at the error-current-accumulating capacitor, an error current output from an amplifier of the sample-and-hold circuit, and then applying, via the feedback circuit, a voltage boost to an input of the amplifier. The magnitude of the voltage boost depends on a voltage of the error-current-accumulating capacitor, and on various design parameters of the components of the circuit. By appropriately setting the design parameters, the magnitude of the fed-back voltage boost can be made to cancel out error due to charge injection and noise.

Abstract: An improved analog switch for use in an ultrasound elastography probe is disclosed. The improved analog switch results in less heat dissipation compared to prior art analog switches.

Abstract: Switches comprising a normally-off semiconductor device and a normally-on semiconductor device in cascode arrangement are described. The switches include a capacitor connected between the gate of the normally-on device and the source of the normally-off device. The switches may also include a zener diode connected in parallel with the capacitor between the gate of the normally-on device and the source of the normally-off device. The switches may also include a pair of zener diodes in series opposing arrangement between the gate and source of the normally-off device. Switches comprising multiple normally-on and/or multiple normally-off devices are also described. The normally-on device can be a JFET such as a SiC JFET. The normally-off device can be a MOSFET such as a Si MOSFET. The normally-on device can be a high voltage device and the normally-off device can be a low voltage device. Circuits comprising the switches are also described.

Abstract: A power-on-reset circuit includes an execution circuit and a control circuit. The execution circuit includes a first input terminal connected to a power supply, a second input terminal and the first output terminal each initially are at a low level. The first output terminal transitions from the low level to a high level when the first input terminal and the second input terminal have a voltage not less than a predetermined voltage. The control circuit includes a third input terminal connected to the first output terminal, a fourth input terminal connected to the first input terminal, and a second output terminal connected to the second input terminal. The second input terminal transitions from the low level to the high level when a difference between the voltage at the first input terminal and the voltage at the first output terminal is greater than the predetermined voltage.

Abstract: A semiconductor device according to one embodiment includes a first normally-off type transistor including a first source, a first drain, a first gate, and a first body diode, a second normally-off type transistor including a second source connected to the first source, a second drain, a second gate connected to the first gate, and a second body diode, a normally-on type transistor including a third source connected to the first drain, a third drain, and a third gate connected to the second drain, and a diode including an anode connected to the second drain and a cathode connected to the third drain.

Abstract: The invention relates to a sensor (1) comprising a pulse generator (2) and an electrode (3) connected to an output of the pulse generator (2). A detector (61) detects a change in the amplitude of the signal being present at the electrode, and a control unit (62) operatively connected to the output of the detector (61), detects the presence of a person interacting with the sensor based on the output signal of the detector (61). Furthermore, the electrode (3) is connected to the pulse generator (2) via an inductive circuit such that the sensor can detect the presence of a user but can also be used as a touch sensor. In one embodiment, the pulse generator (2) via an inductive circuit is adapted to generate a pulse train with repetition rate equal to the resonance frequency of the inductive circuit or to an integer multiple of an octave of said resonance frequency. An automatic faucet (100) using such sensor is further described.

Abstract: A physical unclonable function (PUF) located on a supply item for an imaging device is disclosed. The PUF has a toothed rack configured to mate with a gear. During reading operations, the gear turns and translates the PUF linearly under a magnetic sensor. This configuration is inexpensive and robust. Other devices are disclosed.

Abstract: A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.

Abstract: A semiconductor device includes a setting circuit and a reset circuit. The setting circuit includes a latch circuit having first and second inverters driven by a first power voltage whose level is fixed and a first transistor which is switched between an ON state and an OFF state on the basis of a level of a second power voltage whose level varies depending on a surrounding environment, and sets data corresponding to a reference voltage to the latch circuit in response to the first transistor being switched to the ON state. The reset circuit includes an N-type second transistor connected to an output of the first inverter and an input of the second inverter. The second transistor sets data corresponding to the reference voltage to the latch circuit in response to the second voltage being equal to or lower than a predetermined voltage value.

Abstract: According to one embodiment, a level shift circuit includes a first transistor, a second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor and eighth transistor. The level shift circuit also includes a first capacitance element, a second capacitance element, third capacitance element and fourth capacitance element. The first through eighth transistors have a first conductivity type. The first through fourth transistors are included to a bi-stable multi-vibrator. The fifth through the eighth transistors are included to an active load for the differential input of the signal through the third capacitance element and the fourth capacitance element.

Abstract: A termination resistance adjustment circuit includes a replica circuit having the same characteristics as drive circuits; a current source being able to adjust the amount of a load current of the replica circuit; a voltage generation circuit to generate a plurality of reference voltages respectively corresponding to a plurality of values of the input data with the plurality of bits; a comparison circuit to compare an output voltage of the replica circuit with the reference voltages; and a control circuit to change the amount of the load current by controlling the current source, to calculate values of the output resistances of the replica circuit for each of the plurality of levels, and to adjust the number of use of the drive circuits for each bit of the input data, based on the calculated values of the output resistances for each of the plurality of levels.

Abstract: A device including an array of superconducting logic cells, where each of the superconducting logic cells is configured to receive at least one input and provide at least one output, is provided. Each of the superconducting logic cells includes at least one Josephson junction, whose state changes based on at least a biasing condition caused by a phase of a first clock or a phase of a second clock. The array of the superconducting logic cells is configured to perform at least one operation based at least on a connection arrangement of the array of the superconducting logic cells.

Abstract: A VCO generates a clock signal. A phase and frequency detector compares phases and frequencies of the clock signal generated by the VCO and an input signal. A charge pump adjusts a control voltage of the VCO based on an output of the phase and frequency detector. An identical digit detector generates a first signal by delaying a rising timing of the input signal by a first time, generates a second signal by delaying a falling timing of the input signal by a second time, detects succession of identical digits in the input signal based on the first signal and the second signal, and stops adjustment of the control voltage by the charge pump when the identical digits succeed by a predetermined number of identical digits or more.

Abstract: According to one embodiment, a quantum computation apparatus includes a plurality of quantum nonlinear oscillators, a controller, and a measuring device. Each of the quantum nonlinear oscillators implements superposition of distinguishable quantum states by bifurcating one quantum state via a quantum adiabatic change controlled by a bifurcation parameter. The quantum nonlinear oscillators couple with each other by nondissipative coupling accompanying no loss. The controller individually controls the bifurcation parameters of the quantum nonlinear oscillators. A measuring device measures outputs from the quantum nonlinear oscillators.

Abstract: The present invention provides a signal-processing circuit including an amplification module and an analog-to-digital conversion module, wherein the amplification module includes a first input terminal for receiving an input signal, a second input terminal for receiving a reference signal, and an output terminal coupled to the analog-to-digital conversion module. Furthermore, the input signal and the reference signal are amplified by the amplification module individually, and an amplified signal is output to the analog-to-digital conversion module through the output terminal, and then the amplified signal undergoes analog-to-digital conversion by the analog-to-digital conversion module. The first amplification coefficient of which the input signal is amplified by the amplification module and the second amplification coefficient of which the reference signal is amplified by the amplification module are opposite in sign.

Abstract: A transmission apparatus includes an encoder that codes a data sequence with a parity check matrix, wherein the data sequence includes a final information bit sequence and virtual information bits, and outputs the final information bit sequence and a parity sequence, as LDPC codes, and a transmitter that transmits the LDPC codes as a transmission data. A column length of the parity check matrix is longer than a total length of the final information bit sequence and the parity sequence, by a length of the virtual information bits that are set to “0” and are not transmitted. The total length of the final information bit sequence and the parity sequence has a sequence length corresponding to a length from a first column to a determined column of the parity check matrix. The encoder generates the LDPC codes by using the first column to the determined column among one or more column(s) of the parity check matrix.

Abstract: Systems and methods are disclosed for optically communicating data by, at a transmitter side, encoding a block of input bits by one or more outer encoders, and after interleaving the encoded bits, permuting the encoded bits according to a predetermined sequence or order, and further encoding the encoded bits by an inner encoder, and at a receiver side, decoding received bits with an inner decoder, and after the encoded bits are permuted, subsequently decoding by and outer decoder, and returning information bits at an outer decoder as an output. The soft-decision and hard-decision outputs from the outer BCH code help the inner LDPC decoder to have better estimation of the received bits and gain performance. The performance in higher-order modulation formats could be as large as 0.5 dB in one embodiment.

Abstract: A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.

Abstract: In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be performed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source.

Abstract: A first memory location stores circulant contents of portions A, C, E, and B of a parity check matrix H. A second memory location stores circulant column counts of the portions A, C, E, and B. A third memory location stores a dense matrix equal to (ET?1B+D)?1, where T is an identity matrix and D and T are also portions of the parity check matrix H. First and second parity information is generated in response to receiving information data. Generating the first and second parity information includes accessing the circular content of the portions A, C, E, and B of a parity check matrix H and accessing the circulant column counts of the portions A, C, E, and B.

Abstract: A heat spreader and a method for making a heat spreader are disclosed. In an embodiment the heat spreader includes an enclosure with a hollow core and a foam core located in the hollow core.

Abstract: Crest factor reduction techniques and apparatus provide good performance while reducing the impact to power consumption and implementation cost. An example method begins with identifying multiple non-overlapping and separated signal segments in a signal made up of a sequence of digital signal values, each identified segment being an interval in which at least one the digital signal values exceeds a predetermined threshold. For each identified signal segment, an overshoot vector representing the extent by which the identified signal segment exceeds the predetermined threshold is calculated. Each overshoot vector is separately filtered with a digital filter having one or more passbands corresponding to in-band portions of the signal. Each filtered overshoot vector is separately scaled, in some embodiments, and each scaled, filtered, overshoot vector is subtracted from the corresponding portion of the signal, to obtain a compensated signal having a reduced crest factor.

Abstract: Otherwise incompatible digital predistortion and uptilt can be used together, such as in a cable television or other cable communications system having a frequency-dependent signal loss at high frequencies. The predistortion can be used to compensate for a nonlinear gain compression of a power amplifier at higher frequencies. Additional uplift and equalizer circuits can be included to address deleterious distortion effects that may otherwise arise by using predistortion and uptilt together. Training and adaptation of various components are described. Fine and coarse uptilt adjustments can be provided.

Abstract: A digital pre-distortion system can inversely model a power amplifier of a system to linearize the transmitter. A complex baseband model for digital pre-distortion based on a narrowband signal assumption is unworkable for an ultra wide band Cable television application. Predistortion can use a true wide band model including real-valued basis terms, obtained from a real-valued signal. When raised to a power, both even and odd harmonics or both odd or even other non-linear terms are represented and negative frequency fold-over can be accounted for. A Hilbert transform can be applied. Compressed sensing can be used to reduce the number of basis terms in the true real wide band model to generate a sparse model. Sparse equalization can be added to improve the stability of the digital pre-distortion system.

Abstract: An RF communications device may include a circuit board having a dielectric layer and conductive traces, one of the conductive traces defining a transmission line. The RF communications device may also include an RF transmitter carried by the circuit board and coupled to the transmission line, and RF switching circuits, each RF switching circuit including a substrate having a tapered proximal end coupled to the transmission line, and a distal end extending outwardly on the convex side of the transmission line. Each RF switching circuit may include a series diode, and a shunt diode coupled to the series diode, the series diode extending from the tapered proximal end and across an interior of the substrate.

Abstract: An RF communications device may include a circuit board having a dielectric layer and conductive traces, one of the conductive traces defining a transmission line. The RF communications device may also include an RF transmitter carried by the circuit board and coupled to the transmission line, and RF switching circuits, each RF switching circuit including a substrate having a tapered proximal end coupled to the transmission line, and a distal end extending outwardly on the convex side of the transmission line. Each RF switching circuit may include a series diode, and a shunt diode coupled to the series diode, the series diode extending from the tapered proximal end and across an interior of the substrate.

Abstract: Embodiments of the present invention provide an interference cancellation apparatus and method.

Abstract: A receiver, including: a local oscillator (LO) configured to generate a signal with a frequency; a mixer coupled to the LO, the mixer configured to change a first frequency of an input signal to a second frequency based on the generated signal; a baseband filter coupled to the mixer and having a bandwidth; and a controller coupled to the local oscillator, the controller configured to adjust the frequency of the signal to shift the second frequency of the input signal to a third frequency in response to a presence of one or more intra-band jammers that fall within the bandwidth of the baseband filter so that a respective image of the one or more intra-band jammers avoids failing into a respective one of a plurality wanted signals in the input signal.

Abstract: A method, receiver and system for isolated wireless data transfer are disclosed. The receiver includes a switching mixer connected to receive a data signal and a local oscillator signal and to output a mixed differential signal, a programmable gain amplifier using an operational transconductance amplifier (OTA) and resistive feedback, the OTA connected to receive the mixed differential signal and to provide an amplified differential signal to a polyphase filter, and an analog demodulator to demodulate the output of the polyphase filter and provide digital output.

Abstract: Radio frequency (RF) front end circuitry includes primary communications circuitry and secondary communications circuitry. The primary communications circuitry is configured to provide primary RF transmit signals and receive primary RF receive signals. The secondary communications circuitry is configured to provide primary RF transmit signals during certain uplink carrier aggregation configurations to provide antenna-to-antenna isolation between primary RF transmit signals and thus reduce intermodulation between signals in problematic operating band combinations.

Abstract: A communication device includes a first processing unit that sends a first command to start an activation processing. The communication device also includes a second processing unit that receives the first command from the first processing unit. In addition, the communication device includes an interface between the first processing unit and the second processing unit. The first processing unit activates the interface at a predetermined interface level from among a plurality of interface levels. The second processing unit starts an application in accordance with the activated interface level. The first processing unit and the second processing unit exchange data by the activated application. The first processing unit and the second processing unit perform a deactivation processing of the activated interface.

Abstract: An electronic device, for example for near field communication (NFC), includes a device host including an operating system (OS), a trusted execution environment (TEE), and a near field communication (NFC) controller configured to enable communication of the electronic device with other devices. The NFC controller is coupled to the device host by a data channel for data exchange and a control channel for control information exchange, and the control channel is provided between the TEE and the NFC controller.

Abstract: Methods and systems are provided for synthesizing and displaying distributed data using Near Field Communication (NFC). A system includes a plurality of NFC-enabled mobile devices, a NFC base transmitter generating a Radio Frequency (RF) field, and a central computing device in electronic communication with the NFC base transmitter. Each NFC-enabled mobile device has a NFC payload encoding a unique user identifier that corresponds to a quantity of user data associated with a mobile application on that mobile device. The NFC base transmitter is configured to the NFC payload(s) of mobile devices being within a certain range of the RF field. The system is programmed to generate a plurality of user interface elements based on the quantities of user data, and instruct a display device to render a visual representation of each user interface element at display coordinates determined based on the quantities of user data.

Abstract: A communication arrangement may include a communication device, which may include an application processor, a mobile radio circuit, and a near-field communication (NFC) circuit configured according to an NFC technology for transmission of data and energy for operating a circuit external to the communication device. The arrangement may include a flexible carrier mounted detachably on the communication device. The carrier may include a radio circuit, an NFC circuit configured according to an NFC technology, a circuit coupled to the NFC circuit and the radio circuit, which is configured to be operated with energy which is received by means of the NFC circuit according to the NFC technology, the circuit configured for converting data coded in accordance with the NFC technology into data coded in accordance with the radio technology, or for converting data coded in accordance with the radio technology into data coded in accordance with the NFC technology.

Abstract: An information processing device includes: a communication control unit which performs short-range wireless communication with an IC tag; a base antenna; and a terminal to which an extension antenna device can be connected, the extension antenna device includes: extension antennas; and a terminal which, by being connected to the terminal to which an extension antenna device can be connected, connects the extension antennas and the information processing device to each other, and the communication control unit performs the short-range wireless communication with the IC tag via at least any of the base antenna 19 and the extension antennas.

Abstract: Various embodiments provide a contactless circuit arrangement. The contactless circuit arrangement includes at least one antenna, an antenna tuning circuit having a plurality of electrical components, and an energy supply interface which is connected to the antenna tuning circuit in an electrically conductive manner and is intended to supply electrical energy for electrically connecting or disconnecting at least one electrical component of the plurality of electrical components for adapting the antenna tuning circuit to a target frequency.