Abstract: A system includes a memory, a processor, an encoder, a head, and a decoder. The memory stores information. The processor processes information and controls operation of other components. The encoder encodes a first portion and a second portion of a servo track to form a first and second encoded values. The second code has a run length associated therewith. The first and second encoded values result in a Gray code. Each bit of the Gray code remains constant for at least a number of tracks corresponding to the run length. The head is configured to write the first and the second encoded values onto a media, and is configured to read the first and the second encoded values from the media. The decoder decodes the first encoded value and the second encoded value. The processor determines a servo track address from the decoded first value and the decoded second value.

Abstract: A control mechanism may control the height and/or position of a read/write head configured to interact with a rotating information storage surface. A computation unit may compute a detected topography from gap measurements using a dynamic filter including a model of read/write head dynamics. A sensor may detect gap measurements of a side read/write track while the read/write head is interacting with a current read/write track. A memory may store the detected topography. The control mechanism may adjust the height of the read/write head based on the detected and/or stored topography. The control mechanism may be a reactionless control mechanism configured to apply a counterforce to offset movements of the read/write head and/or a slider.

Abstract: A perpendicular magnetic recording medium includes a perpendicular magnetic layer provided above a nonmagnetic substrate, and a protection layer provided on the perpendicular magnetic layer. The perpendicular magnetic layer has an hcp structure, and includes stacked layers having a (0002) crystal plane oriented parallel to a surface of the nonmagnetic substrate. An uppermost layer amongst the stacked layers includes polycrystal grains selected from a CoCr-base alloy, a CoPt-base alloy, a CoCrPt-base alloy, and a CoPtCr-base alloy. The protection layer makes contact with the uppermost layer of the perpendicular magnetic layer, and includes a single graphene layer or a graphene stack, and an amorphous carbon layer. The single graphene layer or the graphene stack is bonded in parallel to a (0002) crystal plane of the polycrystal grains.

Abstract: Digital optical tape archival storage systems and methods are disclosed. A digital optical tape recorder may simultaneously write data and two or more guide tracks onto a digital optical tape recording medium. A digital optical taper reader may include a camera comprising an array of detectors to capture a two-dimensional image of the digital optical tape recording medium, and an image processor to extract the data from the two-dimensional image. The camera may capture the two-dimensional image of the digital optical tape recording medium without aligning individual data bits recorded on the digital optical tape recording medium to individual detectors within the camera.

Abstract: A holographic light-emitting module includes a light source module and a light shape control module. The light source module is configured to provide a signal light beam and a reference light beam, in which polarizations of the signal light beam and the reference light beam are orthogonal. The light shape control module is configured to receive the signal light beam and the reference light beam propagated from the light source module, in which the signal light beam and the reference light beam are modulated and emitted by the light shape control module The reference light beam is surrounded by the signal light beam and located at a center of the signal light beam, and the signal light beam and the reference light beam are partially overlapped.

Abstract: A reproduction system has a content reproduction section 220 that reproduces a content having a cycle; a special reproduction operation section 230 that performs special reproduction on the content by which the content is reproduced at a reproduction position different from a normal reproduction return position at a time of normal reproduction reproduced normally; a special reproduction process section 235 that makes the content reproduction section 220 perform the special reproduction based on an operation of the special reproduction operation section 230; and a return process section 250 that matches the normal reproduction return position of the content with a position corresponding to cycle timing with which the normal reproduction continues without the special reproduction when the normal reproduction returns after the special reproduction is cancelled in case that the special reproduction is performed.

Abstract: Systems and methods relating generally to determining flaws on a storage medium.

Abstract: Physiological cues, such as elevated heart or respiratory rates can be masked from video of a person before the video is sent to another party. The masking of human-perceptible and non-human-perceptible physiological cues removes information from the video that another party could use to determine the person's emotional state. For example, variations in a person's skin color that are typically imperceptible to the human eye and from which a person's heart rate can be detected, can be removed or altered so that another party viewing the video cannot determine the person's actual heart rate in an attempt to determine the person's emotional state, even if they are performing computer analysis on the video. The presence of some physiological cues can be determined by detecting that a physiological measure is above a specified physiological measure threshold.

Abstract: Systems and techniques for modifying a subsection of uploaded media are presented. An instruction component receives a media file and a media enhancement instruction that includes enhancement data and media interval data for a first segment of the media file. A processing component modifies the first segment of the media file associated with the media interval data based on the enhancement data to generate an edited first segment of the media file. A finalization component generates an edited version of the media file that includes the edited first segment of the media file and at least a second segment of the media file that is not modified based on the enhancement data.

Abstract: There are provided respective systems and methods for recording and playing back media content. The system for recording media content includes a segmenter (303) for splitting transport stream data and index data corresponding to the media content into discrete files at periodic intervals on access point boundaries. Each of the discrete files includes a respective transport segment and a respective index segment. The system also includes a segment storage device (304) for storing the discrete files.

Abstract: An information output device includes an output unit, a recognition unit and a control unit. The output unit outputs a content. The recognition unit recognizes a user. The control unit (i) determines whether the content currently being output by the output unit is suitable for the recognized user, thereby producing a determination result and (ii) changes, on the basis of the determination result, the current output content to a content having the same substance as the current output content but a different playback time from the current output content.

Abstract: A multivariant video segmentation system and method including accepting video segments that make up a video, accepting video segment variants for the video segments, and selecting a particular video segment variant to provide as a video segment at a particular sequential time order. The video segments are provided to a user at each relative sequential time order via a video player on a first webpage, user inputs associated with the video player and at least one webpage are accepted, and engagements and conversions from the user inputs are determined and stored. The engagements include at least a viewing time of the user viewing the video, and conversions include completion of a predefined task by the user that differs from the user viewing the video. The video segment path with the highest engagement or conversion value associated with information related to the user viewing the video is provided to the user.

Abstract: Methods, apparatus, and systems for time-based and geographic navigation of video content are provided. Video content and associated metadata information are recorded and encoded using a video capture and encoding module. The associated metadata information includes at least one of date and time information of the recording and geographic position information indicative of a recording location. The recorded video content and the associated metadata information are communicated to a remote storage and web server device. A graphical user interface enables the display of an interactive map showing a route and current location of the video capture and encoding module. The video content may be searched using at least one of the graphical user interface and the interactive map by the date and/or time information and the geographic position information. Selected video content can be streamed or downloaded to a select location for display or storage.

Abstract: A data storage system allows a subscriber to store data at the time the subscriber experiences the date with an indication, such as a press of a button or a voice command. The indication causes a request to obtain and store the data to be issued. For example, the subscriber can store music while listening to it, store or request movies while viewing them, or store movie soundtracks while viewing movies. The entire music file can be stored, for example, in a vehicle in which the subscriber is traveling. For some environments, such as storage in a cellular telephone, a portion of the music is stored in a format compatible for that environment, such as cellular telephone ring tone format. When the indication is received, a determination is made as to which music is required, generally by determining the time of the indication. The music heard by the listener is then downloaded for storage in accordance with the subscriber's request.

Abstract: Provided are an image processing apparatus and method for processing images. The image processing apparatus is connected to at least one camera and includes: a performance calculating unit configured to calculate a decoding performance of the at least one camera based on information about at least one of a codec, a resolution and a frame rate of image frames which are received from the at least one camera, and a filtering unit configured to filter the received image frames to select image frames for decoding, based on a result of the calculation of the decoding performance of the at least one camera.

Abstract: To provide a semiconductor device having large memory capacity and high reliability of data or a small-size semiconductor device having a small circuit area. A memory cell includes first and second data retention portions capable of storing multilevel data. A data voltage is written to the first data retention portion from a first wiring through a transistor and a second wiring, and a data voltage is written to the second data retention portion from the second wiring through a transistor and the first wiring. With the configuration, data voltages reduced by the threshold voltages of the transistors can be retained in the first and second data retention portions. The written data voltages where the threshold voltages of the transistors are canceled can be read by precharging and then discharging the first wiring.

Abstract: Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an external power supply and to provide an internal power supply to the memory device upon receipt of a command. The power up circuitry may be configured to provide the internal power supply limited to a peak current, or may be configured to provide the internal power supply not limited to a peak current. The memory device may be, for example, a synchronous dynamic random access memory (SDRAM) device or Flash memory.

Abstract: Methods and devices for providing unclonable chip identification are provided. An integrated circuit device includes: a first transistor having a first gate oxide thickness; a second transistor having a second gate oxide thickness different than the first gate oxide thickness; and a reading circuit connected to the first transistor and the second transistor, wherein the reading circuit reads a difference in threshold voltage between the first transistor and the second transistor.

Abstract: A memory circuit includes a transistor, a signal line and a plurality of information lines. The transistor includes a first electrode, a second electrode and a control electrode. The transistor is included in a memory cell. The signal line is connected to the first electrode of the transistor. The voltage on the signal line is programmable. At most one of the information lines is connected to the second electrode of the transistor via a contact. Information stored in the memory cell is coded according to the voltage programmed on the signal line and an option of which information line the contact should connect to the second electrode of the transistor.

Abstract: A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.

Abstract: A sense amplifier (SA) and a method for operating the SA are provided. The SA includes a first differential pair of transistors configured to receive a first differential input, a second differential pair of transistors configured to receive a second differential input, and a current source configured to source a current to flow through the first and second differential pairs of transistors. The method includes receiving by a first differential pair of transistors a first differential input, receiving by a second differential pair of transistors a second differential input, and flowing a current through the first and second differential pairs of transistors. A multi-bank memory is provided. The memory includes a first bank of memory cells and a second bank of memory cells sharing the disclosed SA.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs data, a data strobe signal, an external command, and a clock signal. The second semiconductor device aligns the data in synchronization with the data strobe signal to generate first and second alignment data and latches the first and second alignment data to generate first and second latch data in response to a latch signal which is generated by dividing the data strobe signal.

Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.

Abstract: A semiconductor memory apparatus includes a driving current control block configured to sense a resistance value of a dummy memory element, and generates a write driver control signal; and a write driving block configured to provide a driving voltage to a memory cell array in response to a write driver enable signal and the write driver control signal.

Abstract: A stack memory device may include a core chip and a base chip. The core chip may include a data receiver, a strobe signal generation unit, and a test register. The data receiver may be configured for receiving data outputted from the core chip through a first normal port. The strobe signal generation unit may be configured to generate a data strobe signal based on one of a normal strobe signal and a test strobe signal depending on an operation mode. The test register may store data outputted from the data receiver in response to the data strobe signal.

Abstract: An apparatus for reducing load in a memory module. In such an apparatus, there is a circuit platform with a plurality of memory chips coupled to the circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel.

Abstract: An integrated circuit (IC) device can include a plurality of banks, each including a plurality of memory cells, and separately accessible according to a received bank address value, each bank configured to enable accesses on different phases of an internal clock signal; and a plurality of channel groups, each channel group including a plurality of channels, each channel including its own data connections, address connections, and control input connections for accessing the banks, the channels of different groups accessing the memory banks on the different phases of the internal clock signal.

Abstract: A data generating device includes: a memory cell array including a plurality of memory cells; a read circuit operative to obtain a plurality of resistance value information pieces from the plurality of memory cells; and a data generator circuit operative to set a condition on the basis of the plurality of resistance value information pieces, and generating data by allocating, on the basis of the condition, the plurality of resistance value information pieces into a plurality of sets which respectively correspond to a plurality of values constituting the data. Each of the plurality of memory cells has a characteristic where, when in a variable state, a resistance value thereof reversibly changes between a plurality of variable resistance value ranges in accordance with an electric stress applied.

Abstract: Sense circuits, memory devices, and related methods are disclosed. A sense circuit includes sample and hold circuitry configured to sample and hold a second response voltage potential, a first response voltage potential, and a third response voltage potential responsive to an evaluation signal applied to a resistance variable memory cell. The sense circuit includes an amplifier operably coupled to the sample and hold circuitry. The amplifier is configured to amplify a difference between a sum of the first response voltage potential and the third response voltage potential, and twice the second response voltage potential. A memory device includes an evaluation signal generating circuit configured to provide the evaluation signal, an array of resistance variable memory cells, and the sense circuit. A method includes applying the evaluation signal to the resistance variable memory cell, sampling and holding the response voltage potentials, and discharging the sample and hold circuitry to the amplifier.

Abstract: Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2N cells/bit reduces the variation in the retention time among memory cells. Although active power increases by a factor of 2N, the refresh time increases by more than 2N as a consequence of the fact that the majority decision does better than averaging for the tail distribution of retention time. The conversion can be realized very simply from the structure of the DRAM array circuit, and it reduces the frequency of disturbance and power consumption by two orders of magnitude. On the basis of this conversion method, some embodiments provide a partial access mode to reduce power consumption dynamically when the full memory capacity is not required.

Abstract: A memory device includes a plurality of banks suitable for including a plurality of word lines, a plurality of latch units each suitable for generating a first address by inverting a predetermined bit of an address of an activated word line of a corresponding bank and latching the first address as a target address in sections other than a target refresh section, and latching an operation address as the target address once in an all-bank refresh section of the target refresh section, wherein all of the plurality of banks are refreshed in the all-bank refresh section. All the plurality of banks are refreshed in the all-bank refresh section, and an address operation unit suitable for generating the operation address by adding or subtracting an operation value to or from the target address. A word line among the plurality of word lines that is selected using the target address may be refreshed in the target refresh section.

Abstract: Various embodiments of methods and systems for temperature compensated memory refresh (“TCMR”) of a dynamic random access memory (“DRAM”) component are disclosed. Embodiments of the solution leverage a memory refresh module located within a memory subsystem to apply a refresh power supply received from a source on the SoC. Advantageously, even though the refresh power supply is received from a source on the SoC according to a certain delivery rate that may not be optimal for each and every bank in the DRAM component, embodiments of the solution are able to apply an effective refresh power supply rate to each bank according to its optimal cycle.

Abstract: A method is disclosed for selecting a semiconductor chip in a stack of semiconductor chips interconnected by through-lines by receiving selection signals at the first terminals located on a first surface of the semiconductor chip, connecting each first terminal to a selected second terminal located on a second surface of the semiconductor chip where each selected second terminal is not aligned with the first terminal to which it is connected, and generating an internal signal based on a selected one of the received selection signals.

Abstract: A method and apparatus for pre-calibration of various system performance states is disclosed. In one embodiment, a method includes, for each of a number of different performance states (or operating points), performing initial calibrations of various parameters associated with transfers of data between a memory and a memory controller. After completing the initial calibrations, the calibrated values are stored. Thereafter, during normal operation and following a change to a new performance state, the values of the various parameters are set to the values to which they were calibrated during the initial calibration for that state.

Abstract: A semiconductor memory device includes a plurality of memory cell blocks each including a plurality of word lines and suitable for being selectively activated based on an active command and a row address, wherein word lines are selected from the respective activated memory cell blocks based on the active command and the row address, and a column decoding block sequentially accessing the activated memory cell blocks to input/output data thereof by decoding a column address based on the row address.

Abstract: A tracking circuit for a memory includes a tracking cell. A tracking word line is connected to the tracking cell. A tracking bit line is connected to the tracking cell. A voltage generator is configured to provide a variable tracking cell power supply voltage to the tracking cell based on a control signal.

Abstract: One feature pertains to a true random number generator that utilizes the settling time of a bit cell as an entropy source to generate random digital output values. The bit cell may be a static random access memory bit cell. The bit cell's settling time may be converted into a digital output using an analog to digital converter. A plurality of bit cells may serially couple to one another in a ring formation. The bit cell ring can then be enabled such that each bit cell of the plurality of bit cells achieves a settling value that activates the subsequent bit cell in the ring causing it to in turn reach a settling value, and so on. An output node of one of the bit cells in the ring can then be sampled using a flip-flop to generate a continuous stream of random bits.

Abstract: A write-assist memory includes a memory supply voltage and a column of SRAM cells that is controlled by a pair of bit lines, during a write operation. Additionally, the write-assist memory includes a write-assist unit that is coupled to the memory supply voltage and the column of SRAM cells and has a separable conductive line located between the pair of bit lines that provides a collapsible SRAM supply voltage to the column of SRAM cells based on a capacitive coupling of a control signal in the pair of bit lines, during the write operation. A method of operating a write-assist memory is also provided.

Abstract: Systems and methods relate to memory operations in a memory array. A compare operation is performed using a sense amplifier. True and complement versions of a search bit are compared with true and complement versions of a data bit stored in a data row of the memory array to generate true and complement sense amplifier inputs. The true and complement sense amplifier inputs are amplified in the sense amplifier to generate a single-ended match signal. The single-ended match signal can be aggregated with other single-ended match signals in the data row to determine whether there is a hit or miss for a compare operation on the entire data row.

Abstract: A circuit includes: a first word line; a second word line; and a memory cell. The memory cell includes: a first pass gate, between a transistor and a first data line (RBL), having a gate coupled to the first word line; the transistor having a drain coupled to the first pass gate, a source coupled to a reference node, and a gate coupled to a data node of the memory cell; and a second pass gate, between the data node and a second data line, having a gate coupled to the second word line. The first word line is configured to turn on the first pass gate. The second word line is configured to turn on the second pass gate after an elapse of a first delay.

Abstract: Method of operating flash memory unit is provided. Flash memory unit includes first and second split-gate flash memory units, source and drain of first split-gate flash memory unit are connected with first and third bit lines respectively, source and drain of second split-gate flash memory unit is connected with second and third bit line respectively, first control gates of two split-gate flash memory units are connected with first control gate line, second control gates of two split-gate flash memory units are connected with second control gate line, word line gates of two split-gate flash memory units are connected with word line, method includes configuring voltages to first and third bit lines, word line, first and second control gate lines to select first storage bit in first split-gate flash memory unit and make first storage bit in to-be-read or to-be-programmed state; suspending second bit line; reading or programming first storage bit.

Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.

Abstract: Memories and methods of operating memories having memory cells sharing a resistance variable material.

Abstract: To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.

Abstract: An integrated circuit (IC) device includes a static random access memory (SRAM) array, and a resistive memory (resistive memory) array. A first set of programmable resistive elements in the resistive memory array are used to store data from memory cells in the SRAM array. Sense amplifier circuitry is couplable to the SRAM array and the resistive memory array. An arbiter is configured to assert an resistive memory enable signal to couple the sense amplifier circuitry to the resistive memory array and decouple the sense amplifier circuitry from the SRAM array during a resistive memory read operation, and to couple the sense amplifier to the SRAM array and decouple the sense amplifier circuitry from the resistive memory array during an SRAM read operation.

Abstract: A memory array including: a first volatile memory cell including first and second cross-coupled inverters between first and second storage nodes; a first non-volatile memory cell including at least one resistive element that can be programmed to take one of at least two resistive states; and a control circuit adapted to couple the first non-volatile memory cell to the first and second storage nodes in order to generate a current for programming the resistive state of the at least one resistive element.

Abstract: A ternary content addressable memory (TCAM) cell is coupled to a first word line and a first match line and includes a first data storage portion coupled to a first search line, a second data storage portion coupled to a complement of the first search line, and a resistor divider portion including two resistive elements coupled in series with the first and second data storage portions of the first TCAM cell. The first and second data storage portions of the first TCAM cell are coupled to a first supply voltage and include two resistive elements coupled in parallel.

Abstract: A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

Abstract: A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.