Patents Issued in May 2, 2017
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Patent number: 9640362Abstract: Provided is an X-ray tube including an anode, a target on the anode, a cathode disposed separate from the target and the anode and comprising an emitter providing an electron beam to the target, and a side wall disposed between the cathode and the anode, and surrounding the target and the emitter. The side wall reflects a light generated by collision of the electron beam with the target to the cathode, and electrically insulates the cathode from the anode.Type: GrantFiled: January 26, 2015Date of Patent: May 2, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jun Tae Kang, Yoon-Ho Song
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Patent number: 9640363Abstract: A nano-patterned system comprises a vacuum chamber, a sample stage and a magnetic-field applying device, which comprises a power supply, a magnetic-field generation device and a pair of magnetic poles. The magnetic-field generation device comprises a coil and a magnetic conductive soft iron core. The power supply is connected to the coil, which is wound on the soft iron core to generate a magnetic field. The soft iron core is of a semi-closed frame structure and the magnetic poles are at the ends of the frame structure. The stage is inside a vacuum chamber. The poles are oppositely arranged inside the vacuum chamber relative to the stage. The coil and the soft iron core are outside the vacuum chamber. The soft iron core leads the magnetic field generated by the coil into the vacuum chamber. The magnetic poles locate a sample on the stage and apply a local magnetic field.Type: GrantFiled: September 30, 2016Date of Patent: May 2, 2017Assignee: Institute Of Physics, Chinese Academy Of SciencesInventors: Guoqiang Yu, Peng Guo, Xiufeng Han, Chaohui Guo, Xiaoyu Sun, Xiangqian Zhou
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Patent number: 9640364Abstract: The present disclosure relates to a gas field ion source comprising a housing, an electrically conductive tip arranged within the housing, a gas supply for supplying one or more gases to the housing, wherein the one or more gases comprise neon or a noble gas with atoms having a mass larger than neon, and an extractor electrode having a hole to permit ions generated in the neighborhood of the tip to pass through the hole. A surface of the extractor electrode facing the tip can be made of a material having a negative secondary ion sputter rate of less than 10?5 per incident neon ion.Type: GrantFiled: December 15, 2015Date of Patent: May 2, 2017Assignee: Carl Zeiss Microscopy, LLCInventors: John A. Notte, IV, FHM-Faridur Rahman, Weijie Huang, Shawn McVey
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Method for determining 3D primitive reciprocal basis of unknown crystal based on single EBSD pattern
Patent number: 9640365Abstract: A method for determining 3D primitive reciprocal basis of an unknown crystal based on a single EBSD pattern includes steps of geometrically correcting all visible Kikuchi bands with the pattern center and the detector distance used for obtaining corresponding reciprocal vectors, and determining components of the corresponding reciprocal vectors in a 3D reciprocal Cartesian coordinate system, so as to obtain a 3D primitive reciprocal basis. The method given in the present invention is able to effectively exclude fake primitive cells; correctly identify the volume of a primitive cell even though the presence of obvious errors in the width of the Kikuchi bands; and successfully determine a 3D primitive reciprocal basis of unknown crystals based on a single EBSD pattern.Type: GrantFiled: January 13, 2016Date of Patent: May 2, 2017Assignee: East China Jiaotong UniversityInventors: Ming Han, Lili Li, Guangyao Xiong, Honglin Luo, Yizao Wan -
Patent number: 9640366Abstract: The present invention has for its object to provide a charged particle beam irradiation method and a charged particle beam apparatus which can suppress unevenness of electrification even when a plurality of different kinds of materials are contained in a pre-dosing area or degrees of density of patterns inside the pre-dosing area differs with positions. To accomplish the above object, a charged particle beam irradiation method and a charged particle beam apparatus are provided according to which the pre-dosing area is divided into a plurality of divisional areas and electrifications are deposited to the plural divisional areas by using a beam under different beam irradiation conditions.Type: GrantFiled: February 9, 2011Date of Patent: May 2, 2017Assignee: Hitachi High-Technologies CorporationInventors: Toshiyuki Yokosuka, Minoru Yamazaki, Hideyuki Kazumi, Kazutami Tago
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Patent number: 9640367Abstract: The present invention provides an inductively coupled, magnetically enhanced ion beam source, suitable to be used in conjunction with probe-forming optics to produce an ion beam without kinetic energy oscillations induced by the source.Type: GrantFiled: September 9, 2014Date of Patent: May 2, 2017Assignee: FEI CompanyInventors: John Keller, Noel Smith, Roderick Boswell, Lawrence Scipioni, Christine Charles, Orson Sutherland
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Patent number: 9640368Abstract: In a plasma processing apparatus, first to third RF power monitors 94, 94 and 98 are configured to monitor high frequency powers (progressive wave powers), which propagate on first to third high frequency power supply lines 88, 90 and 92 from first to third high frequency power supplies 36, 38 and 40 toward a load side, respectively, and high frequency powers (reflection wave powers), which propagate on the first high frequency power supply lines 88, 90 and 92 from the load side toward the first to third high frequency power supplies 36, 38 and 40, respectively, at the same time. A main controller 82 is configured to control the high frequency power supplies 36, 38 and 40 and matching devices 42, 44 and 46 based on monitoring information sent from RF power monitors 94, 96 and 98.Type: GrantFiled: December 13, 2012Date of Patent: May 2, 2017Assignees: TOKYO ELECTRON LIMITED, DAIHEN CORPORATIONInventors: Naoyuki Umehara, Ryuji Ohtani, Shunichi Ito, Kazutaka Sei, Tomomasa Nishida
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Patent number: 9640369Abstract: A plasma generation process that is more optimized for vapor deposition processes in general, and particularly for directed vapor deposition processing. The features of such an approach enables a robust and reliable coaxial plasma capability in which the plasma jet is coaxial with the vapor plume, rather than the orthogonal configuration creating the previous disadvantages. In this way, the previous deformation of the vapor gas jet by the work gas stream of the hollow cathode pipe can be avoided and the carrier gas consumption needed for shaping the vapor plume can be significantly decreased.Type: GrantFiled: February 24, 2010Date of Patent: May 2, 2017Assignee: University of Virginia Patent FoundationInventors: Haydn N. G. Wadley, Goesta Mattausch, Henry Morgner, Frank-Holm Roegner
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Patent number: 9640370Abstract: A method is for etching the whole width of a substrate to expose buried features. The method includes etching a face of a substrate across its width to achieve substantially uniform removal of material; illuminating the etched face during the etch process; applying edge detection techniques to light reflected or scattered from the face to detect the appearances of buried features; and modifying the etch in response to the detection of the buried feature. An etching apparatus for etching substrate across its width to expose buried is also disclosed.Type: GrantFiled: March 4, 2014Date of Patent: May 2, 2017Assignee: SPTS Technologies LimitedInventor: Oliver James Ansell
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Patent number: 9640371Abstract: A system and method of identifying a selected process point in a multi-mode pulsing process includes applying a multi-mode pulsing process to a selected wafer in a plasma process chamber, the multi-mode pulsing process including multiple cycles, each one of the cycles including at least one of multiple, different phases. At least one process output variable is collected for a selected at least one of the phases, during multiple cycles for the selected wafer. An envelope and/or a template of the collected at least one process output variable can be used to identify the selected process point. A first trajectory for the collected process output variable of a previous phase can be compared to a second trajectory of the process output variable of the selected phase. A multivariate analysis statistic of the second trajectory can be calculated and used to identify the selected process point.Type: GrantFiled: October 24, 2014Date of Patent: May 2, 2017Assignee: Lam Research CorporationInventors: Yassine Kabouzi, Jorge Luque, Andrew D. Bailey, III, Mehmet Derya Tetiker, Ramkumar Subramanian, Yoko Yamaguchi
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Patent number: 9640372Abstract: A method for extracting a shielding element from a processing chamber of a substrate processing system or inserting the shielding element into the processing chamber is provided. The substrate processing system includes the processing chamber, a first shielding element for excluding application of material onto parts of a substrate, and a substrate transportation system for transporting substrates or substrate carriers into and out of the processing chamber. The method includes transporting the first shielding element by the substrate transportation system.Type: GrantFiled: November 15, 2012Date of Patent: May 2, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Ralph Lindenberg, Erkan Koparal
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Patent number: 9640373Abstract: Data of a plurality of samples collected by an LC/MS, GC/MS or other systems are converted into a two-dimensional table format. After LC/MS measurement data on a plurality of samples are obtained and the respective extracted ion chromatograms (XICs) are created, a time-axis adjustment for correcting a discrepancy in the retention time is performed, followed by a process of correcting the missing of data which has occurred in the head and/or tail section of the data as a result of the time-axis adjustment.Type: GrantFiled: June 29, 2011Date of Patent: May 2, 2017Assignee: SHIMADZU CORPORATIONInventor: Shinichi Yamaguchi
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Patent number: 9640374Abstract: A new algorithm is taught for identifying compounds from spectroscopic or mass spectra data, wherein the improved order of operations of the present invention are defined as 1) background noise removal, 2) deconvolution by smoothing peaks, finding peaks and grouping peaks into unknown compounds, 3) preparing correlation values for combinations of unknown compound and target compound pairs, 4) sorting the combinations of unknown compound and target compound pairs by their correlation values, 5) removing complete ions from the mass spectra data using a peak, a retention time, and a retention window, and 6) matching unknown compounds to target compounds such that no target compound appears twice.Type: GrantFiled: March 11, 2013Date of Patent: May 2, 2017Assignee: TORION TECHNOLOGIES, INC.Inventors: Joseph L. Oliphant, Chad B. Grant, H. Dennis Tolley
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Patent number: 9640375Abstract: The present invention provides a method for determining low mass ions for diagnosing colorectal cancer by using a MALDI-TOF mass spectrometer to biostatistically analyze low mass ions, which are extracted from a biological sample, and a method for providing information for diagnosing colorectal cancer using same. The present inventions can provide a diagnostic method, which requires low cost and a short time for analysis, can analyze large areas, and which can provide superior and credible discriminations.Type: GrantFiled: August 12, 2011Date of Patent: May 2, 2017Assignee: National Cancer CenterInventors: Byong Chul Yoo, In Hoo Kim, Kyung Hee Kim, Jun Hwa Lee, Kwang Gi Kim, Hee Jin Chang, Dae Yong Kim, Jae Hwan Oh, Byung Chang Kim, Ji Won Park, Sun Young Kim
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Patent number: 9640376Abstract: This invention relates to graphical user-interactive displays for use in MS-based analysis of protein impurities, as well as methods and software for generating and using such. One aspect provides a user-interactive display comprising an extracted mass chromatogram (XIC), an MS1 spectrum and an MS2 spectrum, all simultaneously representing a user-selected peptide. Another aspect provides a user interactive display simultaneously presenting paired spectra (XIC, MS1 and/or MS2) for a variant peptide and its corresponding wildtype counterpart.Type: GrantFiled: June 16, 2014Date of Patent: May 2, 2017Assignee: Protein Metrics Inc.Inventors: Christopher Becker, Marshall Bern, Yong Joo Kil, Michael Taejong Kim, Boyan Zhang
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Patent number: 9640377Abstract: This invention is related to a tandem mass spectrometric analysis method in ion trap mass analyzer. Such method comprise three stages as represented by selective isolation, collision induced disassociation and mass scanning of ion. At the collision induced isolation stage, this invention is expected to endow parent ion of certain mass-charge ratio with energy through resonance excitation by changing cycle of radio frequency signals, namely frequency of radio frequency voltage imposed on the ion trap; such high-energy ions produced through resonance excitation are to be disassociated through collision with neutral molecules in the ion trap, which will further generate product ion to realize tandem mass spectrometric analysis.Type: GrantFiled: July 4, 2014Date of Patent: May 2, 2017Assignee: Fudan UniversityInventors: Fuxing Xu, Liang Wang, Chuanfan Ding
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Patent number: 9640378Abstract: An embodiment of the invention relates to a TOF-MS capable of performing mass spectrometry of a sample at a high throughput. The TOF-MS has an acceleration part for accelerating an ion, a detector for detecting an event of arrival of the accelerated ion, and a data processing part for performing mass spectrometry of the sample, based on a time of flight of the ion. A first structure of the detector includes an MCP, a dynode, and an anode. In the first structure, the dynode is set at a potential higher than that of an output face of the MCP. The anode is disposed at an intermediate position between the MCP and the dynode or on the dynode side with respect to the intermediate position. The anode has plural apertures and is set at a potential higher than that of the dynode.Type: GrantFiled: January 20, 2016Date of Patent: May 2, 2017Assignee: HAMAMATSU PHOTONICS K.K.Inventor: Masahiro Hayashi
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Patent number: 9640379Abstract: A mass spectrometer vacuum interface can include a skimmer apparatus having a skimmer aperture and an internal surface. A method of operating the mass spectrometer vacuum interface can include establishing an outwardly directed flow along the internal surface of the skimmer apparatus.Type: GrantFiled: April 20, 2015Date of Patent: May 2, 2017Assignee: Thermo Fisher Scientific (Bremen) GmbHInventors: Alexander Alekseevich Makarov, Lothar Rottmann
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Patent number: 9640380Abstract: Electrodeless high intensity discharge (HID) lamps have the promise of higher reliability and higher efficiency than traditional electroded high intensity discharge lamps. However, most electrodeless HIDs operate in the frequency range of around 400 MHz or higher resulting in expensive, inefficient RF drivers that reduce the overall efficacy of the lamp. Operating the lamp at lower frequencies results in substantial increase in the physical dimensions of the resonators used in traditional electrodeless HIDs. In this invention a novel wave-launcher technology is used allow the lamp housing's operating frequency to be independent of the physical dimensions of the lamp housing. This provides an avenue to increase the conversion efficiency of the RF driver and the efficacy of the lamp system.Type: GrantFiled: September 20, 2016Date of Patent: May 2, 2017Assignee: SPL INDUSTRIES USA, INC.Inventors: Timothy J. Brockett, Gregg A. Hollingsworth, Mehran Matloubian
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Patent number: 9640381Abstract: Internal components of plasma reactors are composed of a toleratable, ceramic filled plasma-useful polymer such as a high temperature engineering thermoplastic, preferably a polyamideimide or polybenzimidazole. The parts exhibit a low erosion rate upon exposure to plasma at low pressure.Type: GrantFiled: April 10, 2012Date of Patent: May 2, 2017Assignee: QUADRANT EPP AGInventors: Scott Howard Williams, Richard William Campbell, Stephan Glander
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Patent number: 9640382Abstract: In a substrate processing apparatus, with an internal space of a chamber brought into a reduced pressure atmosphere, a first processing liquid is supplied onto an upper surface of a substrate while the substrate is rotated, and the first processing liquid is thereby quickly spread from a center portion toward a peripheral portion on the upper surface of the substrate. It is thereby possible to coat the upper surface of the substrate with the first processing liquid in a shorter time as compared with under normal pressure. Further, by sucking the first processing liquid from the vicinity of an edge of the substrate, it is possible to coat the upper surface of the substrate with the first processing liquid in a still shorter time. As a result, it is possible to shorten the time required for the processing of the substrate.Type: GrantFiled: September 15, 2015Date of Patent: May 2, 2017Assignee: SCREEN HOLDINGS CO., LTD.Inventors: Hirofumi Masuhara, Kenichiro Arai, Masahiro Miyagi, Toru Endo
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Patent number: 9640383Abstract: A liquid treatment apparatus includes a substrate holding member that holds a substrate horizontally, a rotation mechanism that rotates the substrate holding member; a chemical liquid nozzle that supplies a chemical liquid to the substrate held by the substrate holding member; a top plate that covers the substrate held by the substrate holding member from above the substrate; and at least one LED lamp that heats the substrate during a chemical liquid treatment by irradiating the substrate with light of a predetermined wavelength through the top plate from above the top plate.Type: GrantFiled: July 11, 2012Date of Patent: May 2, 2017Assignee: Tokyo Electron LimitedInventors: Kazuhiro Aiura, Norihiro Ito, Takashi Nagai
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Patent number: 9640384Abstract: A substrate cleaning apparatus includes: a substrate holder configured to hold and rotate a substrate; an ultrasonic cleaning unit configured to impart an ultrasonic vibration energy to deaerated pure water and then supply the deaerated pure water onto a surface of the substrate; a pure water spray nozzle configured to spray deaerated pure water onto the surface of the substrate; a chamber surrounding the substrate holder and the pure water spray nozzle; and an inert gas supply line configured to supply an inert gas into the chamber.Type: GrantFiled: December 23, 2013Date of Patent: May 2, 2017Assignee: Ebara CorporationInventor: Tomoatsu Ishibashi
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Patent number: 9640385Abstract: The present disclosure provides methods for removing gate electrode residuals from a gate structure after a gate electrode patterning process. In one example, a method for forming high aspect ratio features in a gate electrode layer in a gate structure includes performing an surface treatment process on gate electrode residuals remaining on a gate structure disposed on a substrate, selectively forming a treated residual in the gate structure on the substrate with some untreated regions nearby in the gate structure, and performing a remote plasma residual removal process to remove the treated residual from the substrate.Type: GrantFiled: January 19, 2016Date of Patent: May 2, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Bhargav Citla, Chentsau Ying, Srinivas D. Nemani
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Patent number: 9640386Abstract: Classes of liquid aminosilanes have been found which allow for the production of silicon carbo-nitride films of the general formula SixCyNz. These aminosilanes, in contrast, to some of the precursors employed heretofore, are liquid at room temperature and pressure allowing for convenient handling. In addition, the invention relates to a process for producing such films. The classes of compounds are generally represented by the formulas: and mixtures thereof, wherein R and R1 in the formulas represent aliphatic groups typically having from 2 to about 10 carbon atoms, e.g., alkyl, cycloalkyl with R and R1 in formula A also being combinable into a cyclic group, and R2 representing a single bond, (CH2)n, a ring, or SiH2.Type: GrantFiled: December 16, 2014Date of Patent: May 2, 2017Assignee: VERSUM MATERIALS US, LLCInventors: Manchao Xiao, Arthur Kenneth Hochberg
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Patent number: 9640387Abstract: A technique includes loading a substrate into a process chamber, supporting the substrate by a mounting table having a heater therein in the process chamber, forming a film on the substrate by supplying a processing gas into the process chamber in a state where the mounting table having the substrate supported thereon is disposed in a first position and the heater is turned on, unloading the substrate on which the film is formed, and supplying a reactive gas into the process chamber in a state where the mounting table is disposed in a second position and the heater is turned on. The second position is closer to a ceiling portion in the process chamber than the first position.Type: GrantFiled: August 28, 2015Date of Patent: May 2, 2017Assignee: HITACHI KOKUSAI ELECTRIC INC.Inventors: Ryuji Yamamoto, Tsukasa Kamakura, Yoshiro Hirose, Satoshi Shimamoto
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Patent number: 9640388Abstract: In a method for forming a fluorocarbon-based insulating film to be in contact with a metal, a microwave is irradiated to the metal to which moisture is adhered in a hydrogen-containing atmosphere. Then plasma CVD using a fluorocarbon-based gas is performed on the metal to which the microwave is irradiated to form the insulating film.Type: GrantFiled: February 12, 2016Date of Patent: May 2, 2017Assignee: TOKYO ELECTRON LIMITEDInventors: Shigeru Kasai, Kotaro Miyatani, Takuya Kurotori, Kenichi Kote, Yutaka Fujino, Akira Tanihara, Kohei Kawamura
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Patent number: 9640389Abstract: A layer structure and method of fabrication of a semiconductor heterostructure containing a two-dimensional electron gas (2DEG), two-dimensional hole gas (2DHG), or a two-dimensional electron/hole gas (2DEHG). The heterostructure contains a quantum well layer with 2DEG, 2DHG, or 2DEHG embedded between two doped charge reservoir layers and at least two remote charge reservoir layers. Such scheme allows reducing the number of scattering ions in the proximity of the quantum well as well a possibility for a symmetric potential for the electron or hole wavefunction in the quantum well, leading to significant improvement in carrier mobility in a broad range of 2DEG or 2DHG concentration in the quantum well. Embodiments of the invention may be applied to the fabrication of galvano-magnetic sensors, HEMT, pHEMT, and MESFET devices.Type: GrantFiled: June 17, 2015Date of Patent: May 2, 2017Assignee: BROLIS SEMICONDUCTORS LTD.Inventors: Augustinas Vizbaras, Kristijonas Vizbaras
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Patent number: 9640390Abstract: Doped semiconductor ink formulations, methods of making doped semiconductor ink formulations, methods of coating or printing thin films, methods of forming electronic devices and/or structures from the thin films, and methods for modifying and controlling the threshold voltage of a thin film transistor using the films are disclosed. A desired dopant may be added to an ink formulation comprising a Group IVA compound and a solvent, and then the ink may be printed on a substrate to form thin films and conductive structures/devices, such as thin film transistors. By adding a customized amount of the dopant to the ink prior to printing, the threshold voltage of a thin film transistor made from the doped semiconductor ink may be independently controlled upon activation of the dopant.Type: GrantFiled: May 7, 2013Date of Patent: May 2, 2017Assignee: Thin Film Electronics ASAInventors: Wenzhuo Guo, Fabio Zurcher, Arvind Kamath, Joerg Rockenberger
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Patent number: 9640391Abstract: A method for growing a transition metal dichalcogenide on a substrate, the method including providing a growth substrate having a first side and a second side opposite the first side; providing a source substrate having a first side and a second side opposite the first side; depositing a transition metal oxide on at least a portion of the first side of the source substrate; combining the growth substrate with the source substrate such that the first side of the growth substrate contacts the transition metal oxide, the combining producing a substrate stack; exposing the substrate stack to a chalcogenide gas, whereby the transition metal oxide reacts with the chalcogenide gas to produce a layer of a transition metal dichalcogenide on at least a portion of the first side of the growth substrate; and removing the source substrate from the growth substrate having the layer of the transition metal dichalcogenide thereon.Type: GrantFiled: June 23, 2016Date of Patent: May 2, 2017Assignee: THE TRUSTEES OF THE STEVENS INSTITUTE OF TECHNOLOGYInventors: Eui-Hyeok Yang, Kyung Nam Kang
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Patent number: 9640393Abstract: The present invention relates to a substrate with a crystallized silicon film and manufacturing method thereof, wherein the substrate with the crystallized silicon film comprises: a substrate, which is a polymer substrate; and a crystallized silicon film, which is formed on at least one surface of the substrate, wherein the crystallized silicon film comprises a plurality of silicon crystals with column structures, and the crystallinity of the crystallized silicon film is higher than 90%.Type: GrantFiled: August 3, 2016Date of Patent: May 2, 2017Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Nyan-Hwa Tai, Chi-Young Lee, Ping-Yen Hsieh
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Patent number: 9640394Abstract: Method for fabricating a semiconductor structure. The method includes: providing a crystalline silicon substrate; defining an opening in a dielectric layer on the crystalline silicon substrate, the opening having sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; providing a confinement structure above the dielectric layer, thereby forming a confinement region between the confinement structure and the dielectric layer; and growing a crystalline compound semiconductor material in the confinement region thereby at least partially filling the confinement region. The present invention also provides an improved compound semiconductor structure and a device for fabricating such semiconductor structure.Type: GrantFiled: August 26, 2015Date of Patent: May 2, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniele Caimi, Lukas Czornomaz, Jean Fompeyrine, Emanuele Uccelli
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Patent number: 9640395Abstract: A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.Type: GrantFiled: May 10, 2016Date of Patent: May 2, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Zhiyuan Cheng
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Patent number: 9640396Abstract: Novel double- and triple-patterning methods are provided. The methods involve applying a shrinkable composition to a patterned template structure (e.g., a structure having lines) and heating the composition. The shrinkable composition is selected to possess properties that will cause it to shrink during heating, thus forming a conformal layer over the patterned template structure. The layer is then etched to leave behind pre-spacer structures, which comprise the features from the pattern with remnants of the shrinkable composition adjacent the feature sidewalls. The features are removed, leaving behind a doubled pattern. In an alternative embodiment, an extra etch step can be carried out prior to formation of the features on the template structure, thus allowing the pattern to be tripled rather than doubled.Type: GrantFiled: January 5, 2010Date of Patent: May 2, 2017Assignee: Brewer Science Inc.Inventors: Qin Lin, Rama Puligadda, James Claypool, Douglas J. Guerrero, Brian Smith
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Patent number: 9640397Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first layer is deposited over a substrate. A plurality of mandrels is formed over the first layer. Guiding-spacers are formed along sidewalls of the mandrels. Then the mandrels are removed. A neutral layer (NL) and a block copolymer (BCP) layer are deposited over the first layer and the guiding-spacers. A anneal is applied to the BCP layer to form a first polymer nanostructure between the guiding-spacers and being surrounded by a second polymer nanostructure. The first polymer nanostructures locate at a same distance from the first layer. Polymer nano-blocks are formed by selectively etching the second polymer nanostructure and the NL. By using the polymer nano-blocks and the guiding spacer as etch masks, the first layer is etched to form openings. The substrate is etched through the openings to form substrate trench and substrate fin.Type: GrantFiled: March 14, 2014Date of Patent: May 2, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chieh-Han Wu, Chung-Ju Lee, Tien-I Bao, Tsung-Yu Chen, Shinn-Sheng Yu, Yu-Fu Lin, Jeng-Horng Chen
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Patent number: 9640398Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.Type: GrantFiled: May 14, 2015Date of Patent: May 2, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
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Patent number: 9640399Abstract: A method of forming patterns includes forming a guide pattern and first peripheral patterns on an underlying layer. The guide pattern provides first openings and the first peripheral patterns provide a fifth opening used in alignment of the guide pattern. An alignment status of the guide pattern is verified using the fifth opening. A block copolymer layer is formed to fill the first and fifth openings. The block copolymer layer is annealed to provide a blocking portion sealing the fifth opening and to form first domains in each first opening and a second domain surrounding the first domains formed in each first opening. The first domains are removed to form third openings. The underlying layer is etched using the blocking portion and sidewalls of the second domains as etch barriers to form fourth openings that extend from the third openings to penetrate the underlying layer.Type: GrantFiled: August 11, 2015Date of Patent: May 2, 2017Assignee: SK Hynix Inc.Inventors: Jung Gun Heo, Hong Ik Kim, Keun Do Ban, Cheol Kyu Bok
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Patent number: 9640400Abstract: Embodiments described herein generally relate to doping of three dimensional (3D) structures on a substrate. In one embodiment, a conformal dopant containing film may be deposited over the 3D structures. Suitable dopants that may be incorporated in the film may include boron, phosphorous, and other suitable dopants. The film may be subsequently annealed to diffuse the dopants into the 3D structures.Type: GrantFiled: December 8, 2015Date of Patent: May 2, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Rui Cheng, Abhijit Basu Mallick, Srinivas Gandikota, Pramit Manna
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Patent number: 9640401Abstract: A method of manufacturing a semiconductor device includes forming a cavity in a first semiconductor layer formed on a semiconducting base layer, the cavity extending from a process surface of the first semiconductor layer at least down to the base layer, forming a recessed mask liner on a portion of a sidewall of the cavity distant to the process surface or a mask plug in a portion of the cavity distant to the process surface, and growing a second semiconductor layer on the process surface by epitaxy, the second semiconductor layer spanning the cavity.Type: GrantFiled: June 21, 2016Date of Patent: May 2, 2017Assignee: Infineon Technologies AGInventors: Johannes Georg Laven, Hans-Joachim Schulze, Anton Mauder, Erich Griebl
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Patent number: 9640402Abstract: Methods for forming a gate structure of a circuit structure are provide. The methods for forming the gate structure may include: forming a first gate pattern in a gate mask layer, the forming including a first etching of rounded corner portions of the first gate pattern; forming a second gate pattern in the gate mask layer, the second gate pattern at least partially overlapping the first gate pattern, the forming including a second etching of rounded corner portions of the second gate pattern; and, etching the gate mask layer using the first gate pattern and second gate pattern to form the gate structure.Type: GrantFiled: February 22, 2016Date of Patent: May 2, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Xintuo Dai, Jiong Li
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Patent number: 9640403Abstract: A low electric field source erasable non-volatile memory unit includes a substrate having a source diffusion region and a drain diffusion region. The source diffusion region includes a heavily-doped region and a lightly-doped region extending. A first dielectric layer and a tunnel dielectric layer are formed on the substrate. The tunnel dielectric layer includes a lower face contiguous to or partially overlapped with the lightly-doped region of the source diffusion region. A select gate and a floating gate are respectively formed on the first dielectric layer and the tunnel dielectric layer. The floating gate includes a source side edge contiguous to or partially overlapped with the lightly-doped region and misaligned from the heavily-doped region by a distance. A second dielectric layer and a control gate are formed on the floating gate. The control gate and the floating gate are insulating to each other by the second dielectric layer.Type: GrantFiled: January 16, 2015Date of Patent: May 2, 2017Assignee: Xinnova Technology Ltd.Inventors: Der-Tsyr Fan, Chih-Ming Chen, Jung-Chang Lu
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Patent number: 9640404Abstract: In a method of forming a tungsten film, an initial tungsten film and a main tungsten film are formed on an underlying film of a substrate. The initial tungsten film is formed on the underlying film by sequentially supplying a tungsten chloride gas and a reduction gas into a chamber while supplying a purging gas between the supplies of the tungsten chloride gas and the reduction gas, or by simultaneously supplying the tungsten chloride gas and the reduction gas. The main tungsten film is formed on the initial tungsten film by sequentially supplying the tungsten chloride gas and the reduction gas into the chamber while purging an inside of the chamber between the supplies of the tungsten chloride gas and the reduction gas. A supply amount of the tungsten chloride gas in forming the initial film is smaller than that in forming the main tungsten film.Type: GrantFiled: March 24, 2016Date of Patent: May 2, 2017Assignee: TOKYO ELECTRON LIMITEDInventors: Kenji Suzuki, Koji Maekawa, Takanobu Hotta
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Patent number: 9640405Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.Type: GrantFiled: December 29, 2015Date of Patent: May 2, 2017Assignee: XINTEC INC.Inventors: Ying-Nan Wen, Chien-Hung Liu, Shih-Yi Lee, Ho-Yin Yiu
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Patent number: 9640407Abstract: A polishing composition of the present invention contains a water-soluble polymer having a hydrophilic group, and abrasive grains. A hydrophobic silicon-containing part after being polished with the polishing composition has a water contact angle lower than that of the hydrophobic silicon-containing part after being polished with another composition having the same makeup as the polishing composition except that the water-soluble polymer is not contained therein. Examples of the water-soluble polymer include polysaccharides and alcohol compounds. Another polishing composition of the present invention contains abrasive grains having a silanol group, and a water-soluble polymer. When this polishing composition is left to stand for one day in an environment at a temperature of 25° C., the water-soluble polymer is adsorbed on the abrasive grains at 5,000 or more molecules per 1 ?m2 of surface area of the abrasive grains.Type: GrantFiled: May 31, 2012Date of Patent: May 2, 2017Assignee: FUJIMI INCORPORATEDInventors: Yasuyuki Yamato, Youhei Takahashi, Tomohiko Akatsuka
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Patent number: 9640408Abstract: A method for etching a layer in a plasma chamber with an inner injection zone gas feed and an outer injection zone gas feed is provided. The layer is placed in the plasma chamber. A pulsed etch gas is provided from the inner injection zone gas feed at a first frequency, wherein flow of pulsed etch gas from the inner injection zone gas feed is ramped down to zero. The pulsed etch gas is provided from the outer injection zone gas feed at the first frequency and simultaneous with and out of phase with the pulsed etch gas from the inner injection zone gas feed. The etch gas is formed into a plasma to etch the layer, simultaneous with the providing the pulsed etch gas from the inner injection zone gas feed and providing the pulsed gas from the outer interjection zone gas feed.Type: GrantFiled: February 19, 2016Date of Patent: May 2, 2017Assignee: Lam Research CorporationInventors: Saravanapriyan Sriraman, Alexander Paterson
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Patent number: 9640409Abstract: A method for processing a semiconductor substrate includes a) providing a substrate stack including a first layer, a plurality of cores arranged in a spaced relationship on the first layer and one or more underlying layers arranged below the first layer; b) depositing a conformal layer on the first layer and the plurality of cores; c) partially etching the conformal layer to create spacers arranged adjacent to sidewalls of the plurality of cores, wherein the partial etching of the conformal layer causes upper portions of the spacers to have an asymmetric profile; d) selectively etching the plurality of cores relative to the spacers and the first layer; e) depositing polymer film on sidewalls of the spacers; and f) etching the upper portions of the spacers to remove the asymmetric profile and to planarize the upper portions of the spacers.Type: GrantFiled: February 2, 2016Date of Patent: May 2, 2017Assignee: LAM RESEARCH CORPORATIONInventors: Dengliang Yang, Joon Hong Park
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Patent number: 9640410Abstract: According to one embodiment, a pattern formation method includes forming a resist pattern on an underlying film, slimming the resist pattern, forming a pinning portion having affinity for a first polymer by depositing, on a surface of the slimmed resist pattern, an etching product produced by etching the underlying film, forming a neutral, film having affinity for the first polymer and a second polymer on the underlying film after the etching, forming a block copolymer film containing the first polymer and the second polymer on the pinning portion and the neutral film, forming a microphase separation pattern by applying a predetermined process to the block copolymer film to perform microphase separation.Type: GrantFiled: July 24, 2015Date of Patent: May 2, 2017Assignee: Kabushiki Kaisha ToshibaInventor: Yuriko Seino
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Patent number: 9640411Abstract: Method for manufacturing a transistor device comprising a germanium channel material on a silicon based substrate, the method comprising providing a shallow trench isolation (STI) substrate comprising a silicon protrusion embedded in STI dielectric structures, and partially recessing the silicon protrusion in order to provide a trench in between adjacent STI structures, and to provide a V-shaped groove at an upper surface of the recessed protrusion. The method also includes growing a Si1-xGex SRB layer in the trenches, and growing a germanium based channel layer on the Si1-xGex SRB layer. In this example, the Si1-xGex SRB layer comprises a germanium content x that is within the range of 20% to 99%, and the SRB layer has a thickness less than 400 nm. The present disclosure also relates to an associated transistor device.Type: GrantFiled: November 5, 2015Date of Patent: May 2, 2017Assignee: IMEC VZWInventors: Jianwu Sun, Roger Loo
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Patent number: 9640412Abstract: The present invention generally relates to methods and apparatus for processing substrates. Embodiments of the invention include apparatuses for processing a substrate comprising a dynamic heat sink that is substantially transparent to light from a radiant heat source, the dynamic heat sink being positioned near the substrate so the two are coupled. Additional embodiments of the invention are directed to methods of processing a substrate using the apparatuses described.Type: GrantFiled: November 20, 2009Date of Patent: May 2, 2017Assignee: Applied Materials, Inc.Inventors: Wolfgang Aderhold, Joseph M. Ranish, Blake R. Koelmel
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Patent number: 9640413Abstract: Provided is an etching-before-packaging horizontal chip three-dimensional system level metal circuit board structure comprising a metal substrate frame; the metal substrate frame is provided with base islands and pins therein; the front faces of the base islands are provided with chips; the front faces of the chips are connected to the front faces of the pins via metal wires; conductive posts are disposed on the front faces or back faces of the pins; the peripheral areas of the base islands, the areas between the base islands and the pins, the areas between the pins, the areas above the base islands and the pins, the areas below the base islands and the pins, and the exteriors of the chips, the metal wires and the conductive posts are all encapsulated with molding compound.Type: GrantFiled: December 2, 2013Date of Patent: May 2, 2017Assignee: Jiangsu Changjiang Electronics Technology Co., LtdInventors: Steve Xin Liang, Chih-Chung Liang, Yu-Bin Lin, Yaqin Wang, Youhai Zhang