Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Abstract: Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The methods and compositions prepared by the methods can be used as indelible marking materials for use on microelectronic packages and as solder and sealant barriers to prevent overspreading of liquids on the oxide surfaces of microelectronic packages. The polyacrylate polymers are covalently linked to the oxide surface by use during the printing and UV-curing process of an adhesion promoter having as a first domain an oxide-reactive silyl group, bonded via a linker to an acrylate-reactive group.

Abstract: A single- and dual-chamber module-attachable wafer-handling chamber includes: a wafer-handling main chamber equipped with a wafer-handling robot therein, and adaptors for connecting process modules to the wafer-handling main chamber. The adaptors are detachably attached to the sides of the wafer-handling main chamber, respectively, and the process modules are detachably attached to the adaptors, respectively, so that the process modules can be attached to the wafer-handling main chamber, regardless of whether the process modules are of a single-chamber type or dual-chamber type.

Abstract: A cassette transfer apparatus includes a holding unit configured to hold a cassette having a wafer loaded therein, the cassette having at least one stepped part, and the holding unit including at least one holding part configured to have the at least one stepped part placed thereon. The at least one stepped part includes a pair of stepped parts provided at opposite surfaces of the cassette, and the at least one holding part includes a pair of holding parts that extends back and forth and is configured to have the pair of stepped parts placed thereon.

Abstract: An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding applications includes an end effector having a frame member and a floating carrier connected to the frame member with a gap formed therebetween, wherein the floating carrier has a semi-circular interior perimeter. The centered semiconductor wafer pairs are positionable within a processing system using the end effector under robotic control. The centered semiconductor wafer pairs are bonded together without the presence of the end effector in the bonding device.

Abstract: In accordance with an alternative embodiment of the present invention, a method for forming a semiconductor device includes applying a paste over a semiconductor substrate, and forming a ceramic carrier by solidifying the paste. The semiconductor substrate is thinned using the ceramic carrier as a carrier.

Abstract: A method of processing a wafer includes coating the front side of the wafer with a water-soluble liquid resin to form a thin film; fixing the wafer to a protective plate for protecting the front side of the wafer, with a bond material interposed between the protective plate and the thin film; holding by a chuck table the protective plate with the wafer fixed thereto and grinding the back side of the wafer to make the wafer have a predetermined thickness; releasing step of releasing the bond material together with the protective plate to which the wafer has been fixed; and supplying water to the bond material remaining on the front side of the wafer to remove the thin film together with the bond material.

Abstract: Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

Abstract: A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.

Abstract: Integrated circuits and methods for producing the same are provided. In accordance with one embodiment a method of producing an integrated circuit includes forming a trench defined by a first material. The trench is filled with a second material to produce a gap defined within the second material, where the second material is in a solid state. The second material is reflowed within the trench to reduce a volume of the gap, and the second material is then solidified within the trench.

Abstract: Embodiments described herein relate to methods for forming an air gap interconnect. A metal spacer layer is conformally deposited on a substrate having mandrel structures formed thereon. The metal spacer layer is etched to form spacer features and the mandrel structures are removed from the substrate. Various other dielectric deposition, patterning and etching steps may be performed to desirably pattern materials present on the substrate. Ultimately, a trench is formed between adjacent spacer features and a capping layer is deposited over the trench to form an air gap between the adjacent spacer features. For packaging purposes, an interconnect via may be configured to contact at least one of the spacer features adjacent the air gap.

Abstract: Various embodiments provide methods and systems for making and/or cleaning semiconductor devices. In one embodiment, a semiconductor device can be formed including a metal layer and a photoresist polymer. During formation, the semiconductor device can be cleaned in a cleaning chamber by a first cleaning solution provided from a solution supply device. After this cleaning process, a second cleaning solution containing metal ions and/or polymer residues can be produced and processed in a solution processing device to at least partially remove the metal ions and/or polymer residues to produce a third cleaning solution for re-use. In an exemplary fabrication or cleaning system, the solution processing device may be configured connecting to either an inlet or an outlet of the cleaning chamber. After cleaning, the semiconductor device can be processed to include a metal plug or an interconnect wiring.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.

Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate; and forming an ultra-low-dielectric-constant (ULK) dielectric layer on a surface of the substrate. The method also includes etching the ultra-low-dielectric-constant dielectric layer to form a trench in the ultra-low-dielectric-constant dielectric layer; and performing an inert plasma treatment process on a side surface of the trench. Further, the method includes performing a carbonization process on the side surface of the trench; and performing a nitridation process on the side surface of the trench to form a SiCNH layer on the side surface of the trench.

Abstract: A self-aligned repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organometallic compound as a precursor gas. The precursor gas adsorbed on a dielectric layer exposed by defects in a barrier layer is transformed to an insulating metal oxide layer, and the precursor gas adsorbed on the barrier layer is transformed to a metal layer.

Abstract: A method of fabricating a semiconductor device includes: forming a metal layer containing Al; forming an insulating film on the metal layer; forming an opening pattern to the insulating film, the metal layer being exposed in the opening pattern; and forming a wiring layer in the opening pattern, a first portion being disposed between an edge of the wiring layer and an edge of the opening pattern, a width of the first portion being 1 ?m or less, and the metal layer being exposed in the first portion.

Abstract: A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least one major surface of the first metal layer, and forming a second dielectric layer over the first metal layer and the first graphene layer. The method further includes forming an opening in the second dielectric layer which exposes the first metal layer, forming a second metal layer over the second dielectric layer and within the opening, and forming a second graphene layer on at least one major surface of the second metal layer, wherein the second graphene layer is also formed within the opening.

Abstract: Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

Abstract: The disclosed subject matter provides a memory device structure and a fabricating method thereof. The memory device structure includes a substrate including a device region and a peripheral region; multiple gate structures; a first dielectric layer, a second barrier layer, multiple source interconnecting lines, and multiple drain region plugs; a second dielectric layer in the device region include multiple source line plugs, and multiple second drain region plugs, and multiple controlling gate plugs; a third dielectric layer including multiple first conductive layers; a fourth dielectric layer including multiple interconnecting structures; a fifth dielectric layer including multiple second conductive layers; and a sixth dielectric layer including multiple third conductive layers.

Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.

Abstract: A method for processing an electroplated copper film in copper interconnect process is disclosed by the present invention. Firstly, in the copper back-end-of-line interconnect process, the first annealing process for the electroplated copper film is performed at or below 180° C.; then, after the copper back-end-of-line interconnect process, another annealing process with higher temperature (equal or above 240° C.) to the electroplated copper film is performed to make the copper recrystallize, so as to decrease the resistivity of the electroplated copper film and form an interface state having lower resistivity at the interface of the vias bottom, which decrease the contact resistance between the vias and the underlying copper interconnects and further reduce the RC time delay in the vias. The present invention can be applied in the Cu/Low-k back-end-of-line interconnect process and compatible with the standard Cu/Low-k back-end-of-line process integration.

Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

Abstract: A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates.

Abstract: A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

Abstract: Integrated circuits and methods for manufacturing the same are provided. A method for producing an integrated circuit includes forming a first active dummy gate, a second active dummy gate, and an inactive gate overlying a substrate. The first active dummy gate is replaced with a first metal gate, where replacing the first active dummy gate includes planarizing the first metal gate, the second active dummy gate, and the inactive gate. The second active dummy gate is replaced with a second replacement metal after the first active dummy gate was replaced, where the inactive gate remains overlying the substrate.

Abstract: A method for manufacturing a semiconductor device may include the following steps: providing a semiconductor substrate structure; providing a substrate-connecting barrier layer on the semiconductor substrate structure; performing one or more iterations of a composite-layer formation process to provide a gate-connecting barrier layer, wherein the composite-layer formation process comprises: applying a silicon-containing compound set to an outmost existing barrier layer to form an amorphous silicon layer, and forming an overlying barrier layer on the amorphous silicon layer, wherein the substrate-connecting barrier layer is the outmost existing barrier layer for a first iteration of the one or more iterations, and wherein the gate-connecting barrier layer is the overlying barrier layer resulted from a last iteration of the one or more iterations; and providing a conductive gate layer on the gate-connecting barrier layer.

Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.

Abstract: A method for complementary metal oxide semiconductor (CMOS) fin integration includes recessing a fin structure buried in a dielectric fill to form a trench in the dielectric fill having a fin portion remaining at a bottom thereof. A new fin is epitaxially grown in the trench from the fin portion. The new fin included SiGe.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas. Moreover, first through fourth gate insulating layers are on the first through fourth areas, respectively. Amounts of work function control materials in the first through fourth gate insulating layers, nitrogen concentrations in the first through fourth gate insulating layers, and/or thicknesses of the first through fourth gate insulating layers vary among the first through fourth gate insulating layers. Methods for fabricating semiconductor devices are also provided.

Abstract: Provided is a method of fabricating a semiconductor device with a field effect transistor. The method may include forming a first gate electrode and a second gate electrode extending substantially parallel to each other and each crossing a PMOSFET region on a substrate and an NMOSFET region on the substrate; forming an interlayered insulating layer covering the first gate electrode and the second gate electrode; patterning the interlayered insulating layer to form a first sub contact hole on the first gate electrode, the first sub contact hole being positioned between the PMOSFET region and the NMOSFET region, when viewed in a plan view; and patterning the interlayered insulating layer to form a first gate contact hole and to expose a top surface of the second gate electrode, wherein the first sub contact hole and the first gate contact hole form a single communication hole.

Abstract: A method of fabricating a switched-capacitor converter includes providing a semiconductor layer having a top surface and a bottom surface, forming switching elements on the top surface of the semiconductor layer, forming a first insulation layer and first interconnection patterns on the switching elements, forming a second insulation layer over the first insulation layer and the first interconnection patterns, forming a second interconnection pattern over the second insulation layer, forming a third insulation layer over the second insulation layer and the second interconnection pattern, forming third interconnection patterns and a lower interconnection pattern over the bottom surface of the semiconductor layer, forming a capacitor over the lower interconnection pattern, forming a fourth insulation layer over the bottom surface of the semiconductor layer to expose an upper electrode pattern of the capacitor, forming a fifth insulation layer covering the capacitor, and forming pads in the fifth insulation laye

Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a semiconductor substrate; and forming a plurality of semiconductor devices on the semiconductor substrate. The method also includes forming a dielectric layer covering the plurality of the semiconductor devices on the semiconductor substrate; and forming an optical auxiliary layer configured to reflect a portion of a levelness-detecting light and absorb a portion of the levelness detecting light transmitting through the optical auxiliary layer during a levelness-detecting process over the dielectric layer. Further, the method includes forming a photoresist layer over the optical auxiliary layer; and detecting a levelness of the semiconductor substrate and exposing the photoresist layer to form a patterned photoresist layer.

Abstract: A circuit is disclosed that includes a signal-forcing path, a discharging path, a contact probe, a monitoring probe and a switch module. The signal-forcing path is connected to a signal source. The discharging path is connected to a discharging voltage terminal. The contact probe contacts a pad module of an under-test device. The monitoring probe generates a monitored voltage associated with the pad module. The switch module is operated in a discharging mode to connect the contact probe to the discharging path when the monitored voltage does not reach a threshold voltage such that the under-test device is discharged and is operated in an operation mode to connect the contact probe to the signal-forcing path when the monitored voltage reaches the threshold voltage such that a signal generated by the signal source is forced to the under-test device.

Abstract: A film forming apparatus, which forms a thin film formed of a metal oxide on a substrate by alternately supplying a raw material gas formed of an organic material containing a metal and an oxidation gas for oxidizing the organic material to the substrate a plurality of times, within a reaction vessel under a vacuum atmosphere, is provided. A control part outputs a control signal for comparing a moisture concentration detected by a moisture detection part with a set value after initiation of a step of supplying the oxidation gas and before starting a step of supplying the raw material gas, and when the moisture concentration exceeds a set value, for increasing a substitution operation of an atmosphere substitution step.

Abstract: Photoreflectance spectroscopy is used to measure strain at or near the edge of a wafer in a production process. The strain measurement is used to anticipate defects and make prospective corrections in later stages of the production process. Strain measurements are used to associate various production steps with defects to enhance later production processes.

Abstract: A method for reducing light-induced-degradation in manufacturing a solar cell, includes the steps of: (a) irradiating the solar cell with an irradiance; (b) maintaining the solar cell within a temperature range; (c) removing the solar cell away from the irradiance of step (a) after a time; and (d) determining the irradiance, the temperature range, and the time such that the LID is optimally below a predetermined LID.

Abstract: A wafer processing method is provided. The method includes providing a to-be-processed wafer having a first surface with a plurality of the device regions and dicing groove regions between adjacent device regions and a second surface; and providing a capping wafer having a first surface and a second surface. The method also includes bonding the first surface of the capping wafer with the first surface of the to-be-processed wafer. Further, the method includes performing an edge trimming process onto the to-be-processed wafer to cause a radius of the to-be-processed wafer to be smaller than a radius of the capping wafer; and grinding the second surface of the capping wafer. Further, the method also includes cleaning the second surface of the capping wafer; and etching a portion of the grinded and cleaned capping wafer to expose the dicing groove regions on the first surface of the to-be-processed wafer.

Abstract: An electronic component housing package has an input/output member that is bonded to a hole part of a frame body via a brazing material. This input/output member has a top surface that is bonded to first side wall parts and a second side wall part inside the first side wall parts, and the top surface is provided with a narrow part having a narrow width at a portion that is bonded to the first side wall part. When the input/output member is bonded, the flow of the brazing material on the top surface can be controlled by the narrow part.

Abstract: This invention is provided with: a circuit board which is placed in a package and in which an electric circuit including a power semiconductor element is formed; and a plurality of press-fit terminals each having a wire-bond portion electrically connected in the package to the electric circuit, a press-fit portion for making electrical connection with an apparatus to be connected, and a body portion whose one end portion continuous to the wire bond portion is internally fastened to the package and whose other end portion supports the press-fit portion so as to place the press-fit portion away from the package; wherein in each of the plurality of press-fit terminals, at a portion in the body portion exposed from the package, there is formed a constriction portion that is constricted from both sides in a direction perpendicular to the center line, so as to leave a portion around the center line.

Abstract: A semiconductor device includes an insulating substrate having a circuit plate on a principal surface thereof; a semiconductor element fixed to the circuit plate; an external terminal having one end fixed to the circuit plate; and a printed circuit board facing the principal surface of the insulating substrate, and having a through-hole for passing through the external terminal. A rigidity of a peripheral region of the through-hole is lower than a rigidity of other regions.

Abstract: A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding.

Abstract: Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.

Abstract: A device is provided, which includes a wiring structure including a first surface and a second surface opposite the first surface. The device also includes a first semiconductor die on the first surface of the wiring structure where the first semiconductor die includes first power amplifier unit. The device further includes a second semiconductor die on the first surface of the wiring structure where the second semiconductor has a second power amplifier unit and is spaced apart from the first semiconductor die. In addition, the device includes a first input port at the second surface of the wiring structure, and a first conductor in the wiring structure to electrically connect the first input port to the first semiconductor die and the second semiconductor die.

Abstract: Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

Abstract: A semiconductor device includes a leadframe and a semiconductor chip including a contact. The contact faces the leadframe and is electrically coupled to the leadframe via solder. The semiconductor device includes a solder barrier adjacent to the first contact and an edge of the chip.

Abstract: A semiconductor device of the present invention includes: a first substrate (1) on which a power semiconductor element (2) is mounted; a heat-dissipating plate (12); an insulating layer (11) disposed between the first substrate (1) and the heat-dissipating plate (12); and molding resin (4) that molds the first substrate (1), the heat-dissipating plate (12), and the insulating layer (11). The heat-dissipating plate (12) has a first surface opposite to the insulating layer (12), the first surface being exposed from the molding resin (4). The insulating layer (11) has a curved area (11a) that is curved to the first surface and an end that is located in the molding resin (4).

Abstract: A power module includes a substrate DMB (Direct Metal Bonded). A novel bridging DMB is surface mounted to the substrate DMB along with power semiconductor device dice. The top metal layer of the bridging DMB has one or more islands to which bonding wires can connect. In one example, an electrical path extends from a module terminal, through a first bonding wire and to a first location on a strip-shaped island, through the island to a second location, and from the second location and through a second bonding wire. The strip-shaped island of the bridging DMB serves as a section of the overall electrical path. Another bonding wire of a separate electrical path passes transversely over the strip-shaped island without any wire crossing any other wire. Use of the bridging DMB promotes bonding wire mechanical strength as well as heat sinking from bonding wires down to the substrate DMB.

Abstract: Disclosed herein is a device that includes a first wiring provided as a first-level wiring layer and elongated in a first direction; and a first wiring pad provided as the first-level wiring layer, the first wiring pad being rectangular and including a first side edge that is elongated in the first direction and a second side edge that is elongated in a second direction crossing to the first direction, the first side edge being greater in length than the second side edge, the first wiring pad being greater in length in the second direction than the first wiring.

Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry. The semiconductor device includes a built-up substrate lead frame having, a sub-structure of I/O terminals and a die attach area, the I/O terminals and die attach area enveloped in a molding compound, the die attach area having exposed areas to facilitate device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads; connection traces electrically couple the I/O terminals with one another, said connection traces having facilitated electroplating of exposed vertical surfaces of the I/O terminals during assembly, said connection traces being severed after assembly. An envelope of molding compound encapsulates the device die onto the built-up substrate lead frame.