Abstract: Disclosed is method of manufacturing an array substrate, including steps of: forming a thin film transistor on a substrate through a patterning process; and on the substrate on which the thin film transistor has been formed, forming an organic transparent insulation layer including a first via hole and a first transparent electrode layer disposed above the organic transparent insulation layer and including a second via hole through one patterning process, wherein the centers of the first via hole and the second via hole coincide with each other in a thickness direction of the substrate, and a projection of the first via hole on the substrate is within a projection of the second via hole on the substrate.

Abstract: The present invention provides a TFT substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different. According to the different functions of the different TFTs, the present invention employs different working structures for the Switching TFT and the Driving TFT to respectively implement deposition and photolithography, and employs different materials for the active layers of the Switching TFT and the Driving TFT to differentiate the electrical properties of different TFTs in the TFT substrate. Accordingly, the accurate control to the OLED with lowest cost can be realized.

Abstract: A thin film transistor (TFT) device is provided. The TFT device includes a first conductive layer including a gate electrode and a connection pad. The TFT device further includes a first dielectric layer covering the gate electrode, and a semiconductor layer disposed on the dielectric layer and overlapping the gate electrode. The TFT device further includes a second dielectric layer disposed on the semiconductor layer and the first dielectric layer so as to expose first and second portions of the semiconductor layer and the connection pad. The TFT device further includes a second conductive layer which includes a source electrode portion covering the first portion of the semiconductor layer; a pixel electrode portion extending to the source electrode portion; a drain electrode portion covering the second portion of the semiconductor layer; and an interconnection portion disposed on the connection pad and extending to the drain electrode portion.

Abstract: An array substrate includes a base substrate including a display area and a peripheral area adjacent to the display area, a gate line extending in a first direction, a data line extending in a second direction crossing the gate line, a switching element electrically connected to the gate and data lines, a color filter pattern and a dummy color pattern in the display and peripheral areas, respectively, a pixel electrode on the color filter pattern, and a light blocking pattern including a black matrix pattern partially overlapping the color filter pattern and a black boundary pattern overlapping the dummy color pattern. The black boundary pattern covers the peripheral area and includes a first portion which overlaps the dummy color pattern and a second portion which does not overlap the dummy color pattern. A cross-sectional thickness of the first portion is smaller than that of the second portion.

Abstract: An LCD panel, an array substrate and a manufacturing method for TFT are disclosed. The method includes: providing a substrate; forming a first metal layer on the substrate, wherein the first metal layer includes an aluminum metal layer, an aluminum oxide layer and a molybdenum metal layer stacked sequentially; patterning the first metal layer to form a gate electrode of a TFT; sequentially forming a gate insulation layer, a semiconductor layer and an ohmic contact layer on the gate electrode; forming a second metal layer on the ohmic contact layer; and patterning the second metal layer to form a source electrode and a drain electrode of the TFT. The present invention can inhibit hillock generated by the aluminum metal layer in a high temperature environment, avoid the short circuit generated among the gate, the source and the drain electrodes of the TFT to ensure the display quality of an image.

Abstract: Displays can be fabricated using driver transistors formed with high quality semiconductor channel materials, and switching transistors formed with low quality semiconductor channel materials. The driver transistors can require high forward current to drive emission of the OLED pixels, but might not require very low leakage current. The switching transistors can require low leakage current to allow the pixel capacitor to retain the signal level for accurate OLED device emission, preventing abnormal displays or cross talks.

Abstract: The present invention provides a method for manufacturing the N-type TFT, which includes subjecting a light shielding layer to a grating like patternization treatment for controlling different zones of a poly-silicon layer to induce difference of crystallization so as to have different zones of the poly-silicon layer forming crystalline grains having different sizes, whereby through just one operation of ion doping, different zones of the poly-silicon layer have differences in electrical resistivity due to difference of grain size generated under the condition of identical doping concentration to provide an effect equivalent to an LDD structure for providing the TFT with a relatively low leakage current and improved reliability. Further, since only one operation of ion injection is involved, the manufacturing time and manufacturing cost can be saved, damages of the poly-silicon layer can be reduced, the activation time can be shortened, thereby facilitating the manufacture of flexible display devices.

Abstract: A method for manufacturing an array substrate includes coating a photoresist onto an insulation layer including a gate insulation layer and an etch stop layer, wherein the gate insulation layer covers a conductive pattern and the etch stop layer covers a semiconductive pattern. The method further includes exposing the photoresist to form a photoresist partially-reserved region and a photoresist unreserved region. The method further includes performing a first etching process to at least partially remove a portion of the insulation layer located at a position corresponding to the photoresist unreserved region, to form an intermediate hole. The method further includes performing a second etching process to form the first via hole and form the second via hole at a position of the intermediate hole, thereby to reveal the semiconductive pattern and the conductive pattern at positions corresponding to the first via hole and the second via hole, respectively.

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact.

Abstract: An integration method of fabricating optical sensor device and thin film transistor device includes the follow steps. A substrate is provided, and a gate electrode and a bottom electrode are formed on the substrate. A first insulating layer is formed on the gate electrode and the bottom electrode, and the first insulating layer at least partially exposes the bottom electrode. An optical sensing pattern is formed on the bottom electrode. A patterned transparent semiconductor layer is formed on the first insulating layer, wherein the patterned transparent semiconductor layer includes a first transparent semiconductor pattern covering the gate electrode, and a second transparent semiconductor pattern covering the optical sensing pattern. A source electrode and a drain electrode are formed on the first transparent semiconductor pattern.

Abstract: A semiconductor detector device comprises a layer of semiconductor material for generating charge in response to an input event and an array of pixels for collecting charge. Tracks are connected to the pixels to supply signals representing the collected charge to a reader circuit. The pixels are grouped into sets, all the pixels within a set being connected to the same track, the sets of pixels being interwoven so that so that any group of n adjacent pixels capable of collecting charge generated by a single input event is connected to a combination of n tracks that is unique to the group of pixels, where n has a value of one of 2, 3 or 4. This allows detection of position of the area of charge collection on the basis of temporally coincident signals on a combination of at least n tracks.

Abstract: An imaging and pulse detection array includes: a plurality of pixels connected to a controller, the controller being configured to generate an image based on an image signal originating from each pixel in the plurality of pixels and configured to detect a pulse on at least one of the pixels in the plurality of pixels, and each of the pixels in the plurality of pixels including an imaging circuit and a pulse detection circuit, the imaging circuit and the pulse detection circuit including a shared circuit architecture, and wherein the imaging circuit and the pulse detection circuit include a shared portion.

Abstract: A CMOS image sensor including: an array of M×N pixels, the pixels of a same column being connected to a same output track, each pixel including a photodiode, a sense node, a transfer transistor, a reset transistor, and a read circuit; and a test circuit including an assembly of N elementary reference cells respectively connected to the N output tracks of the sensor, each cell including a resistor, a sense node, a transfer transistor, a reset transistor, and a read circuit, the N resistors being series-connected between first and second nodes of application of a reference voltage.

Abstract: With an image sensor in which the amplifier circuit is disposed at each pixel, there is such an issue that the threshold voltage of the transistor fluctuates so that the signal voltage fluctuates because a voltage is continuously applied between the source and the gate of the transistor at all times when using the amorphous thin film semiconductor as the transistor that constitutes an amplifier circuit. The gate-source potential of the TFT that constitutes the amplifier circuit is controlled so that the gate terminal voltage becomes smaller than the source terminal voltage in an integrating period where the pixels accumulate the signals, and controlled so that the gate terminal voltage becomes larger than the source terminal voltage in a readout period where the pixels output the signals.

Abstract: Embodiments of an image sensor pixel that includes a photosensitive element, a floating diffusion region, and a transfer device. The photosensitive element is disposed in a substrate layer for accumulating an image charge in response to light. The floating diffusion region is dispose in the substrate layer to receive the image charge from the photosensitive element. The transfer device is disposed between the photosensitive element and the floating diffusion region to selectively transfer the image charge from the photosensitive element to the floating diffusion region. The transfer device includes a buried channel device including a buried channel gate disposed over a buried channel dopant region. The transfer device also includes a surface channel device including a surface channel gate disposed over a surface channel region. The surface channel device is in series with the buried channel device. The surface channel gate has the opposite polarity of the buried channel gate.

Abstract: A near-infrared-absorbing composition includes a copper compound and a compound having a partial structure represented by Formula (1) described below and the content of the copper compound is in a range of 3×10?3 mol to 1 mol in relation to 1 g of the compound having the partial structure represented by Formula (1) described below, in Formula (1), R1 represents a hydrogen atom or an organic group.

Abstract: A gate electrode of a field effect transistor is formed. Next, an offset spacer film with a double-layer structure including a silicon oxide film as a lower-layer film and a silicon nitride film as an upper-layer film is formed on a sidewall surface of the gate electrode. The silicon nitride film serves as a supply source of an element for terminating dangling bonds of silicon in a device formation region. Next, treatment for leaving the offset spacer film intact or treatment for removing the silicon nitride film of the offset spacer film is performed. Thereafter, a sidewall insulating film is formed on the sidewall surface of the gate electrode.

Abstract: There is provided a solid-state imaging device including: one or more photoelectric conversion elements provided on side of a first surface of a semiconductor substrate; a through electrode coupled to the one or more photoelectric conversion elements, and provided between the first surface and a second surface of the semiconductor substrate; and an amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate, in which the one or more photoelectric conversion elements are coupled to a gate of the amplifier transistor and the floating diffusion via the through electrode.

Abstract: The disclosure provides at least a photoelectric converter, and at least a photoelectric conversion system, including a plurality of pixels each having a photoelectric conversion layer and a pixel electrode; a first electrode that supplies a potential to each of the photoelectric conversion layers of a plurality of pixels in common, and a second electrode that supplies the potential to the first electrode. The pixel electrode is formed by metal and further includes an oxide conductive film disposed between the first electrode and the second electrode.

Abstract: Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters.

Abstract: One innovation includes an IR sensor having an array of sensor pixels to convert light into current, each sensor pixel of the array including a photodetector region, a lens configured to focus light into the photodetector region, the lens adjacent to the photodetector region so light propagates through the lens and into the photodetector region, and a substrate disposed with photodetector region between the substrate and the lens, the substrate having one or more transistors formed therein. The sensor also includes reflective structures positioned between at least a portion of the substrate and at least a portion of the photodetector region and such that at least a portion of the photodetector region is between the one or more reflective structures and the lens, the one or more reflective structures configured to reflect the light that has passed through at least a portion of the photodetector region into the photodetector region.

Abstract: Embodiments described herein relate to a dual-band photodetector. The dual-band photodetector includes a barrier layer (10) disposed between two infrared absorption layers (8, 12) wherein the barrier layer (10) is lattice matched to at least one of the infrared absorption layers (8, 12). Furthermore, one infrared absorption layer includes dilute nitride to adjust the band gap to a desired cut-off wavelength while maintaining valence-band alignment with the barrier layer. Embodiments also relate to a system and processes for producing the photodetector fabricated from semiconductor materials.

Abstract: A system and method for a multi-sensor pixel architecture for use in a digital imaging system is described. The system includes at least one semiconducting layer for absorbing radiation incident on opposites of the at least one semiconducting layer along with a set of electrodes on one side of the semiconducting layer for transmitting a signal associated with the radiation absorbed by the semiconducting layer.

Abstract: A method for fabricating a signal-separating CFA includes forming a multi-height CFA on a substrate. The multi-height CFA includes a plurality of tall spectral filters and a plurality of short spectral filters. Each of the tall spectral filters is taller than each of the short spectral filters. The method also includes disposing a spectral-blocking layer on the multi-height CFA, and planarizing the spectral-blocking layer to expose a top surface of each of the plurality of tall spectral filters.

Abstract: A method for producing an image pickup apparatus includes: a process of cutting an image pickup chip substrate where electrode pads are formed around each of the light receiving sections to fabricate image pickup chips; a process of bonding image pickup chips determined as non-defective products to a glass wafer to fabricate a joined wafer; a process of filling a sealing member among the image pickup chips on the joined wafer; a machining process including a thinning a thickness of the joined wafer to flatten a machining surface and a forming through-hole interconnections, each of which is connected to each of the electrode pads; a process of forming a plurality of external connection electrodes, each of which is connected to each of the electrode pads via each of the through-hole interconnections; and a process of cutting the joined wafer.

Abstract: A demodulation pixel improves the charge transport speed and sensitivity by exploiting two effects of charge transport in silicon in order to achieve the before-mentioned optimization. The first one is a transport method based on the CCD gate principle. However, this is not limited to CCD technology, but can be realized also in CMOS technology. The charge transport in a surface or even a buried channel close to the surface is highly efficient in terms of speed, sensitivity and low trapping noise. In addition, by activating a majority carrier current flowing through the substrate, another drift field is generated below the depleted CCD channel. This drift field is located deeply in the substrate, acting as an efficient separator for deeply photo-generated electron-hole pairs. Thus, another large amount of minority carriers is transported to the diffusion nodes at high speed and detected.

Abstract: A high-voltage flip LED chip and a manufacturing method thereof. In the high-voltage flip LED chip, a P-N electrode connecting metal block is filled into an isolation trench between two adjacent chip units and is respectively filled into a first electrode hole of one chip unit and a second electrode hole of the other chip unit to serially connect the two adjacent chips.

Abstract: Provided is a memory device, including a memory element on a substrate; a protection insulating pattern covering a side surface of the memory element and exposing a top surface of the memory element; an upper mold layer on the protection insulating pattern; and a bit line on and connected to the memory element, the bit line extending in a first direction, the protection insulating pattern including a first protection insulating pattern covering a lower side surface of the memory element; and a second protection insulating pattern covering an upper side surface of the memory element and including a different material from the first protection insulating pattern.

Abstract: A semiconductor device including a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.

Abstract: A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first and second non-functional regions. The first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region. A magnetic memory element is formed in the first functional region and a logic element is formed in the second functional region. A plurality of magnetism controllable dummy structures are formed in the proximate memory region and external logic circuit region. The magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.

Abstract: A high density non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A deep trench MOS (“metal-oxide-semiconductor”) transistor having a floating gate with small area relative to conventional devices can be provided, in addition to a capacitor or transistor acting as a capacitor. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. The small area floating gate of the deep trench transistor can be connected to the other side of the selector device, and a second transistor can be connected in series with the deep trench transistor.

Abstract: Resistive random access memory (ReRAM) array includes line stack structures located over a substrate. The line stack structures are laterally spaced apart along a first horizontal direction, and extend along a second horizontal direction that is different from the first horizontal direction. Each line stack structure comprises an alternating plurality of word lines and bit lines. An intervening line stack including a memory material line structure, an intrinsic semiconductor material line structure, and a doped semiconductor material line structure is located between each vertically neighboring pair of a word line and a bit line within the alternating plurality of word lines and bit lines. A two-dimensional array of vertical selector lines functions as gate electrodes that activates a semiconductor channel between a word line and a bit line. Resistance of the memory material line structure contacting the activated semiconductor channel can be programmed and/or measured within the ReRAM array.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate and a display layer formed over the substrate and including a pixel area and a non-pixel area. The display also includes an upper thin layer formed over the display layer, wherein the upper thin layer comprises at least first and second conductive layers and a dielectric layer formed between the first and second conductive layers, wherein the second conductive layer is closer to the substrate than the first conductive layer, and wherein the first and second conductive layers are patterned as a touch electrode. The display further includes a light absorbing member at least partially overlapping the non-pixel area and not overlapping the pixel area.

Abstract: A CCM substrate (1) includes as a light-emitting layer on a substrate (11) a red conversion layer (142), a green conversion layer (152), and a light scattering layer (162); a bank (13) which stands on the substrate (11), and partitions the light-emitting layer; and a light-transmission suppressing layer (10) which is formed on at least a portion of a side surface (13a) of the bank (13) which is a surface facing the light-emitting layer, and suppresses light transmission between the light-emitting layers (the red conversion layer (142), the green conversion layer (152), and the light scattering layer (162)) with the bank (13) interposed therebetween by causing the light to be reflected or scattered, in which the light-transmission suppressing layer (10) is comprising metal or metal salt, and the bank (13) has a group, an ion, or a molecule for immobilizing the metal or metal ion.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a stretchable substrate, a thin film transistor (TFT) formed over the stretchable substrate and including a plurality of electrodes, an OLED electrically connected to the TFT and including a plurality of electrodes, and a plurality of interconnection lines connected to the electrodes of the OLED and the TFT. At least one of the interconnection lines is configured to move in a stretching direction and rotate an electrode selected from the electrodes of the OLED and the TFT connected to the at least one interconnection line.

Abstract: An OLED apparatus includes: a substrate; a TFT on the substrate and comprising an active layer, a first interlayer insulating layer between the gate electrode and the source and drain electrodes and comprising an inorganic material; a second interlayer insulating layer between the first interlayer insulating layer and the source and drain electrodes and comprising an organic material; a first organic layer covering the source and drain electrodes; a second organic layer on the first organic layer; a capacitor comprising a first electrode comprising a same material as the gate electrode, and a second electrode comprising a same material as the source and drain electrodes; a pixel electrode in an opening in an area that does not overlap with the TFT and the capacitor, and contacting one of the source and drain electrodes; an emission layer on the pixel electrode; and an opposite electrode on the emission layer.

Abstract: A potential of a gate of a driving transistor is fixed, and the driving transistor is operated in a saturation region, so that a current is supplied thereto anytime. A current control transistor operating in a linear region is disposed serially with the driving transistor, and a video signal for transmitting a signal of emission or non-emission of the pixel is input to a gate of the current control transistor via a switching transistor.

Abstract: The present application discloses an array substrate comprising a base substrate; and a plurality of rows of pixel units and a plurality of rows of reset signal lines on the base substrate, every two adjacent rows of pixel units share one reset signal line. Every two adjacent rows of pixel units and a reset signal line between the two adjacent rows of pixel units constitute a pixel unit group, each pixel unit group comprises a plurality of columns of pixel units.

Abstract: There are provided a semiconductor unit that prevents connection failure caused by a wiring substrate to improve reliability, a method of manufacturing the semiconductor unit, and an electronic apparatus including the semiconductor unit. The semiconductor unit includes: a device substrate including a functional device and an electrode; a first wiring substrate electrically connected to the functional device through the electrode; and a second wiring substrate electrically connected to the functional device through the first wiring substrate.

Abstract: A display device and method of manufacturing the same are disclosed. In one aspect, the display device includes a first line extending in a first direction, a second line extending in a second direction, and a storage capacitor electrically connected to at least one of the first line and the second line. The first line includes a first metal pattern layer extending in the first direction, an intermediate insulating layer formed over the first metal pattern layer, and a second metal pattern layer formed over the first metal pattern layer and the intermediate insulating layer. The second metal pattern layer extends in the first direction. The first line also includes a third metal pattern layer electrically connecting the first metal pattern layer to the second metal pattern layer via a contact hole.

Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

Abstract: A method includes forming an insulating carrier substrate, forming a shallow trench isolation region within the insulating carrier substrate, and forming a plurality of gate recesses on the shallow trench isolation region. The plurality of gate recesses is formed by forming a plurality of dummy gates on the shallow trench isolation region and etching the plurality of dummy gates. The method further includes depositing a metal resistor layer within the plurality of gate recesses.

Abstract: Vertical metal-insulator-metal (MIM) capacitors include a metal conductor including a sidewall; a high k dielectric layer on the sidewall of the metal conductor; and a vertically oriented metal layer on the high k dielectric layer. Also disclosed are methods for fabricating the vertical MIM capacitor, wherein a single patterning/mask process can used to fabricate the vertical MIM capacitor structure.

Abstract: In accordance with some embodiments of the present disclosure, a capacitor structure of an integrated circuit chip includes an insulation layer, a first electrode, and a second electrode. The insulation layer includes an insulation partition and has a first trench and a second trench separated from the first trench by the insulation partition. The first electrode is disposed in the first trench. The second electrode is disposed in the second trench. The first electrode first electrode is arranged along a spiral trajectory and surrounds a spiral channel. The second electrode is disposed within the spiral channel.

Abstract: A metal-insulator-metal capacitor is provided in a replacement metal gate module having a gate cap formed on a gate. The capacitor includes a first electrode formed within a portion of the gate using a metal forming the gate. The first electrode has a horizontal component and a stack rising from at least a portion of the horizontal component. The capacitor further includes an insulator formed within a recess. The recess is formed to have a lower portion and walls rising from edges of the lower portion. The lower portion is formed on a different portion of the horizontal component than the stack. The walls are formed adjacent to a sidewall of the stack and a portion of the gate cap. The capacitor also includes a second electrode formed within the recess and on the insulator.

Abstract: A semiconductor device of the present invention is a semiconductor device having a semiconductor layer comprising a wide band gap semiconductor, wherein the semiconductor layer includes: a first conductivity-type source region, a second conductivity-type channel region and a first conductivity-type drain region, which are formed in this order from the surface side of the semiconductor layer; a source trench lying from the surface of the semiconductor layer through the source region and the channel region to the drain region; a gate insulating film formed so as to contact the channel region; a gate electrode facing the channel region with the gate insulating film interposed therebetween; and a first breakdown voltage holding region of a second conductivity type formed selectively on the side face or the bottom face of the source trench, and the semiconductor device includes a barrier formation layer, which is joined with the drain region in the source trench, for forming, by junction with the drain region, a j

Abstract: A semiconductor device of trench gate type is provided that has achieved both large on-current and high off-state breakdown voltage. Around trench T and between it and electric field relaxation p-layer 16, low resistance n-layer 17 is provided. Low resistance n-layer 17 is formed deeper than trench T, and shallower than electric field relaxation p-layer 16, being connected to n?-layer (drift layer) 12 just thereunder, and thus low resistance n-layer 17 and n?-layer 12 are integrated to form a drift layer. Although low resistance n-layer 17 is n-type as is n?-layer 12, donor concentration thereof is set higher than that of n?-layer 12, thereby low resistance n-layer 17 having a resistivity lower than that of n?-layer 12. This low resistance n-layer 17 is provided in on-current path (between electric field relaxation p-layer 16 and trench T), whereby low resistance n-layer 17 can lower the resistance to on-current.

Abstract: The present invention provides some methods for forming at least two different nanowire structures with different diameters on one substrate. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) and the drive currents of a nanowire field effect transistor, in this invention, at least two nanowire structures with different diameters can be formed on one substrate. Therefore, in the following steps, these nanowire structures can be applied in different nanowire field effect transistors with different Vt and drive currents. This way, the flexibility of the nanowire field effect transistors can be improved.

Abstract: A MOSFET includes: a SiC layer including one main surface and provided with a plurality of contact regions; and a plurality of source electrodes formed in contact with the contact regions. In the MOSFET, in a plan view of the one main surface, a plurality of cells including the contact regions and the source electrodes are formed adjacent to one another, each of the plurality of cells having an outer circumferential shape that is a shape of hexagon including a long axis. According to the MOSFET, a contact resistance between each contact region and each source electrode can be further reduced, thereby attaining a more improved electrical property.

Abstract: It is an object to provide the techniques capable of restraining avalanche breakdown at cells opposite to a corner portion of a gate pad. A MOSFET is provided with a corner cell, which is disposed in a region opposite to a corner portion of a gate pad in a planar view, and an internal cell, which is disposed in a region in the opposite side of the gate pad with respect to the corner cell. In a contour shape of the corner cell, a longest distance among distances each of which is shortest distance between a longest side and each of sides opposite to the longest side is equal to or less than two times of a length of one of equal sides or a short side of the internal cell.